zhouhua e4fdbdfeec Initial JPEG-LS FPGA encoder baseline with tooling and timeout fix

2026-04-16 18:55:08 +08:00

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Initial JPEG-LS FPGA encoder baseline with tooling and timeout fix

2026-04-16 18:55:08 +08:00

fpga

Initial JPEG-LS FPGA encoder baseline with tooling and timeout fix

2026-04-16 18:55:08 +08:00

img

Initial JPEG-LS FPGA encoder baseline with tooling and timeout fix

2026-04-16 18:55:08 +08:00

tools

Initial JPEG-LS FPGA encoder baseline with tooling and timeout fix

2026-04-16 18:55:08 +08:00

.gitignore

Initial JPEG-LS FPGA encoder baseline with tooling and timeout fix

2026-04-16 18:55:08 +08:00

Description

在xilinx7v690t芯片用verilog实现的jpeg_ls算法，参考charls的C语言实现，采用动态误差调节，目标是200M像素/秒@250MHz的高吞吐实现

56 MiB

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