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Tighten ratio-4 dynamic NEAR thresholds

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zhouhua
2026-04-16 22:08:40 +08:00
parent 3a80e8bf9f
commit 5fedb4fb23
2 changed files with 89 additions and 29 deletions
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86
fpga/verilog/jls_near_ctrl.sv
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@@ -105,8 +105,11 @@ module jls_near_ctrl #(
// approximate the project review buckets while avoiding wide constant
// multipliers in the 250 MHz strip-control path.
logic [47:0] target_plus_one_eighth;
logic [47:0] target_plus_one_thirtysecond;
logic [47:0] target_plus_one_quarter;
logic [47:0] target_plus_one_half;
logic [47:0] target_plus_three_quarters;
logic [47:0] target_times_two_plus_quarter;
logic [47:0] target_times_two;
logic [47:0] target_times_three;
logic [47:0] target_times_five;
@@ -260,29 +263,54 @@ module jls_near_ctrl #(
end
always_comb begin
target_plus_one_thirtysecond = pending_target_bits_sum +
{5'b00000, pending_target_bits_sum[47:5]};
target_plus_one_eighth = pending_target_bits_sum + {3'b000, pending_target_bits_sum[47:3]};
target_plus_one_quarter = pending_target_bits_sum + {2'b00, pending_target_bits_sum[47:2]};
target_plus_one_half = pending_target_bits_sum + {1'b0, pending_target_bits_sum[47:1]};
target_plus_three_quarters = pending_target_bits_sum +
{1'b0, pending_target_bits_sum[47:1]} +
{2'b00, pending_target_bits_sum[47:2]};
target_times_two = {pending_target_bits_sum[46:0], 1'b0};
target_times_two_plus_quarter = {pending_target_bits_sum[46:0], 1'b0} +
{2'b00, pending_target_bits_sum[47:2]};
target_times_three = pending_target_bits_sum + {pending_target_bits_sum[46:0], 1'b0};
target_times_five = pending_target_bits_sum + {pending_target_bits_sum[45:0], 2'b00};
end
always_comb begin
first_strip_level_next = NEAR_LEVEL_31;
if (pending_actual_bits_sum <= target_plus_one_eighth) begin
first_strip_level_next = NEAR_LEVEL_0;
end else if (pending_actual_bits_sum <= target_plus_one_quarter) begin
first_strip_level_next = NEAR_LEVEL_1;
end else if (pending_actual_bits_sum <= target_plus_one_half) begin
first_strip_level_next = NEAR_LEVEL_2;
end else if (pending_actual_bits_sum <= target_times_two) begin
first_strip_level_next = NEAR_LEVEL_4;
end else if (pending_actual_bits_sum <= target_times_three) begin
first_strip_level_next = NEAR_LEVEL_8;
end else if (pending_actual_bits_sum <= target_times_five) begin
first_strip_level_next = NEAR_LEVEL_16;
end
case (active_ratio)
RATIO_1_TO_4, RATIO_1_TO_8: begin
if (pending_actual_bits_sum <= target_plus_one_eighth) begin
first_strip_level_next = NEAR_LEVEL_0;
end else if (pending_actual_bits_sum <= target_plus_one_quarter) begin
first_strip_level_next = NEAR_LEVEL_1;
end else if (pending_actual_bits_sum <= target_plus_one_half) begin
first_strip_level_next = NEAR_LEVEL_2;
end else if (pending_actual_bits_sum <= target_plus_three_quarters) begin
first_strip_level_next = NEAR_LEVEL_4;
end else if (pending_actual_bits_sum <= target_times_two_plus_quarter) begin
first_strip_level_next = NEAR_LEVEL_8;
end
end
default: begin
if (pending_actual_bits_sum <= target_plus_one_eighth) begin
first_strip_level_next = NEAR_LEVEL_0;
end else if (pending_actual_bits_sum <= target_plus_one_quarter) begin
first_strip_level_next = NEAR_LEVEL_1;
end else if (pending_actual_bits_sum <= target_plus_one_half) begin
first_strip_level_next = NEAR_LEVEL_2;
end else if (pending_actual_bits_sum <= target_times_two) begin
first_strip_level_next = NEAR_LEVEL_4;
end else if (pending_actual_bits_sum <= target_times_three) begin
first_strip_level_next = NEAR_LEVEL_8;
end else if (pending_actual_bits_sum <= target_times_five) begin
first_strip_level_next = NEAR_LEVEL_16;
end
end
endcase
end
always_comb begin
@@ -294,16 +322,36 @@ module jls_near_ctrl #(
always_comb begin
step_up_one_level = 1'b0;
if (pending_actual_bits_sum > target_plus_sixteenth) begin
step_up_one_level = 1'b1;
end
case (active_ratio)
RATIO_1_TO_4, RATIO_1_TO_8: begin
if (pending_actual_bits_sum > target_plus_one_thirtysecond) begin
step_up_one_level = 1'b1;
end
end
default: begin
if (pending_actual_bits_sum > target_plus_sixteenth) begin
step_up_one_level = 1'b1;
end
end
endcase
end
always_comb begin
step_up_two_levels = 1'b0;
if (pending_actual_bits_sum > target_plus_quarter) begin
step_up_two_levels = 1'b1;
end
case (active_ratio)
RATIO_1_TO_4, RATIO_1_TO_8: begin
if (pending_actual_bits_sum > target_plus_one_eighth) begin
step_up_two_levels = 1'b1;
end
end
default: begin
if (pending_actual_bits_sum > target_plus_quarter) begin
step_up_two_levels = 1'b1;
end
end
endcase
end
always_comb begin