#----------------------------------------------------------- # Vivado v2023.2 (64-bit) # SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023 # IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 # SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 # Start of session at: Tue May 26 23:39:08 2026 # Process ID: 21364 # Current directory: E:/proj/proj_521/can_parse_ctrl # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent11772 E:\proj\proj_521\can_parse_ctrl\can_parse_ctrl.xpr # Log file: E:/proj/proj_521/can_parse_ctrl/vivado.log # Journal file: E:/proj/proj_521/can_parse_ctrl\vivado.jou # Running On: DESKTOP-UONVKRQ, OS: Windows, CPU Frequency: 2400 MHz, CPU Physical cores: 4, Host memory: 8434 MB #----------------------------------------------------------- start_gui open_project E:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.xpr WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at E:/app/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.1 available at E:/app/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.1/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.0 available at E:/app/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.0/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.1 available at E:/app/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.1/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at E:/app/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.1 available at E:/app/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.1/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at E:/app/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at E:/app/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at E:/app/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at E:/app/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available Scanning sources... Finished scanning sources INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/proj/proj_518/FPGA_DESIGN_IP/FPGA_DESIGN_IP'. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'E:/app/Xilinx/Vivado/2023.2/data/ip'. open_project: Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1578.176 ; gain = 403.965 update_compile_order -fileset sources_1 open_bd_design {E:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd} Reading block design file ... Adding component instance block -- xilinx.com:user:can_init:1.0 - can_init_0 Adding component instance block -- xilinx.com:user:can_rx_parse_axi:1.0 - can_rx_parse_axi_0 Adding component instance block -- xilinx.com:user:uart_parse_real:1.0 - uart_parse_real_0 Adding component instance block -- xilinx.com:user:ibufg_user:1.0 - ibufg_user_0 Adding component instance block -- xilinx.com:ip:clk_wiz:6.0 - clk_wiz_0 Adding component instance block -- xilinx.com:ip:util_vector_logic:2.0 - util_vector_logic_0 Adding component instance block -- xilinx.com:ip:util_vector_logic:2.0 - util_vector_logic_1 Adding component instance block -- xilinx.com:ip:axi_interconnect:2.1 - axi_interconnect_0 Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - xbar Adding component instance block -- xilinx.com:ip:can:5.1 - can_0 Adding component instance block -- xilinx.com:ip:can:5.1 - can_1 Successfully read diagram from block design file open_bd_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 1662.086 ; gain = 37.461 regenerate_bd_layout validate_bd_design INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_0 clk_wiz propagate ERROR: [BD 41-237] Bus Interface property FREQ_HZ does not match between /can_0/CAN_S_AXI_LITE(100000000) and /axi_interconnect_0/xbar/M00_AXI(10000000) ERROR: [BD 41-237] Bus Interface property FREQ_HZ does not match between /can_1/CAN_S_AXI_LITE(100000000) and /axi_interconnect_0/xbar/M01_AXI(10000000) ERROR: [Common 17-39] 'validate_bd_design' failed due to earlier errors. delete_bd_objs [get_bd_intf_nets S00_AXI_1] [get_bd_intf_nets axi_interconnect_0_M00_AXI] [get_bd_intf_nets axi_interconnect_0_M01_AXI] [get_bd_intf_nets S01_AXI_1] [get_bd_cells axi_interconnect_0] startgroup create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 endgroup set_property location {6 1239 241} [get_bd_cells smartconnect_0] set_property CONFIG.NUM_MI {2} [get_bd_cells smartconnect_0] connect_bd_intf_net [get_bd_intf_pins smartconnect_0/S00_AXI] [get_bd_intf_pins can_init_0/m_axi] connect_bd_intf_net [get_bd_intf_pins smartconnect_0/S01_AXI] [get_bd_intf_pins can_rx_parse_axi_0/m_axi] connect_bd_intf_net [get_bd_intf_pins smartconnect_0/M00_AXI] [get_bd_intf_pins can_0/CAN_S_AXI_LITE] connect_bd_intf_net [get_bd_intf_pins smartconnect_0/M01_AXI] [get_bd_intf_pins can_1/CAN_S_AXI_LITE] connect_bd_net [get_bd_pins smartconnect_0/aclk] [get_bd_pins ibufg_user_0/clk_out] connect_bd_net [get_bd_pins smartconnect_0/aresetn] [get_bd_pins util_vector_logic_1/Res] regenerate_bd_layout validate_bd_design CRITICAL WARNING: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_0: The device(s) attached to /M00_AXI do not share a common clock domain with this smartconnect instance. Modify the clock domain values of the attached device(s) or re-customize this AXI SmartConnect instance to add a new clock pin and connect it to the same clock source of the IP attached to /M00_AXI to prevent further clock DRC violations. CRITICAL WARNING: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_0: The device(s) attached to /M01_AXI do not share a common clock domain with this smartconnect instance. Modify the clock domain values of the attached device(s) or re-customize this AXI SmartConnect instance to add a new clock pin and connect it to the same clock source of the IP attached to /M01_AXI to prevent further clock DRC violations. CRITICAL WARNING: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_0: The device(s) attached to /S00_AXI do not share a common clock domain with this smartconnect instance. Modify the clock domain values of the attached device(s) or re-customize this AXI SmartConnect instance to add a new clock pin and connect it to the same clock source of the IP attached to /S00_AXI to prevent further clock DRC violations. CRITICAL WARNING: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_0: The device(s) attached to /S00_AXI do not share a common clock frequency with this smartconnect instance. Modify the clock frequency values of the attached device(s) or re-customize this AXI SmartConnect instance to add a new clock pin and connect it to the same clock source of the IP attached to /S00_AXI to prevent further clock DRC violations. CRITICAL WARNING: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_0: The device(s) attached to /S01_AXI do not share a common clock domain with this smartconnect instance. Modify the clock domain values of the attached device(s) or re-customize this AXI SmartConnect instance to add a new clock pin and connect it to the same clock source of the IP attached to /S01_AXI to prevent further clock DRC violations. CRITICAL WARNING: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_0: The device(s) attached to /S01_AXI do not share a common clock frequency with this smartconnect instance. Modify the clock frequency values of the attached device(s) or re-customize this AXI SmartConnect instance to add a new clock pin and connect it to the same clock source of the IP attached to /S01_AXI to prevent further clock DRC violations. INFO: [BD 5-943] Reserving offset range <0x44A0_0000 [ 64K ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing. INFO: [BD 5-943] Reserving offset range <0x44A1_0000 [ 64K ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing. INFO: [BD 5-943] Reserving offset range <0x44A0_0000 [ 64K ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing. INFO: [BD 5-943] Reserving offset range <0x44A1_0000 [ 64K ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing. INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_0: SmartConnect design_1_smartconnect_0_0 is in Low-Area Mode. xit::source_ipfile: Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1772.883 ; gain = 47.816 INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_0 clk_wiz propagate CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow. Please check your design and connect them as needed: /can_rx_parse_axi_0/tlm_record_task_id /can_rx_parse_axi_0/tlm_downlink_task_id /can_rx_parse_axi_0/tlm_disk_status /can_rx_parse_axi_0/tlm_cam_dt_status /can_rx_parse_axi_0/tlm_lvds /can_rx_parse_axi_0/tlm_reconfig /can_rx_parse_axi_0/tlm_fpga_temp /can_rx_parse_axi_0/tlm_compress_flash validate_bd_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:20 . Memory (MB): peak = 1779.094 ; gain = 54.027 regenerate_bd_layout validate_bd_design -force CRITICAL WARNING: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_0: The device(s) attached to /M00_AXI do not share a common clock domain with this smartconnect instance. Modify the clock domain values of the attached device(s) or re-customize this AXI SmartConnect instance to add a new clock pin and connect it to the same clock source of the IP attached to /M00_AXI to prevent further clock DRC violations. CRITICAL WARNING: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_0: The device(s) attached to /M01_AXI do not share a common clock domain with this smartconnect instance. Modify the clock domain values of the attached device(s) or re-customize this AXI SmartConnect instance to add a new clock pin and connect it to the same clock source of the IP attached to /M01_AXI to prevent further clock DRC violations. CRITICAL WARNING: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_0: The device(s) attached to /S00_AXI do not share a common clock domain with this smartconnect instance. Modify the clock domain values of the attached device(s) or re-customize this AXI SmartConnect instance to add a new clock pin and connect it to the same clock source of the IP attached to /S00_AXI to prevent further clock DRC violations. CRITICAL WARNING: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_0: The device(s) attached to /S00_AXI do not share a common clock frequency with this smartconnect instance. Modify the clock frequency values of the attached device(s) or re-customize this AXI SmartConnect instance to add a new clock pin and connect it to the same clock source of the IP attached to /S00_AXI to prevent further clock DRC violations. CRITICAL WARNING: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_0: The device(s) attached to /S01_AXI do not share a common clock domain with this smartconnect instance. Modify the clock domain values of the attached device(s) or re-customize this AXI SmartConnect instance to add a new clock pin and connect it to the same clock source of the IP attached to /S01_AXI to prevent further clock DRC violations. CRITICAL WARNING: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_0: The device(s) attached to /S01_AXI do not share a common clock frequency with this smartconnect instance. Modify the clock frequency values of the attached device(s) or re-customize this AXI SmartConnect instance to add a new clock pin and connect it to the same clock source of the IP attached to /S01_AXI to prevent further clock DRC violations. INFO: [BD 5-943] Reserving offset range <0x44A0_0000 [ 64K ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing. INFO: [BD 5-943] Reserving offset range <0x44A1_0000 [ 64K ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing. INFO: [BD 5-943] Reserving offset range <0x44A0_0000 [ 64K ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing. INFO: [BD 5-943] Reserving offset range <0x44A1_0000 [ 64K ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing. INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_0: SmartConnect design_1_smartconnect_0_0 is in Low-Area Mode. xit::source_ipfile: Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1805.191 ; gain = 22.523 INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_0 clk_wiz propagate CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow. Please check your design and connect them as needed: /can_rx_parse_axi_0/tlm_record_task_id /can_rx_parse_axi_0/tlm_downlink_task_id /can_rx_parse_axi_0/tlm_disk_status /can_rx_parse_axi_0/tlm_cam_dt_status /can_rx_parse_axi_0/tlm_lvds /can_rx_parse_axi_0/tlm_reconfig /can_rx_parse_axi_0/tlm_fpga_temp /can_rx_parse_axi_0/tlm_compress_flash validate_bd_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1811.484 ; gain = 32.391 generate_target all [get_files E:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd] INFO: [BD 41-1662] The design 'design_1.bd' is already validated. Therefore parameter propagation will not be re-run. CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow. Please check your design and connect them as needed: /can_rx_parse_axi_0/tlm_record_task_id /can_rx_parse_axi_0/tlm_downlink_task_id /can_rx_parse_axi_0/tlm_disk_status /can_rx_parse_axi_0/tlm_cam_dt_status /can_rx_parse_axi_0/tlm_lvds /can_rx_parse_axi_0/tlm_reconfig /can_rx_parse_axi_0/tlm_fpga_temp /can_rx_parse_axi_0/tlm_compress_flash WARNING: [BD 41-2671] The dangling interface net will not be written out to the BD file. WARNING: [BD 41-2671] The dangling interface net will not be written out to the BD file. Wrote : Wrote : Verilog Output written to : e:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/synth/design_1.v Verilog Output written to : e:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/sim/design_1.v Verilog Output written to : e:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v INFO: [BD 41-1029] Generation completed for the IP Integrator block can_init_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block can_rx_parse_axi_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block uart_parse_real_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block ibufg_user_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_wiz_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block util_vector_logic_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block util_vector_logic_1 . INFO: [BD 41-1029] Generation completed for the IP Integrator block can_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block can_1 . Exporting to file e:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/hw_handoff/design_1_smartconnect_0_0.hwh Generated Hardware Definition File e:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/synth/design_1_smartconnect_0_0.hwdef INFO: [BD 41-1029] Generation completed for the IP Integrator block smartconnect_0 . Exporting to file e:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh Generated Hardware Definition File e:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/synth/design_1.hwdef generate_target: Time (s): cpu = 00:01:07 ; elapsed = 00:01:39 . Memory (MB): peak = 2182.520 ; gain = 371.035 catch { config_ip_cache -export [get_ips -all design_1_can_init_0_0] } INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_can_init_0_0 catch { config_ip_cache -export [get_ips -all design_1_can_rx_parse_axi_0_0] } INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_can_rx_parse_axi_0_0 catch { config_ip_cache -export [get_ips -all design_1_uart_parse_real_0_0] } INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_uart_parse_real_0_0 catch { config_ip_cache -export [get_ips -all design_1_ibufg_user_0_0] } INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ibufg_user_0_0 catch { config_ip_cache -export [get_ips -all design_1_clk_wiz_0_0] } INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_clk_wiz_0_0 catch { config_ip_cache -export [get_ips -all design_1_util_vector_logic_0_0] } INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_util_vector_logic_0_0 catch { config_ip_cache -export [get_ips -all design_1_util_vector_logic_0_1] } INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_util_vector_logic_0_1 catch { config_ip_cache -export [get_ips -all design_1_can_0_2] } INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_can_0_2 catch { config_ip_cache -export [get_ips -all design_1_can_0_3] } INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_can_0_3 catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_0] } INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_smartconnect_0_0 export_ip_user_files -of_objects [get_files E:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet create_ip_run [get_files -of_objects [get_fileset sources_1] E:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd] launch_runs design_1_can_0_2_synth_1 design_1_can_0_3_synth_1 design_1_can_init_0_0_synth_1 design_1_can_rx_parse_axi_0_0_synth_1 design_1_clk_wiz_0_0_synth_1 design_1_ibufg_user_0_0_synth_1 design_1_smartconnect_0_0_synth_1 design_1_uart_parse_real_0_0_synth_1 design_1_util_vector_logic_0_0_synth_1 design_1_util_vector_logic_0_1_synth_1 -jobs 8 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_can_0_2 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_can_0_3 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_can_init_0_0 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_can_rx_parse_axi_0_0 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_clk_wiz_0_0 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ibufg_user_0_0 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_smartconnect_0_0 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_uart_parse_real_0_0 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_util_vector_logic_0_0 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_util_vector_logic_0_1 [Tue May 26 23:46:39 2026] Launched design_1_can_0_2_synth_1, design_1_can_0_3_synth_1, design_1_can_init_0_0_synth_1, design_1_can_rx_parse_axi_0_0_synth_1, design_1_clk_wiz_0_0_synth_1, design_1_ibufg_user_0_0_synth_1, design_1_smartconnect_0_0_synth_1, design_1_uart_parse_real_0_0_synth_1, design_1_util_vector_logic_0_0_synth_1, design_1_util_vector_logic_0_1_synth_1... Run output will be captured here: design_1_can_0_2_synth_1: E:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.runs/design_1_can_0_2_synth_1/runme.log design_1_can_0_3_synth_1: E:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.runs/design_1_can_0_3_synth_1/runme.log design_1_can_init_0_0_synth_1: E:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.runs/design_1_can_init_0_0_synth_1/runme.log design_1_can_rx_parse_axi_0_0_synth_1: E:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.runs/design_1_can_rx_parse_axi_0_0_synth_1/runme.log design_1_clk_wiz_0_0_synth_1: E:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.runs/design_1_clk_wiz_0_0_synth_1/runme.log design_1_ibufg_user_0_0_synth_1: E:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.runs/design_1_ibufg_user_0_0_synth_1/runme.log design_1_smartconnect_0_0_synth_1: E:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.runs/design_1_smartconnect_0_0_synth_1/runme.log design_1_uart_parse_real_0_0_synth_1: E:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.runs/design_1_uart_parse_real_0_0_synth_1/runme.log design_1_util_vector_logic_0_0_synth_1: E:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.runs/design_1_util_vector_logic_0_0_synth_1/runme.log design_1_util_vector_logic_0_1_synth_1: E:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.runs/design_1_util_vector_logic_0_1_synth_1/runme.log launch_runs: Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 2182.520 ; gain = 0.000 export_simulation -of_objects [get_files E:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd] -directory E:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.ip_user_files/sim_scripts -ip_user_files_dir E:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.ip_user_files -ipstatic_source_dir E:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.ip_user_files/ipstatic -lib_map_path [list {modelsim=E:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/modelsim} {questa=E:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/questa} {riviera=E:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/riviera} {activehdl=E:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet