#----------------------------------------------------------- # Vivado v2023.2 (64-bit) # SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023 # IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 # SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 # Start of session at: Tue May 26 23:59:08 2026 # Process ID: 26204 # Current directory: C:/proj/pro_finish/can_parse_ctrl # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent27284 C:\proj\pro_finish\can_parse_ctrl\can_parse_ctrl.xpr # Log file: C:/proj/pro_finish/can_parse_ctrl/vivado.log # Journal file: C:/proj/pro_finish/can_parse_ctrl\vivado.jou # Running On: DESKTOP-EB3SDQ2, OS: Windows, CPU Frequency: 2112 MHz, CPU Physical cores: 16, Host memory: 16817 MB #----------------------------------------------------------- start_gui open_project C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.xpr update_compile_order -fileset sources_1 open_bd_design {C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd} make_wrapper -files [get_files C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd] -top update_ip_catalog -rebuild update_ip_catalog -rebuild set_property ip_repo_paths {} [current_project] update_ip_catalog set_property ip_repo_paths C:/proj/FPGA_DESIGN_IP [current_project] update_ip_catalog reset_run design_1_util_vector_logic_0_1_synth_1 reset_run design_1_can_0_3_synth_1 reset_run design_1_can_init_0_0_synth_1 reset_run design_1_can_rx_parse_axi_0_0_synth_1 reset_run design_1_uart_parse_real_0_0_synth_1 reset_run design_1_ibufg_user_0_0_synth_1 reset_run design_1_clk_wiz_0_0_synth_1 reset_run design_1_util_vector_logic_0_0_synth_1 reset_run design_1_can_0_2_synth_1 reset_run design_1_smartconnect_0_0_synth_1 regenerate_bd_layout validate_bd_design -force make_wrapper -files [get_files C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd] -top add_files -norecurse c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v launch_runs impl_1 -to_step write_bitstream -jobs 24 wait_on_run impl_1 file mkdir C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/constrs_1 file mkdir C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/constrs_1/new close [ open C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/constrs_1/new/can_parse_ctrl.xdc w ] add_files -fileset constrs_1 C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/constrs_1/new/can_parse_ctrl.xdc reset_run synth_1 launch_runs impl_1 -to_step write_bitstream -jobs 24 wait_on_run impl_1 create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd] synth_design -rtl -rtl_skip_mlo -name rtl_1 place_ports rx_i_0 K38 set_property IOSTANDARD HSTL_I_12 [get_ports [list rx_i_0]] set_property IOSTANDARD HSTL_I_12 [get_ports [list rx_i_0]] set_property IOSTANDARD LVCMOS18 [get_ports [list rx_i_0]] set_property IOSTANDARD LVCMOS18 [get_ports [list can_phy_rx_0]] set_property target_constrs_file C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/constrs_1/new/can_parse_ctrl.xdc [current_fileset -constrset] save_constraints -force create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd] refresh_design reset_run synth_1 launch_runs impl_1 -to_step write_bitstream -jobs 24 wait_on_run impl_1 open_bd_design {C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd} get_property CLK_DOMAIN [get_pins design_1_smartconnect_0_0/aclk] get_property CLK_DOMAIN [get_pins design_1_smartconnect_0/aclk] get_pins -hierarchical -filter {NAME=~ *smartconnect*/aclk} get_property CLK_DOMAIN [get_pins design_1_i/can_0/aclk] get_property CLK_DOMAIN [get_pins design_1_i/smartconnect_0/aclk] get_property CLK_DOMAIN [get_pins design_1_i/can_0/aclk] get_pins -of_objects [get_cells design_1_i/can_0] -filter {DIRECTION == IN && NAME =~ *clk*} get_property CLK_DOMAIN [get_pins design_1_i/can_0/s_axi_aclk] get_property CLK_DOMAIN [get_pins design_1_i/can_0/can_clk] get_property CLK_DOMAIN [get_pins design_1_i/smartconnect_0/aclk] get_property CLK_DOMAIN [get_pins design_1_i/can_1/s_axi_aclk] get_property PERIOD [get_clocks -of_objects [get_pins design_1_i/can_0/s_axi_aclk]] write_bd_layout -format pdf -orientation portrait -force C:/Users/zhaoms/Desktop/design_1.pdf set_property ALLOW_COMBINING true [get_pins design_1_smartconnect_0/aclk] set sc_inst [get_bd_cells smartconnect_0] list_property $sc_inst get_property -all CONFIG.* $sc_inst | grep -i clock # 1. 查看当前时钟数量 get_property CONFIG.NUM_CLKS [get_bd_cells smartconnect_0] # 2. 修改为 4 个独立时钟（对应 S00、S01、M00、M01） set_property CONFIG.NUM_CLKS 4 [get_bd_cells smartconnect_0] # 3. 刷新设计 regenerate_bd_layout # 4. 查看新生成的时钟引脚 get_pins -of_objects [get_bd_cells smartconnect_0] -filter {DIRECTION == IN && NAME =~ *aclk*} delete_bd_objs [get_bd_nets clk_in1_0_1] [get_bd_cells ibufg_user_0] undo undo undo delete_bd_objs [get_bd_nets clk_in1_0_1] [get_bd_cells ibufg_user_0] connect_bd_net [get_bd_ports clk_in1_0] [get_bd_pins clk_wiz_0/clk_in1] save_bd_design regenerate_bd_layout regenerate_bd_layout validate_bd_design undo undo undo undo startgroup create_bd_cell -type ip -vlnv xilinx.com:user:ibufg_user:1.0 ibufg_user_1 endgroup delete_bd_objs [get_bd_cells ibufg_user_1] regenerate_bd_layout set_property SOURCE_SET sources_1 [get_filesets sim_1] add_files -fileset sim_1 -norecurse C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/tb_design_1_wrapper.v update_compile_order -fileset sim_1 update_compile_order -fileset sim_1 open_bd_design {C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd} update_ip_catalog -rebuild -scan_changes report_ip_status -name ip_status upgrade_ip [get_ips {design_1_can_init_0_0 design_1_ibufg_user_0_0}] -log ip_upgrade.log export_ip_user_files -of_objects [get_ips {design_1_can_init_0_0 design_1_ibufg_user_0_0}] -no_script -sync -force -quiet generate_target all [get_files C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd] report_ip_status -name ip_status regenerate_bd_layout validate_bd_design report_ip_status -name ip_status update_ip_catalog -rebuild update_ip_catalog -rebuild report_ip_status -name ip_status upgrade_ip -vlnv xilinx.com:user:can_init:1.0 [get_ips design_1_can_init_0_0] -log ip_upgrade.log export_ip_user_files -of_objects [get_ips design_1_can_init_0_0] -no_script -sync -force -quiet generate_target all [get_files C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd] catch { config_ip_cache -export [get_ips -all design_1_can_init_0_0] } catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_0] } catch { config_ip_cache -export [get_ips -all design_1_ibufg_user_0_0] } export_ip_user_files -of_objects [get_files C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd] launch_runs design_1_can_init_0_0_synth_1 design_1_ibufg_user_0_0_synth_1 design_1_smartconnect_0_0_synth_1 -jobs 24 wait_on_run design_1_can_init_0_0_synth_1 wait_on_run design_1_ibufg_user_0_0_synth_1 wait_on_run design_1_smartconnect_0_0_synth_1 export_simulation -of_objects [get_files C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files -ipstatic_source_dir C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/modelsim} {questa=C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/questa} {riviera=C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/riviera} {activehdl=C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet report_ip_status -name ip_status regenerate_bd_layout regenerate_bd_layout startgroup set_property CONFIG.MODE_MSR {0x00000002} [get_bd_cells can_init_0] endgroup save_bd_design regenerate_bd_layout generate_target Simulation [get_files C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd] export_ip_user_files -of_objects [get_files C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet export_simulation -of_objects [get_files C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files -ipstatic_source_dir C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/modelsim} {questa=C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/questa} {riviera=C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/riviera} {activehdl=C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet launch_simulation source tb_design_1_wrapper.tcl current_wave_config {Untitled 1} add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/can_init_0/inst}} restart run 50 ms current_wave_config {Untitled 1} add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/can_rx_parse_axi_0}} restart run 50 ms current_wave_config {Untitled 1} add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/can_init_0/inst}} current_wave_config {Untitled 1} add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst}} restart run 50 ms current_wave_config {Untitled 1} add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0}} open_bd_design {C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd} close_bd_design [get_bd_designs design_1] open_bd_design {C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd} open_bd_design {C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd} close_bd_design [get_bd_designs design_1] open_bd_design {C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd} startgroup create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 endgroup set_property -dict [list \ CONFIG.NUM_MI {2} \ CONFIG.NUM_SI {2} \ ] [get_bd_cells axi_interconnect_0] set_property location {7 1589 500} [get_bd_cells axi_interconnect_0] delete_bd_objs [get_bd_intf_nets can_init_0_m_axi] [get_bd_intf_nets can_rx_parse_axi_0_m_axi] [get_bd_intf_nets smartconnect_0_M00_AXI] [get_bd_intf_nets smartconnect_0_M01_AXI] [get_bd_cells smartconnect_0] set_property location {7 2096 334} [get_bd_cells can_1] connect_bd_intf_net [get_bd_intf_pins can_1/CAN_S_AXI_LITE] -boundary_type upper [get_bd_intf_pins axi_interconnect_0/M01_AXI] connect_bd_intf_net -boundary_type upper [get_bd_intf_pins axi_interconnect_0/M00_AXI] [get_bd_intf_pins can_0/CAN_S_AXI_LITE] connect_bd_intf_net -boundary_type upper [get_bd_intf_pins axi_interconnect_0/S00_AXI] [get_bd_intf_pins can_init_0/m_axi] connect_bd_intf_net -boundary_type upper [get_bd_intf_pins axi_interconnect_0/S01_AXI] [get_bd_intf_pins can_rx_parse_axi_0/m_axi] connect_bd_net [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] -boundary_type upper connect_bd_net [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] -boundary_type upper connect_bd_net [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] -boundary_type upper connect_bd_net [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/S01_ACLK] -boundary_type upper connect_bd_net [get_bd_pins axi_interconnect_0/S01_ACLK] [get_bd_pins ibufg_user_0/clk_out] connect_bd_net [get_bd_pins axi_interconnect_0/S01_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] -boundary_type upper connect_bd_net [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] -boundary_type upper connect_bd_net [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] -boundary_type upper connect_bd_net [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_0/ARESETN] -boundary_type upper connect_bd_net [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins util_vector_logic_1/Res] regenerate_bd_layout validate_bd_design startgroup set_property -dict [list \ CONFIG.CLKOUT2_JITTER {192.113} \ CONFIG.CLKOUT2_PHASE_ERROR {164.985} \ CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {50.000} \ CONFIG.CLKOUT2_USED {true} \ CONFIG.MMCM_CLKOUT1_DIVIDE {20} \ CONFIG.NUM_OUT_CLKS {2} \ ] [get_bd_cells clk_wiz_0] endgroup delete_bd_objs [get_bd_nets ibufg_user_0_clk_out] connect_bd_net [get_bd_pins ibufg_user_0/clk_out] [get_bd_pins clk_wiz_0/clk_in1] connect_bd_net [get_bd_pins clk_wiz_0/clk_out2] [get_bd_pins uart_parse_real_0/clk] connect_bd_net [get_bd_pins clk_wiz_0/clk_out2] [get_bd_pins can_rx_parse_axi_0/aclk] connect_bd_net [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] -boundary_type upper connect_bd_net [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] -boundary_type upper connect_bd_net [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] -boundary_type upper connect_bd_net [get_bd_pins axi_interconnect_0/S01_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] -boundary_type upper connect_bd_net [get_bd_pins can_init_0/clk] [get_bd_pins axi_interconnect_0/S01_ACLK] connect_bd_net [get_bd_pins can_init_0/clk] [get_bd_pins clk_wiz_0/clk_out2] connect_bd_net [get_bd_pins can_0/s_axi_aclk] [get_bd_pins can_1/s_axi_aclk] connect_bd_net [get_bd_pins can_1/s_axi_aclk] [get_bd_pins clk_wiz_0/clk_out2] regenerate_bd_layout validate_bd_design generate_target all [get_files C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd] catch { config_ip_cache -export [get_ips -all design_1_can_init_0_0] } catch { config_ip_cache -export [get_ips -all design_1_clk_wiz_0_0] } catch { config_ip_cache -export [get_ips -all design_1_xbar_0] } export_ip_user_files -of_objects [get_files C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd] launch_runs design_1_can_init_0_0_synth_1 design_1_clk_wiz_0_0_synth_1 design_1_xbar_0_synth_1 -jobs 24 wait_on_run design_1_can_init_0_0_synth_1 wait_on_run design_1_clk_wiz_0_0_synth_1 wait_on_run design_1_xbar_0_synth_1 export_simulation -of_objects [get_files C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files -ipstatic_source_dir C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/modelsim} {questa=C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/questa} {riviera=C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/riviera} {activehdl=C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet close_sim launch_simulation source tb_design_1_wrapper.tcl current_wave_config {Untitled 2} add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/can_rx_parse_axi_0}} restart run 50 ms current_wave_config {Untitled 2} add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/axi_interconnect_0}} restart run 50 ms open_bd_design {C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd} current_wave_config {Untitled 2} add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/can_0}} restart run 50 ms current_wave_config {Untitled 2} add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/can_init_0}} current_wave_config {Untitled 2} add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/axi_interconnect_0}} current_wave_config {Untitled 2} add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/can_init_0}} current_wave_config {Untitled 2} add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/axi_interconnect_0/m00_couplers}} current_wave_config {Untitled 2} add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/axi_interconnect_0/s00_couplers}} open_bd_design {C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd} restart run 50 ms open_bd_design {C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd} open_bd_design {C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd} set_property range 128 [get_bd_addr_segs {can_init_0/m_axi/SEG_can_0_Reg}] set_property offset 0x00000000 [get_bd_addr_segs {can_init_0/m_axi/SEG_can_0_Reg}] set_property range 128 [get_bd_addr_segs {can_init_0/m_axi/SEG_can_1_Reg}] set_property offset 0x00000200 [get_bd_addr_segs {can_init_0/m_axi/SEG_can_1_Reg}] set_property range 512 [get_bd_addr_segs {can_init_0/m_axi/SEG_can_0_Reg}] set_property range 256 [get_bd_addr_segs {can_init_0/m_axi/SEG_can_0_Reg}] set_property range 256 [get_bd_addr_segs {can_init_0/m_axi/SEG_can_1_Reg}] set_property offset 0x0 [get_bd_addr_segs {can_rx_parse_axi_0/m_axi/SEG_can_0_Reg}] set_property range 256 [get_bd_addr_segs {can_rx_parse_axi_0/m_axi/SEG_can_0_Reg}] set_property range 256 [get_bd_addr_segs {can_rx_parse_axi_0/m_axi/SEG_can_1_Reg}] set_property offset 0x200 [get_bd_addr_segs {can_rx_parse_axi_0/m_axi/SEG_can_1_Reg}] save_bd_design regenerate_bd_layout validate_bd_design generate_target all [get_files C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd] catch { config_ip_cache -export [get_ips -all design_1_xbar_0] } export_ip_user_files -of_objects [get_files C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd] launch_runs design_1_xbar_0_synth_1 -jobs 24 wait_on_run design_1_xbar_0_synth_1 export_simulation -of_objects [get_files C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files -ipstatic_source_dir C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/modelsim} {questa=C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/questa} {riviera=C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/riviera} {activehdl=C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet close_sim launch_simulation launch_simulation launch_simulation source tb_design_1_wrapper.tcl current_wave_config {Untitled 3} add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/can_0}} restart run 50 ms current_wave_config {Untitled 3} add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/can_rx_parse_axi_0}} restart restart run 50 ms close_sim startgroup set_property CONFIG.MODE_MSR {0x00000000} [get_bd_cells can_init_0] endgroup generate_target all [get_files C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd] catch { config_ip_cache -export [get_ips -all design_1_can_init_0_0] } catch { [ delete_ip_run [get_ips -all design_1_can_init_0_0] ] } export_ip_user_files -of_objects [get_files C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd] export_simulation -of_objects [get_files C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files -ipstatic_source_dir C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/modelsim} {questa=C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/questa} {riviera=C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/riviera} {activehdl=C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet reset_run synth_1 launch_runs impl_1 -to_step write_bitstream -jobs 24 wait_on_run impl_1