Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 | Date : Sat May 30 10:47:30 2026 | Host : DESKTOP-EB3SDQ2 running 64-bit major release (build 9200) | Command : upgrade_ip | Device : xc7vx690tffg1761-2 --------------------------------------------------------------------------------------------------------------------------------------------- Upgrade Log for IP 'design_1_lvds_rx_0_0' 1. Summary ---------- SUCCESS in the update of design_1_lvds_rx_0_0 (xilinx.com:user:lvds_rx:1.0 (Rev. 2)) to current project options. Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 | Date : Sat May 30 10:38:31 2026 | Host : DESKTOP-EB3SDQ2 running 64-bit major release (build 9200) | Command : upgrade_ip | Device : xc7vx690tffg1761-2 --------------------------------------------------------------------------------------------------------------------------------------------- Upgrade Log for IP 'design_1_lvds_rx_0_0' 1. Summary ---------- SUCCESS in the update of design_1_lvds_rx_0_0 (xilinx.com:user:lvds_rx:1.0 (Rev. 2)) to current project options. Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 | Date : Fri May 29 21:43:08 2026 | Host : DESKTOP-EB3SDQ2 running 64-bit major release (build 9200) | Command : upgrade_ip | Device : xc7vx690tffg1761-2 --------------------------------------------------------------------------------------------------------------------------------------------- Upgrade Log for IP 'design_1_lvds_rx_0_0' 1. Summary ---------- CAUTION (success, with warnings) in the update of design_1_lvds_rx_0_0 (xilinx.com:user:lvds_rx:1.0 (Rev. 2)) to current project options. After upgrade, an IP may have parameter and port differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality. Also, please review the updated IP instantiation template to ensure proper connectivity, and update your design if required. 2. Connection Warnings ---------------------- Detected external port differences while upgrading 'design_1_lvds_rx_0_0'. These changes may impact your design. -Upgrade has removed port 'ssp_csn' -Upgrade has removed port 'ssp_data' Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 | Date : Fri May 29 21:41:18 2026 | Host : DESKTOP-EB3SDQ2 running 64-bit major release (build 9200) | Command : upgrade_ip | Device : xc7vx690tffg1761-2 --------------------------------------------------------------------------------------------------------------------------------------------- Upgrade Log for IP 'design_1_lvds_rx_0_0' 1. Summary ---------- CAUTION (success, with warnings) in the update of design_1_lvds_rx_0_0 (xilinx.com:user:lvds_rx:1.0 (Rev. 2)) to current project options. After upgrade, an IP may have parameter and port differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality. Also, please review the updated IP instantiation template to ensure proper connectivity, and update your design if required. 2. Connection Warnings ---------------------- Detected external port differences while upgrading 'design_1_lvds_rx_0_0'. These changes may impact your design. -Upgrade has removed port 'ssp_clk' -Upgrade has added port 'lvds_rx_clk_n' -Upgrade has added port 'lvds_rx_clk_p' -Upgrade has added port 'lvds_rx_csn_n' -Upgrade has added port 'lvds_rx_csn_p' -Upgrade has added port 'lvds_rx_data_n' -Upgrade has added port 'lvds_rx_data_p' Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 | Date : Fri May 29 20:47:24 2026 | Host : DESKTOP-EB3SDQ2 running 64-bit major release (build 9200) | Command : upgrade_ip | Device : xc7vx690tffg1761-2 --------------------------------------------------------------------------------------------------------------------------------------------- Upgrade Log for IP 'design_1_lvds_rx_0_0' 1. Summary ---------- SUCCESS in the update of design_1_lvds_rx_0_0 (xilinx.com:user:lvds_rx:1.0 (Rev. 2)) to current project options. Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 | Date : Fri May 29 15:57:27 2026 | Host : DESKTOP-EB3SDQ2 running 64-bit major release (build 9200) | Command : upgrade_ip | Device : xc7vx690tffg1761-2 --------------------------------------------------------------------------------------------------------------------------------------------- Upgrade Log for IP 'design_1_lvds_rx_0_0' 1. Summary ---------- SUCCESS in the update of design_1_lvds_rx_0_0 (xilinx.com:user:lvds_rx:1.0 (Rev. 2)) to current project options. Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 | Date : Fri May 29 13:21:25 2026 | Host : DESKTOP-EB3SDQ2 running 64-bit major release (build 9200) | Command : upgrade_ip | Device : xc7vx690tffg1761-2 --------------------------------------------------------------------------------------------------------------------------------------------- Upgrade Log for IP 'design_1_lvds_rx_0_0' 1. Summary ---------- SUCCESS in the update of design_1_lvds_rx_0_0 (xilinx.com:user:lvds_rx:1.0 (Rev. 2)) to current project options. Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 | Date : Fri May 29 11:17:33 2026 | Host : DESKTOP-EB3SDQ2 running 64-bit major release (build 9200) | Command : upgrade_ip | Device : xc7vx690tffg1761-2 --------------------------------------------------------------------------------------------------------------------------------------------- Upgrade Log for IP 'design_1_lvds_rx_0_0' 1. Summary ---------- SUCCESS in the upgrade of design_1_lvds_rx_0_0 (xilinx.com:user:lvds_rx:1.0) from (Rev. 1) to (Rev. 2) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 | Date : Fri May 29 10:48:20 2026 | Host : DESKTOP-EB3SDQ2 running 64-bit major release (build 9200) | Command : upgrade_ip | Device : xc7vx690tffg1761-2 --------------------------------------------------------------------------------------------------------------------------------------------- Upgrade Log for IP 'design_1_lvds_rx_0_0' 1. Summary ---------- CAUTION (success, with warnings) in the upgrade of design_1_lvds_rx_0_0 (xilinx.com:user:lvds_rx:1.0) from (Rev. 2) to (Rev. 1) After upgrade, an IP may have parameter differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality. 2. Customization warnings ------------------------- Parameter 'FIFO_DEPTH' is no longer present on the upgraded IP 'design_1_lvds_rx_0_0', and cannot be set to '64' 3. Debug Commands ----------------- The following debug information can be passed to Vivado as Tcl commands, in order to validate or debug the output of the upgrade flow. You may consult any warnings from within this upgrade, and alter or remove the configuration parameter(s) which caused the warning; then execute the Tcl commands, and use the IP Customization GUI to verify the IP configuration. create_ip -vlnv xilinx.com:user:lvds_rx:1.0 -user_name design_1_lvds_rx_0_0 set_property -dict "\ CONFIG.ADDR_WIDTH {12} \ CONFIG.CHKSUM_EN {0} \ CONFIG.Component_Name {design_1_lvds_rx_0_0} \ CONFIG.FIFO_WIDTH {8} \ CONFIG.STREAM_WIDTH {8} \ CONFIG.aresetn.INSERT_VIP {0} \ CONFIG.aresetn.POLARITY {ACTIVE_LOW} \ CONFIG.clk.ASSOCIATED_BUSIF {m_axis} \ CONFIG.clk.ASSOCIATED_PORT {} \ CONFIG.clk.ASSOCIATED_RESET {} \ CONFIG.clk.CLK_DOMAIN {/clk_wiz_0_clk_out1} \ CONFIG.clk.FREQ_HZ {50000000} \ CONFIG.clk.FREQ_TOLERANCE_HZ {0} \ CONFIG.clk.INSERT_VIP {0} \ CONFIG.clk.PHASE {0.0} \ CONFIG.m_axis.CLK_DOMAIN {/clk_wiz_0_clk_out1} \ CONFIG.m_axis.FREQ_HZ {50000000} \ CONFIG.m_axis.HAS_TKEEP {1} \ CONFIG.m_axis.HAS_TLAST {1} \ CONFIG.m_axis.HAS_TREADY {1} \ CONFIG.m_axis.HAS_TSTRB {1} \ CONFIG.m_axis.INSERT_VIP {0} \ CONFIG.m_axis.LAYERED_METADATA {undef} \ CONFIG.m_axis.PHASE {0.0} \ CONFIG.m_axis.TDATA_NUM_BYTES {1} \ CONFIG.m_axis.TDEST_WIDTH {0} \ CONFIG.m_axis.TID_WIDTH {0} \ CONFIG.m_axis.TUSER_WIDTH {0} \ CONFIG.ssp_clk.ASSOCIATED_BUSIF {} \ CONFIG.ssp_clk.ASSOCIATED_PORT {} \ CONFIG.ssp_clk.ASSOCIATED_RESET {} \ CONFIG.ssp_clk.CLK_DOMAIN {design_1_util_ds_buf_0_0_IBUF_OUT} \ CONFIG.ssp_clk.FREQ_HZ {100000000} \ CONFIG.ssp_clk.FREQ_TOLERANCE_HZ {0} \ CONFIG.ssp_clk.INSERT_VIP {0} \ CONFIG.ssp_clk.PHASE {0.0} " [get_ips design_1_lvds_rx_0_0] Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 | Date : Thu May 28 20:48:54 2026 | Host : DESKTOP-EB3SDQ2 running 64-bit major release (build 9200) | Command : upgrade_ip | Device : xc7vx690tffg1761-2 --------------------------------------------------------------------------------------------------------------------------------------------- Upgrade Log for IP 'design_1_lvds_rx_0_0' 1. Summary ---------- SUCCESS in the update of design_1_lvds_rx_0_0 (xilinx.com:user:lvds_rx:1.0 (Rev. 2)) to current project options. Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 | Date : Thu May 28 10:12:28 2026 | Host : DESKTOP-EB3SDQ2 running 64-bit major release (build 9200) | Command : upgrade_ip | Device : xc7vx690tffg1761-2 --------------------------------------------------------------------------------------------------------------------------------------------- Upgrade Log for IP 'design_1_uart_parse_real_0_0' 1. Summary ---------- SUCCESS in the update of design_1_uart_parse_real_0_0 (xilinx.com:user:uart_parse_real:1.0 (Rev. 2)) to current project options. Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 | Date : Wed May 27 20:04:14 2026 | Host : DESKTOP-EB3SDQ2 running 64-bit major release (build 9200) | Command : upgrade_ip | Device : xc7vx690tffg1761-2 --------------------------------------------------------------------------------------------------------------------------------------------- Upgrade Log for IP 'design_1_uart_parse_real_0_0' 1. Summary ---------- SUCCESS in the update of design_1_uart_parse_real_0_0 (xilinx.com:user:uart_parse_real:1.0 (Rev. 2)) to current project options. Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 | Date : Wed May 27 13:03:03 2026 | Host : DESKTOP-EB3SDQ2 running 64-bit major release (build 9200) | Command : upgrade_ip | Device : xc7vx690tffg1761-2 --------------------------------------------------------------------------------------------------------------------------------------------- Upgrade Log for IP 'design_1_can_init_0_0' 1. Summary ---------- SUCCESS in the update of design_1_can_init_0_0 (xilinx.com:user:can_init:1.0 (Rev. 2)) to current project options. Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 | Date : Wed May 27 12:57:49 2026 | Host : DESKTOP-EB3SDQ2 running 64-bit major release (build 9200) | Command : upgrade_ip | Device : xc7vx690tffg1761-2 --------------------------------------------------------------------------------------------------------------------------------------------- Upgrade Log for IP 'design_1_ibufg_user_0_0' 1. Summary ---------- SUCCESS in the update of design_1_ibufg_user_0_0 (xilinx.com:user:ibufg_user:1.0 (Rev. 2)) to current project options. Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 | Date : Wed May 27 12:57:49 2026 | Host : DESKTOP-EB3SDQ2 running 64-bit major release (build 9200) | Command : upgrade_ip | Device : xc7vx690tffg1761-2 --------------------------------------------------------------------------------------------------------------------------------------------- Upgrade Log for IP 'design_1_can_init_0_0' 1. Summary ---------- SUCCESS in the update of design_1_can_init_0_0 (xilinx.com:user:can_init:1.0 (Rev. 2)) to current project options. Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 | Date : Tue May 26 23:28:00 2026 | Host : DESKTOP-UONVKRQ running 64-bit major release (build 9200) | Command : upgrade_ip | Device : xc7vx690tffg1761-2 --------------------------------------------------------------------------------------------------------------------------------------------- Upgrade Log for IP 'design_1_can_rx_parse_axi_0_0' 1. Summary ---------- SUCCESS in the update of design_1_can_rx_parse_axi_0_0 (xilinx.com:user:can_rx_parse_axi:1.0 (Rev. 2)) to current project options.