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zhaoms
2026-05-27 15:44:58 +08:00
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can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/elab.rtd Normal file
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can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_can_0_2_stub.v Normal file
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "can_v5_1_1,Vivado 2023.2" *)
module design_1_can_0_2(can_clk, can_phy_rx, can_phy_tx,
ip2bus_intrevent, s_axi_aclk, s_axi_aresetn, s_axi_awaddr, s_axi_awvalid, s_axi_awready,
s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready, s_axi_bresp, s_axi_bvalid,
s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready, s_axi_rdata, s_axi_rresp,
s_axi_rvalid, s_axi_rready);
input can_clk /* synthesis syn_isclock = 1 */;
input can_phy_rx;
output can_phy_tx;
output ip2bus_intrevent;
input s_axi_aclk /* synthesis syn_isclock = 1 */;
input s_axi_aresetn;
input [7:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [7:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
endmodule

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can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_can_0_3_stub.v Normal file
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "can_v5_1_1,Vivado 2023.2" *)
module design_1_can_0_3(can_clk, can_phy_rx, can_phy_tx,
ip2bus_intrevent, s_axi_aclk, s_axi_aresetn, s_axi_awaddr, s_axi_awvalid, s_axi_awready,
s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready, s_axi_bresp, s_axi_bvalid,
s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready, s_axi_rdata, s_axi_rresp,
s_axi_rvalid, s_axi_rready);
input can_clk /* synthesis syn_isclock = 1 */;
input can_phy_rx;
output can_phy_tx;
output ip2bus_intrevent;
input s_axi_aclk /* synthesis syn_isclock = 1 */;
input s_axi_aresetn;
input [7:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [7:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
endmodule

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can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_can_init_0_0_stub.v Normal file
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "can_init,Vivado 2023.2" *)
module design_1_can_init_0_0(clk, rst_n, m_axi_awvalid, m_axi_awready,
m_axi_awaddr, m_axi_wvalid, m_axi_wready, m_axi_wdata, m_axi_wstrb, m_axi_bvalid,
m_axi_bready, init_done, state);
input clk /* synthesis syn_isclock = 1 */;
input rst_n;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_awaddr;
output m_axi_wvalid;
input m_axi_wready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
input m_axi_bvalid;
output m_axi_bready;
output init_done;
output [5:0]state;
endmodule

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can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_can_rx_parse_axi_0_0_stub.v Normal file
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "can_rx_parse_axi,Vivado 2023.2" *)
module design_1_can_rx_parse_axi_0_0(aclk, aresetn, m_axi_araddr, m_axi_arvalid,
m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready, m_axi_awaddr,
m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, m_axi_wready,
m_axi_bresp, m_axi_bvalid, m_axi_bready, tlm_record_task_id, tlm_downlink_task_id,
tlm_disk_status, tlm_cam_dt_status, tlm_async_serial, tlm_lvds, tlm_reconfig,
tlm_fpga_temp, tlm_compress_flash);
input aclk /* synthesis syn_isclock = 1 */;
input aresetn;
output [31:0]m_axi_araddr;
output m_axi_arvalid;
input m_axi_arready;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rvalid;
output m_axi_rready;
output [31:0]m_axi_awaddr;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
input [31:0]tlm_record_task_id;
input [31:0]tlm_downlink_task_id;
input [15:0]tlm_disk_status;
input [439:0]tlm_cam_dt_status;
input [47:0]tlm_async_serial;
input [47:0]tlm_lvds;
input [55:0]tlm_reconfig;
input [15:0]tlm_fpga_temp;
input [7:0]tlm_compress_flash;
endmodule

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can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_clk_wiz_0_0_stub.v Normal file
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module design_1_clk_wiz_0_0(clk_out1, reset, locked, clk_in1);
output clk_out1 /* synthesis syn_isclock = 1 */;
input reset;
output locked;
input clk_in1;
endmodule

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can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_ibufg_user_0_0_stub.v Normal file
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ibufg_user,Vivado 2023.2" *)
module design_1_ibufg_user_0_0(sys_clk, clk_out);
input sys_clk;
output clk_out /* synthesis syn_isclock = 1 */;
endmodule

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can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_smartconnect_0_0_stub.v Normal file
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "bd_48ac,Vivado 2023.2" *)
module design_1_smartconnect_0_0(aclk, aresetn, S00_AXI_awaddr, S00_AXI_awprot,
S00_AXI_awvalid, S00_AXI_awready, S00_AXI_wdata, S00_AXI_wstrb, S00_AXI_wvalid,
S00_AXI_wready, S00_AXI_bresp, S00_AXI_bvalid, S00_AXI_bready, S01_AXI_awaddr,
S01_AXI_awprot, S01_AXI_awvalid, S01_AXI_awready, S01_AXI_wdata, S01_AXI_wstrb,
S01_AXI_wvalid, S01_AXI_wready, S01_AXI_bresp, S01_AXI_bvalid, S01_AXI_bready,
S01_AXI_araddr, S01_AXI_arprot, S01_AXI_arvalid, S01_AXI_arready, S01_AXI_rdata,
S01_AXI_rresp, S01_AXI_rvalid, S01_AXI_rready, M00_AXI_awaddr, M00_AXI_awprot,
M00_AXI_awvalid, M00_AXI_awready, M00_AXI_wdata, M00_AXI_wstrb, M00_AXI_wvalid,
M00_AXI_wready, M00_AXI_bresp, M00_AXI_bvalid, M00_AXI_bready, M00_AXI_araddr,
M00_AXI_arprot, M00_AXI_arvalid, M00_AXI_arready, M00_AXI_rdata, M00_AXI_rresp,
M00_AXI_rvalid, M00_AXI_rready, M01_AXI_awaddr, M01_AXI_awprot, M01_AXI_awvalid,
M01_AXI_awready, M01_AXI_wdata, M01_AXI_wstrb, M01_AXI_wvalid, M01_AXI_wready,
M01_AXI_bresp, M01_AXI_bvalid, M01_AXI_bready, M01_AXI_araddr, M01_AXI_arprot,
M01_AXI_arvalid, M01_AXI_arready, M01_AXI_rdata, M01_AXI_rresp, M01_AXI_rvalid,
M01_AXI_rready);
input aclk /* synthesis syn_isclock = 1 */;
input aresetn;
input [31:0]S00_AXI_awaddr;
input [2:0]S00_AXI_awprot;
input S00_AXI_awvalid;
output S00_AXI_awready;
input [31:0]S00_AXI_wdata;
input [3:0]S00_AXI_wstrb;
input S00_AXI_wvalid;
output S00_AXI_wready;
output [1:0]S00_AXI_bresp;
output S00_AXI_bvalid;
input S00_AXI_bready;
input [31:0]S01_AXI_awaddr;
input [2:0]S01_AXI_awprot;
input S01_AXI_awvalid;
output S01_AXI_awready;
input [31:0]S01_AXI_wdata;
input [3:0]S01_AXI_wstrb;
input S01_AXI_wvalid;
output S01_AXI_wready;
output [1:0]S01_AXI_bresp;
output S01_AXI_bvalid;
input S01_AXI_bready;
input [31:0]S01_AXI_araddr;
input [2:0]S01_AXI_arprot;
input S01_AXI_arvalid;
output S01_AXI_arready;
output [31:0]S01_AXI_rdata;
output [1:0]S01_AXI_rresp;
output S01_AXI_rvalid;
input S01_AXI_rready;
output [7:0]M00_AXI_awaddr;
output [2:0]M00_AXI_awprot;
output M00_AXI_awvalid;
input M00_AXI_awready;
output [31:0]M00_AXI_wdata;
output [3:0]M00_AXI_wstrb;
output M00_AXI_wvalid;
input M00_AXI_wready;
input [1:0]M00_AXI_bresp;
input M00_AXI_bvalid;
output M00_AXI_bready;
output [7:0]M00_AXI_araddr;
output [2:0]M00_AXI_arprot;
output M00_AXI_arvalid;
input M00_AXI_arready;
input [31:0]M00_AXI_rdata;
input [1:0]M00_AXI_rresp;
input M00_AXI_rvalid;
output M00_AXI_rready;
output [7:0]M01_AXI_awaddr;
output [2:0]M01_AXI_awprot;
output M01_AXI_awvalid;
input M01_AXI_awready;
output [31:0]M01_AXI_wdata;
output [3:0]M01_AXI_wstrb;
output M01_AXI_wvalid;
input M01_AXI_wready;
input [1:0]M01_AXI_bresp;
input M01_AXI_bvalid;
output M01_AXI_bready;
output [7:0]M01_AXI_araddr;
output [2:0]M01_AXI_arprot;
output M01_AXI_arvalid;
input M01_AXI_arready;
input [31:0]M01_AXI_rdata;
input [1:0]M01_AXI_rresp;
input M01_AXI_rvalid;
output M01_AXI_rready;
endmodule

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can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_uart_parse_real_0_0_stub.v Normal file
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "uart_parse_real,Vivado 2023.2" *)
module design_1_uart_parse_real_0_0(clk, rstn, rx_i, async_serial);
input clk /* synthesis syn_isclock = 1 */;
input rstn;
input rx_i;
output [47:0]async_serial;
endmodule

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can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_util_vector_logic_0_0_stub.v Normal file
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "util_vector_logic_v2_0_3_util_vector_logic,Vivado 2023.2" *)
module design_1_util_vector_logic_0_0(Op1, Res);
input [0:0]Op1;
output [0:0]Res;
endmodule

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can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_util_vector_logic_0_1_stub.v Normal file
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "util_vector_logic_v2_0_3_util_vector_logic,Vivado 2023.2" *)
module design_1_util_vector_logic_0_1(Op1, Op2, Res);
input [0:0]Op1;
input [0:0]Op2;
output [0:0]Res;
endmodule

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can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_wrapper.tcl Normal file
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#
# Synthesis run script generated by Vivado
#
namespace eval rt {
variable rc
}
set rt::rc [catch {
uplevel #0 {
set ::env(BUILTIN_SYNTH) true
source $::env(HRT_TCL_PATH)/rtSynthPrep.tcl
rt::HARTNDb_resetJobStats
rt::HARTNDb_resetSystemStats
rt::HARTNDb_startSystemStats
rt::HARTNDb_startJobStats
set rt::cmdEcho 0
rt::set_parameter writeXmsg true
rt::set_parameter enableParallelHelperSpawn true
set ::env(RT_TMP) "C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/tmp"
if { [ info exists ::env(RT_TMP) ] } {
file delete -force $::env(RT_TMP)
file mkdir $::env(RT_TMP)
}
rt::delete_design
rt::set_parameter datapathDensePacking false
set rt::partid xc7vx690tffg1761-2
source $::env(HRT_TCL_PATH)/rtSynthParallelPrep.tcl
file delete -force synth_hints.os
set rt::multiChipSynthesisFlow false
source $::env(SYNTH_COMMON)/common.tcl
set rt::defaultWorkLibName xil_defaultlib
rt::set_parameter defaultVhdlWorkLib xil_defaultlib
rt::set_parameter loadVhdl2008Libs false
rt::set_parameter loadVhdl2019Libs false
rt::set_parameter deferParseUntilElab true
rt::set_parameter sortHdlCommandLine true
set rt::useElabCache false
if {$rt::useElabCache == false} {
rt::read_verilog -sv -include {
c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_uart_parse_real_0_0/src/ila_0/hdl/verilog
c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ipshared/c2c6
c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog
c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ipshared/35de/hdl/verilog
} {
C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv
C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv
C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv
}
rt::read_verilog -include {
c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_uart_parse_real_0_0/src/ila_0/hdl/verilog
c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ipshared/c2c6
c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog
c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ipshared/35de/hdl/verilog
} {
C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_can_init_0_0_stub.v
C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_can_rx_parse_axi_0_0_stub.v
C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_uart_parse_real_0_0_stub.v
C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_ibufg_user_0_0_stub.v
C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_clk_wiz_0_0_stub.v
C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_util_vector_logic_0_0_stub.v
C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_util_vector_logic_0_1_stub.v
C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_can_0_2_stub.v
C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_can_0_3_stub.v
C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_smartconnect_0_0_stub.v
c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/synth/design_1.v
c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
}
rt::read_vhdl -lib xpm C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_VCOMP.vhd
rt::filesetChecksum
}
rt::set_parameter usePostFindUniquification false
set rt::top design_1_wrapper
rt::set_parameter enableIncremental true
rt::set_parameter markDebugPreservationLevel "enable"
set rt::reportTiming false
rt::set_parameter elaborateOnly true
rt::set_parameter elaborateRtl true
rt::set_parameter eliminateRedundantBitOperator false
rt::set_parameter dataflowBusHighlighting false
rt::set_parameter generateDataflowBusNetlist false
rt::set_parameter dataFlowViewInElab false
rt::set_parameter busViewFixBrokenConnections false
rt::set_parameter elaborateRtlOnlyFlow true
rt::set_parameter writeBlackboxInterface true
rt::set_parameter merge_flipflops true
rt::set_parameter srlDepthThreshold 3
rt::set_parameter rstSrlDepthThreshold 4
# MODE:
rt::set_parameter webTalkPath {}
rt::set_parameter synthDebugLog false
rt::set_parameter printModuleName false
rt::set_parameter enableSplitFlowPath "C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/"
set ok_to_delete_rt_tmp true
if { [rt::get_parameter parallelDebug] } {
set ok_to_delete_rt_tmp false
}
if {$rt::useElabCache == false} {
set oldMIITMVal [rt::get_parameter maxInputIncreaseToMerge]; rt::set_parameter maxInputIncreaseToMerge 1000
set oldCDPCRL [rt::get_parameter createDfgPartConstrRecurLimit]; rt::set_parameter createDfgPartConstrRecurLimit 1
$rt::db readXRFFile
rt::run_rtlelab -module $rt::top
rt::set_parameter maxInputIncreaseToMerge $oldMIITMVal
rt::set_parameter createDfgPartConstrRecurLimit $oldCDPCRL
}
set rt::flowresult [ source $::env(SYNTH_COMMON)/flow.tcl ]
rt::HARTNDb_stopJobStats
if { $rt::flowresult == 1 } { return -code error }
set hsKey [rt::get_parameter helper_shm_key]
if { $hsKey != "" && [info exists ::env(BUILTIN_SYNTH)] && [rt::get_parameter enableParallelHelperSpawn] } {
$rt::db killSynthHelper $hsKey
}
rt::set_parameter helper_shm_key ""
if { [ info exists ::env(RT_TMP) ] } {
if { [info exists ok_to_delete_rt_tmp] && $ok_to_delete_rt_tmp } {
file delete -force $::env(RT_TMP)
}
}
source $::env(HRT_TCL_PATH)/rtSynthCleanup.tcl
} ; #end uplevel
} rt::result]
if { $rt::rc } {
$rt::db resetHdlParse
set hsKey [rt::get_parameter helper_shm_key]
if { $hsKey != "" && [info exists ::env(BUILTIN_SYNTH)] && [rt::get_parameter enableParallelHelperSpawn] } {
$rt::db killSynthHelper $hsKey
}
source $::env(HRT_TCL_PATH)/rtSynthCleanup.tcl
return -code "error" $rt::result
}

1
can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/dupFiles.rpt Normal file
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@@ -0,0 +1 @@
CRC performance measure: elapsed=00:00:00.001s;;memory_peak=2503.066MB;;memory_gain=0.000MB