422,lvds,can解析已上板验证通过

This commit is contained in:
zhaoms
2026-05-30 12:09:51 +08:00
parent 929b5c8317
commit 5e635348ba
453 changed files with 27961 additions and 560841 deletions

View File

@@ -67,13 +67,13 @@
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="6"/>
<Option Name="WTModelSimExportSim" Val="6"/>
<Option Name="WTQuestaExportSim" Val="6"/>
<Option Name="WTXSimExportSim" Val="24"/>
<Option Name="WTModelSimExportSim" Val="24"/>
<Option Name="WTQuestaExportSim" Val="24"/>
<Option Name="WTIesExportSim" Val="0"/>
<Option Name="WTVcsExportSim" Val="6"/>
<Option Name="WTRivieraExportSim" Val="6"/>
<Option Name="WTActivehdlExportSim" Val="6"/>
<Option Name="WTVcsExportSim" Val="24"/>
<Option Name="WTRivieraExportSim" Val="24"/>
<Option Name="WTActivehdlExportSim" Val="24"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
@@ -97,33 +97,6 @@
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
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<Proxy FileSetName="design_1_can_0_2"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_can_0_3/design_1_can_0_3.xci">
<Proxy FileSetName="design_1_can_0_3"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_can_rx_parse_axi_0_0/design_1_can_rx_parse_axi_0_0.xci">
<Proxy FileSetName="design_1_can_rx_parse_axi_0_0"/>
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<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xci">
<Proxy FileSetName="design_1_clk_wiz_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_ibufg_user_0_0/design_1_ibufg_user_0_0.xci">
<Proxy FileSetName="design_1_ibufg_user_0_0"/>
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<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_uart_parse_real_0_0/design_1_uart_parse_real_0_0.xci">
<Proxy FileSetName="design_1_uart_parse_real_0_0"/>
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<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_util_vector_logic_0_0/design_1_util_vector_logic_0_0.xci">
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<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_util_vector_logic_0_1/design_1_util_vector_logic_0_1.xci">
<Proxy FileSetName="design_1_util_vector_logic_0_1"/>
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<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_xbar_0/design_1_xbar_0.xci">
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</File>
<File Path="$PGENDIR/sources_1/bd/design_1/hdl/design_1_wrapper.v">
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@@ -189,60 +162,6 @@
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</Config>
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<Config>
<Option Name="TopModule" Val="design_1_can_rx_parse_axi_0_0"/>
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<Config>
<Option Name="TopModule" Val="design_1_uart_parse_real_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
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<Config>
<Option Name="TopModule" Val="design_1_clk_wiz_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
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<Config>
<Option Name="TopModule" Val="design_1_util_vector_logic_0_0"/>
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<Config>
<Option Name="TopModule" Val="design_1_util_vector_logic_0_1"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
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<Config>
<Option Name="TopModule" Val="design_1_can_0_2"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
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<Config>
<Option Name="TopModule" Val="design_1_can_0_3"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
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<Config>
<Option Name="TopModule" Val="design_1_ibufg_user_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="design_1_xbar_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_xbar_0" RelGenDir="$PGENDIR/design_1_xbar_0">
<Config>
<Option Name="TopModule" Val="design_1_xbar_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
@@ -264,18 +183,6 @@
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<Desc>Vivado Synthesis Defaults</Desc>
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<Step Id="synth_design"/>
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<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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@@ -285,95 +192,9 @@
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@@ -389,163 +210,6 @@
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