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422,lvds，can解析已上板验证通过

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zhaoms
2026-05-30 12:09:51 +08:00
parent 929b5c8317
commit 5e635348ba
453 changed files with 27961 additions and 560841 deletions
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11
can_parse_ctrl/can_parse_ctrl.srcs/constrs_1/new/can_parse_ctrl.xdc
View File

@@ -13,3 +13,14 @@ set_property IOSTANDARD LVCMOS18 [get_ports can_phy_rx_1]
set_property IOSTANDARD LVCMOS18 [get_ports can_phy_tx_1]
set_property PACKAGE_PIN K38 [get_ports rx_i_0]
set_property IOSTANDARD LVCMOS18 [get_ports rx_i_0]
set_property PACKAGE_PIN L39 [get_ports lvds_rx_clk_p_0]
set_property IOSTANDARD LVDS [get_ports lvds_rx_clk_p_0]
set_property PACKAGE_PIN H40 [get_ports lvds_rx_data_p_0]
set_property PACKAGE_PIN F42 [get_ports lvds_rx_csn_p_0]
set_property IOSTANDARD LVDS [get_ports lvds_rx_csn_p_0]
set_property IOSTANDARD LVDS [get_ports lvds_rx_data_p_0]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk]

202
can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd
View File

@@ -1,12 +1,12 @@
{
"design": {
"design_info": {
"boundary_crc": "0x64F385109989CA5D",
"boundary_crc": "0xACD5991E8CD2B7B",
"device": "xc7vx690tffg1761-2",
"gen_directory": "../../../../can_parse_ctrl.gen/sources_1/bd/design_1",
"name": "design_1",
"rev_ctrl_bd_flag": "RevCtrlBdOff",
"synth_flow_mode": "Hierarchical",
"synth_flow_mode": "None",
"tool_version": "2023.2",
"validated": "true"
},
@@ -26,6 +26,26 @@
"s01_couplers": {},
"m00_couplers": {},
"m01_couplers": {}
},
"lvds_rx_0": "",
"xlconstant_0": "",
"xlconstant_1": ""
},
"interface_ports": {
"LVDS_RX_DATA": {
"mode": "Slave",
"vlnv_bus_definition": "xilinx.com:interface:diff_clock:1.0",
"vlnv": "xilinx.com:interface:diff_clock_rtl:1.0",
"parameters": {
"CAN_DEBUG": {
"value": "false",
"value_src": "default"
},
"FREQ_HZ": {
"value": "100000000",
"value_src": "default"
}
}
}
},
"ports": {
@@ -83,6 +103,70 @@
},
"can_phy_tx_1": {
"direction": "O"
},
"lvds_rx_csn_n_0": {
"direction": "I"
},
"lvds_rx_clk_p_0": {
"type": "clk",
"direction": "I",
"parameters": {
"CLK_DOMAIN": {
"value": "design_1_lvds_rx_clk_p_0",
"value_src": "default"
},
"FREQ_HZ": {
"value": "100000000",
"value_src": "default"
},
"FREQ_TOLERANCE_HZ": {
"value": "0",
"value_src": "default"
},
"INSERT_VIP": {
"value": "0",
"value_src": "default"
},
"PHASE": {
"value": "0.0",
"value_src": "default"
}
}
},
"lvds_rx_clk_n_0": {
"type": "clk",
"direction": "I",
"parameters": {
"CLK_DOMAIN": {
"value": "design_1_lvds_rx_clk_n_0",
"value_src": "default"
},
"FREQ_HZ": {
"value": "100000000",
"value_src": "default"
},
"FREQ_TOLERANCE_HZ": {
"value": "0",
"value_src": "default"
},
"INSERT_VIP": {
"value": "0",
"value_src": "default"
},
"PHASE": {
"value": "0.0",
"value_src": "default"
}
}
},
"lvds_rx_data_p_0": {
"direction": "I"
},
"lvds_rx_csn_p_0": {
"direction": "I"
},
"lvds_rx_data_n_0": {
"direction": "I"
}
},
"components": {
@@ -184,7 +268,7 @@
"value": "50.000"
},
"CLKOUT2_USED": {
"value": "true"
"value": "false"
},
"MMCM_CLKFBOUT_MULT_F": {
"value": "20.000"
@@ -199,10 +283,10 @@
"value": "50.000"
},
"MMCM_CLKOUT1_DIVIDE": {
"value": "20"
"value": "1"
},
"NUM_OUT_CLKS": {
"value": "2"
"value": "1"
},
"PRIM_IN_FREQ": {
"value": "50.000"
@@ -738,6 +822,27 @@
]
}
}
},
"lvds_rx_0": {
"vlnv": "xilinx.com:user:lvds_rx:1.0",
"ip_revision": "2",
"xci_name": "design_1_lvds_rx_0_0",
"xci_path": "ip\\design_1_lvds_rx_0_0\\design_1_lvds_rx_0_0.xci",
"inst_hier_path": "lvds_rx_0"
},
"xlconstant_0": {
"vlnv": "xilinx.com:ip:xlconstant:1.1",
"ip_revision": "8",
"xci_name": "design_1_xlconstant_0_0",
"xci_path": "ip\\design_1_xlconstant_0_0\\design_1_xlconstant_0_0.xci",
"inst_hier_path": "xlconstant_0"
},
"xlconstant_1": {
"vlnv": "xilinx.com:ip:xlconstant:1.1",
"ip_revision": "8",
"xci_name": "design_1_xlconstant_0_1",
"xci_path": "ip\\design_1_xlconstant_0_1\\design_1_xlconstant_0_1.xci",
"inst_hier_path": "xlconstant_1"
}
},
"interface_nets": {
@@ -780,13 +885,14 @@
"can_0/s_axi_aresetn",
"can_1/s_axi_aresetn",
"can_rx_parse_axi_0/aresetn",
"uart_parse_real_0/rstn",
"can_init_0/rst_n",
"axi_interconnect_0/S01_ARESETN",
"axi_interconnect_0/M01_ARESETN",
"axi_interconnect_0/M00_ARESETN",
"axi_interconnect_0/S00_ARESETN",
"axi_interconnect_0/ARESETN"
"axi_interconnect_0/ARESETN",
"uart_parse_real_0/rstn",
"lvds_rx_0/aresetn"
]
},
"Op1_0_1": {
@@ -826,21 +932,6 @@
"ibufg_user_0/sys_clk"
]
},
"clk_wiz_0_clk_out2": {
"ports": [
"clk_wiz_0/clk_out2",
"uart_parse_real_0/clk",
"can_rx_parse_axi_0/aclk",
"axi_interconnect_0/ACLK",
"axi_interconnect_0/S00_ACLK",
"axi_interconnect_0/M00_ACLK",
"axi_interconnect_0/M01_ACLK",
"axi_interconnect_0/S01_ACLK",
"can_init_0/clk",
"can_0/s_axi_aclk",
"can_1/s_axi_aclk"
]
},
"clk_wiz_0_locked": {
"ports": [
"clk_wiz_0/locked",
@@ -850,7 +941,60 @@
"ibufg_user_0_clk_out": {
"ports": [
"ibufg_user_0/clk_out",
"clk_wiz_0/clk_in1"
"clk_wiz_0/clk_in1",
"uart_parse_real_0/clk",
"can_rx_parse_axi_0/aclk",
"can_init_0/clk",
"axi_interconnect_0/ACLK",
"axi_interconnect_0/S00_ACLK",
"axi_interconnect_0/M00_ACLK",
"axi_interconnect_0/M01_ACLK",
"axi_interconnect_0/S01_ACLK",
"can_0/s_axi_aclk",
"can_1/s_axi_aclk",
"lvds_rx_0/clk"
]
},
"lvds_rx_0_lvds_rx_status": {
"ports": [
"lvds_rx_0/lvds_rx_status",
"can_rx_parse_axi_0/tlm_lvds"
]
},
"lvds_rx_clk_n_0_1": {
"ports": [
"lvds_rx_clk_n_0",
"lvds_rx_0/lvds_rx_clk_n"
]
},
"lvds_rx_clk_p_0_1": {
"ports": [
"lvds_rx_clk_p_0",
"lvds_rx_0/lvds_rx_clk_p"
]
},
"lvds_rx_csn_n_0_1": {
"ports": [
"lvds_rx_csn_n_0",
"lvds_rx_0/lvds_rx_csn_n"
]
},
"lvds_rx_csn_p_0_1": {
"ports": [
"lvds_rx_csn_p_0",
"lvds_rx_0/lvds_rx_csn_p"
]
},
"lvds_rx_data_n_0_1": {
"ports": [
"lvds_rx_data_n_0",
"lvds_rx_0/lvds_rx_data_n"
]
},
"lvds_rx_data_p_0_1": {
"ports": [
"lvds_rx_data_p_0",
"lvds_rx_0/lvds_rx_data_p"
]
},
"rx_i_0_1": {
@@ -870,6 +1014,18 @@
"util_vector_logic_0/Res",
"clk_wiz_0/reset"
]
},
"xlconstant_0_dout": {
"ports": [
"xlconstant_0/dout",
"lvds_rx_0/enable"
]
},
"xlconstant_1_dout": {
"ports": [
"xlconstant_1/dout",
"lvds_rx_0/m_axis_tready"
]
}
},
"addressing": {

2
can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/ip/design_1_can_0_2/design_1_can_0_2.xci
View File

@@ -59,7 +59,7 @@
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2023.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
}
},
"boundary": {

2
can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/ip/design_1_can_0_3/design_1_can_0_3.xci
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@@ -59,7 +59,7 @@
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2023.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
}
},
"boundary": {

2
can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/ip/design_1_can_init_0_0/design_1_can_init_0_0.xci
View File

@@ -41,7 +41,7 @@
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2023.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
}
},
"boundary": {

2
can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/ip/design_1_can_rx_parse_axi_0_0/design_1_can_rx_parse_axi_0_0.xci
View File

@@ -45,7 +45,7 @@
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2023.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
}
},
"boundary": {

37
can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xci
View File

@@ -52,13 +52,13 @@
"CLKIN1_JITTER_PS": [ { "value": "200.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLKOUT2_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLKOUT2_USED": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLKOUT3_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLKOUT4_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"NUM_OUT_CLKS": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"NUM_OUT_CLKS": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
@@ -172,7 +172,7 @@
"MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"MMCM_CLKOUT1_DIVIDE": [ { "value": "20", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"MMCM_CLKOUT1_DIVIDE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
@@ -266,7 +266,7 @@
"PHASE_DUTY_CONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
},
"model_parameters": {
"C_CLKOUT2_USED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_CLKOUT2_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
"C_USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
@@ -326,7 +326,7 @@
"C_USE_POWER_DOWN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USE_STATUS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USE_FREEZE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_NUM_OUT_CLKS": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_NUM_OUT_CLKS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
"C_CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
"C_CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
@@ -340,7 +340,7 @@
"C_OUTCLK_SUM_ROW0A": [ { "value": " Output Output Phase Duty Cycle Pk-to-Pk Phase", "resolve_type": "generated", "usage": "all" } ],
"C_OUTCLK_SUM_ROW0B": [ { "value": " Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)", "resolve_type": "generated", "usage": "all" } ],
"C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__20.00000______0.000______50.0______249.363____164.985", "resolve_type": "generated", "usage": "all" } ],
"C_OUTCLK_SUM_ROW2": [ { "value": "clk_out2__50.00000______0.000______50.0______192.113____164.985", "resolve_type": "generated", "usage": "all" } ],
"C_OUTCLK_SUM_ROW2": [ { "value": "no_CLK_OUT2_output", "resolve_type": "generated", "usage": "all" } ],
"C_OUTCLK_SUM_ROW3": [ { "value": "no_CLK_OUT3_output", "resolve_type": "generated", "usage": "all" } ],
"C_OUTCLK_SUM_ROW4": [ { "value": "no_CLK_OUT4_output", "resolve_type": "generated", "usage": "all" } ],
"C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ],
@@ -410,7 +410,7 @@
"C_MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_MMCM_STARTUP_WAIT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
"C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_MMCM_CLKOUT1_DIVIDE": [ { "value": "20", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_MMCM_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
@@ -541,7 +541,7 @@
"C_FILTER_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
"C_FILTER_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
"C_DIVIDE1_AUTO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
"C_DIVIDE2_AUTO": [ { "value": "0.4", "resolve_type": "generated", "usage": "all" } ],
"C_DIVIDE2_AUTO": [ { "value": "0.02", "resolve_type": "generated", "usage": "all" } ],
"C_DIVIDE3_AUTO": [ { "value": "0.02", "resolve_type": "generated", "usage": "all" } ],
"C_DIVIDE4_AUTO": [ { "value": "0.02", "resolve_type": "generated", "usage": "all" } ],
"C_DIVIDE5_AUTO": [ { "value": "0.02", "resolve_type": "generated", "usage": "all" } ],
@@ -604,7 +604,7 @@
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2023.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
}
},
"boundary": {
@@ -612,7 +612,6 @@
"reset": [ { "direction": "in", "driver_value": "0" } ],
"clk_in1": [ { "direction": "in" } ],
"clk_out1": [ { "direction": "out" } ],
"clk_out2": [ { "direction": "out" } ],
"locked": [ { "direction": "out" } ]
},
"interfaces": {
@@ -665,24 +664,6 @@
"port_maps": {
"CLK_OUT1": [ { "physical_name": "clk_out1" } ]
}
},
"clock_CLK_OUT2": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "master",
"parameters": {
"FREQ_HZ": [ { "value": "50000000", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "/clk_wiz_0_clk_out1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK_OUT2": [ { "physical_name": "clk_out2" } ]
}
}
}
}

2
can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/ip/design_1_ibufg_user_0_0/design_1_ibufg_user_0_0.xci
View File

@@ -31,7 +31,7 @@
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2023.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
}
},
"boundary": {

4
can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/ip/design_1_uart_parse_real_0_0/design_1_uart_parse_real_0_0.xci
View File

@@ -45,7 +45,7 @@
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2023.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
}
},
"boundary": {
@@ -74,7 +74,7 @@
"mode": "slave",
"parameters": {
"ASSOCIATED_RESET": [ { "value": "rstn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"FREQ_HZ": [ { "value": "", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"FREQ_HZ": [ { "value": "50000000", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "/clk_wiz_0_clk_out1", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],

2
can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_0/design_1_util_vector_logic_0_0.xci
View File

@@ -38,7 +38,7 @@
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2023.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
}
},
"boundary": {

2
can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_1/design_1_util_vector_logic_0_1.xci
View File

@@ -38,7 +38,7 @@
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2023.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
}
},
"boundary": {

2
can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/ip/design_1_xbar_0/design_1_xbar_0.xci
View File

@@ -1261,7 +1261,7 @@
"SELECTEDSIMMODEL": [ { "value": "rtl" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2023.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
}
},
"boundary": {

96
can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui
View File

@@ -1,47 +1,65 @@
{
"ActiveEmotionalView":"Default View",
"Default View_ScaleFactor":"0.574794",
"Default View_TopLeft":"-146,0",
"Default View_ScaleFactor":"1.10589",
"Default View_TopLeft":"-183,552",
"ExpandedHierarchyInLayout":"",
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 threadsafe
# -string -flagsOSRD
preplace port port-id_clk_in1_0 -pg 1 -lvl 0 -x 0 -y 400 -defaultsOSRD
preplace port port-id_rx_i_0 -pg 1 -lvl 0 -x 0 -y 710 -defaultsOSRD
preplace port port-id_can_phy_rx_0 -pg 1 -lvl 0 -x 0 -y 520 -defaultsOSRD
preplace port port-id_can_phy_tx_0 -pg 1 -lvl 8 -x 1850 -y 430 -defaultsOSRD
preplace port port-id_can_phy_rx_1 -pg 1 -lvl 0 -x 0 -y 830 -defaultsOSRD
preplace port port-id_can_phy_tx_1 -pg 1 -lvl 8 -x 1850 -y 230 -defaultsOSRD
preplace portBus aresetn_0 -pg 1 -lvl 0 -x 0 -y 420 -defaultsOSRD
preplace inst can_init_0 -pg 1 -lvl 5 -x 980 -y 90 -defaultsOSRD
preplace inst can_rx_parse_axi_0 -pg 1 -lvl 5 -x 980 -y 670 -defaultsOSRD
preplace inst uart_parse_real_0 -pg 1 -lvl 4 -x 710 -y 690 -defaultsOSRD
preplace inst clk_wiz_0 -pg 1 -lvl 2 -x 290 -y 390 -defaultsOSRD
preplace inst util_vector_logic_0 -pg 1 -lvl 1 -x 110 -y 290 -defaultsOSRD -resize 83 88
preplace inst util_vector_logic_1 -pg 1 -lvl 3 -x 490 -y 440 -defaultsOSRD -resize 134 93
preplace inst can_0 -pg 1 -lvl 7 -x 1650 -y 410 -defaultsOSRD
preplace inst can_1 -pg 1 -lvl 7 -x 1650 -y 210 -defaultsOSRD
preplace inst ibufg_user_0 -pg 1 -lvl 1 -x 110 -y 400 -defaultsOSRD
preplace inst axi_interconnect_0 -pg 1 -lvl 6 -x 1300 -y 180 -defaultsOSRD
preplace netloc Net 1 2 6 380J 350 NJ 350 NJ 350 NJ 350 1480J 310 1820
preplace netloc Net1 1 3 4 580 440 830 170 1150 360 1470
preplace netloc Op1_0_1 1 0 3 20 220 NJ 220 390J
preplace netloc can_0_can_phy_tx 1 7 1 NJ 430
preplace netloc can_1_can_phy_tx 1 7 1 NJ 230
preplace netloc can_phy_rx_0_1 1 0 8 NJ 520 NJ 520 NJ 520 590J 510 NJ 510 NJ 510 NJ 510 1820
preplace netloc can_phy_rx_1_1 1 0 8 NJ 830 NJ 830 NJ 830 NJ 830 NJ 830 NJ 830 NJ 830 1830
preplace netloc clk_in1_0_1 1 0 1 NJ 400
preplace netloc clk_wiz_0_locked 1 2 1 380 390n
preplace netloc rx_i_0_1 1 0 4 NJ 710 NJ 710 NJ 710 NJ
preplace netloc uart_parse_real_0_async_serial 1 4 1 N 690
preplace netloc util_vector_logic_0_Res 1 1 1 200J 290n
preplace netloc ibufg_user_0_clk_out 1 1 1 NJ 400
preplace netloc clk_wiz_0_clk_out2 1 2 5 400J 370 600 370 820 180 1140 10 1460
preplace netloc axi_interconnect_0_M01_AXI 1 6 1 N 190
preplace netloc axi_interconnect_0_M00_AXI 1 6 1 1450 170n
preplace netloc S00_AXI_1 1 5 1 N 70
preplace netloc S01_AXI_1 1 5 1 1130 90n
levelinfo -pg 1 0 110 290 490 710 980 1300 1650 1850
pagesize -pg 1 -db -bbox -sgen -140 0 1990 850
preplace port LVDS_RX_DATA -pg 1 -lvl 0 -x -20 -y 20 -defaultsOSRD
preplace port port-id_clk_in1_0 -pg 1 -lvl 0 -x -20 -y 302 -defaultsOSRD
preplace port port-id_rx_i_0 -pg 1 -lvl 0 -x -20 -y 532 -defaultsOSRD
preplace port port-id_can_phy_rx_0 -pg 1 -lvl 0 -x -20 -y 672 -defaultsOSRD
preplace port port-id_can_phy_tx_0 -pg 1 -lvl 8 -x 2100 -y 612 -defaultsOSRD
preplace port port-id_can_phy_rx_1 -pg 1 -lvl 0 -x -20 -y 1022 -defaultsOSRD
preplace port port-id_can_phy_tx_1 -pg 1 -lvl 8 -x 2100 -y 892 -defaultsOSRD
preplace port port-id_lvds_rx_csn_n_0 -pg 1 -lvl 0 -x -20 -y 830 -defaultsOSRD
preplace port port-id_lvds_rx_clk_p_0 -pg 1 -lvl 0 -x -20 -y 770 -defaultsOSRD
preplace port port-id_lvds_rx_clk_n_0 -pg 1 -lvl 0 -x -20 -y 790 -defaultsOSRD
preplace port port-id_lvds_rx_data_p_0 -pg 1 -lvl 0 -x -20 -y 850 -defaultsOSRD
preplace port port-id_lvds_rx_csn_p_0 -pg 1 -lvl 0 -x -20 -y 810 -defaultsOSRD
preplace port port-id_lvds_rx_data_n_0 -pg 1 -lvl 0 -x -20 -y 870 -defaultsOSRD
preplace portBus aresetn_0 -pg 1 -lvl 0 -x -20 -y 330 -defaultsOSRD
preplace inst can_init_0 -pg 1 -lvl 5 -x 1220 -y 752 -defaultsOSRD
preplace inst can_rx_parse_axi_0 -pg 1 -lvl 5 -x 1220 -y 500 -defaultsOSRD
preplace inst uart_parse_real_0 -pg 1 -lvl 4 -x 890 -y 512 -defaultsOSRD
preplace inst clk_wiz_0 -pg 1 -lvl 2 -x 290 -y 202 -defaultsOSRD
preplace inst util_vector_logic_0 -pg 1 -lvl 1 -x 110 -y 192 -defaultsOSRD -resize 83 88
preplace inst util_vector_logic_1 -pg 1 -lvl 3 -x 550 -y 180 -defaultsOSRD -resize 134 93
preplace inst can_0 -pg 1 -lvl 7 -x 1900 -y 592 -defaultsOSRD
preplace inst can_1 -pg 1 -lvl 7 -x 1900 -y 872 -defaultsOSRD
preplace inst ibufg_user_0 -pg 1 -lvl 1 -x 110 -y 302 -defaultsOSRD
preplace inst axi_interconnect_0 -pg 1 -lvl 6 -x 1560 -y 582 -defaultsOSRD
preplace inst lvds_rx_0 -pg 1 -lvl 4 -x 890 -y 792 -defaultsOSRD
preplace inst xlconstant_0 -pg 1 -lvl 3 -x 550 -y 890 -defaultsOSRD
preplace inst xlconstant_1 -pg 1 -lvl 4 -x 890 -y 990 -defaultsOSRD
preplace netloc Net 1 2 6 390J 250 NJ 250 NJ 250 NJ 250 NJ 250 2080
preplace netloc Net1 1 3 4 730 340 1050 340 1380 760 1730
preplace netloc Op1_0_1 1 0 3 10 122 NJ 122 400J
preplace netloc can_0_can_phy_tx 1 7 1 NJ 612
preplace netloc can_1_can_phy_tx 1 7 1 NJ 892
preplace netloc can_phy_rx_0_1 1 0 8 NJ 672 NJ 672 NJ 672 650J 652 1040J 672 1370J 750 NJ 750 2070
preplace netloc can_phy_rx_1_1 1 0 8 NJ 1022 NJ 1022 380J 1050 NJ 1050 NJ 1050 NJ 1050 NJ 1050 2070
preplace netloc clk_in1_0_1 1 0 1 NJ 302
preplace netloc clk_wiz_0_locked 1 2 1 380 172n
preplace netloc rx_i_0_1 1 0 4 NJ 532 NJ 532 NJ 532 NJ
preplace netloc uart_parse_real_0_async_serial 1 4 1 1060 512n
preplace netloc util_vector_logic_0_Res 1 1 1 NJ 192
preplace netloc ibufg_user_0_clk_out 1 1 6 200 302 NJ 302 720 330 1070 330 1390 770 1720
preplace netloc lvds_rx_0_lvds_rx_status 1 4 1 1060 540n
preplace netloc xlconstant_0_dout 1 3 1 670J 752n
preplace netloc xlconstant_1_dout 1 4 1 1040 792n
preplace netloc lvds_rx_csn_n_0_1 1 0 4 0J 820 NJ 820 NJ 820 650J
preplace netloc lvds_rx_clk_p_0_1 1 0 4 NJ 770 NJ 770 NJ 770 680J
preplace netloc lvds_rx_clk_n_0_1 1 0 4 NJ 790 NJ 790 NJ 790 650J
preplace netloc lvds_rx_data_p_0_1 1 0 4 NJ 850 NJ 850 400J 950 680J
preplace netloc lvds_rx_csn_p_0_1 1 0 4 NJ 810 NJ 810 NJ 810 660J
preplace netloc lvds_rx_data_n_0_1 1 0 4 10J 830 NJ 830 NJ 830 640J
preplace netloc axi_interconnect_0_M01_AXI 1 6 1 1710 592n
preplace netloc axi_interconnect_0_M00_AXI 1 6 1 N 572
preplace netloc S00_AXI_1 1 5 1 1400 472n
preplace netloc S01_AXI_1 1 5 1 1410 492n
levelinfo -pg 1 -20 110 290 550 890 1220 1560 1900 2100
pagesize -pg 1 -db -bbox -sgen -190 0 2240 1080
"
}
0

BIN
can_parse_ctrl/can_parse_ctrl.srcs/utils_1/imports/synth_1/design_1_wrapper.dcp
View File

Binary file not shown.