422,lvds，can解析已上板验证通过
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zhaoms
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
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// Please paste the declaration into a Verilog source file or add the file as an additional source.
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(* x_core_info = "can_v5_1_1,Vivado 2023.2" *)
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module design_1_can_0_2(can_clk, can_phy_rx, can_phy_tx,
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ip2bus_intrevent, s_axi_aclk, s_axi_aresetn, s_axi_awaddr, s_axi_awvalid, s_axi_awready,
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s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready, s_axi_bresp, s_axi_bvalid,
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s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready, s_axi_rdata, s_axi_rresp,
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s_axi_rvalid, s_axi_rready);
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input can_clk /* synthesis syn_isclock = 1 */;
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input can_phy_rx;
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output can_phy_tx;
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output ip2bus_intrevent;
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input s_axi_aclk /* synthesis syn_isclock = 1 */;
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input s_axi_aresetn;
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input [7:0]s_axi_awaddr;
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input s_axi_awvalid;
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output s_axi_awready;
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input [31:0]s_axi_wdata;
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input [3:0]s_axi_wstrb;
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input s_axi_wvalid;
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output s_axi_wready;
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output [1:0]s_axi_bresp;
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output s_axi_bvalid;
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input s_axi_bready;
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input [7:0]s_axi_araddr;
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input s_axi_arvalid;
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output s_axi_arready;
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output [31:0]s_axi_rdata;
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output [1:0]s_axi_rresp;
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output s_axi_rvalid;
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input s_axi_rready;
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endmodule
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@@ -1,35 +0,0 @@
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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||||
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||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
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// Please paste the declaration into a Verilog source file or add the file as an additional source.
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(* x_core_info = "can_v5_1_1,Vivado 2023.2" *)
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module design_1_can_0_3(can_clk, can_phy_rx, can_phy_tx,
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ip2bus_intrevent, s_axi_aclk, s_axi_aresetn, s_axi_awaddr, s_axi_awvalid, s_axi_awready,
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s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready, s_axi_bresp, s_axi_bvalid,
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s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready, s_axi_rdata, s_axi_rresp,
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s_axi_rvalid, s_axi_rready);
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input can_clk /* synthesis syn_isclock = 1 */;
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input can_phy_rx;
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output can_phy_tx;
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output ip2bus_intrevent;
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input s_axi_aclk /* synthesis syn_isclock = 1 */;
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input s_axi_aresetn;
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input [7:0]s_axi_awaddr;
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input s_axi_awvalid;
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output s_axi_awready;
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input [31:0]s_axi_wdata;
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input [3:0]s_axi_wstrb;
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input s_axi_wvalid;
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output s_axi_wready;
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output [1:0]s_axi_bresp;
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output s_axi_bvalid;
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input s_axi_bready;
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input [7:0]s_axi_araddr;
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input s_axi_arvalid;
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output s_axi_arready;
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output [31:0]s_axi_rdata;
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output [1:0]s_axi_rresp;
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output s_axi_rvalid;
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input s_axi_rready;
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endmodule
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@@ -1,23 +0,0 @@
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
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// Please paste the declaration into a Verilog source file or add the file as an additional source.
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(* X_CORE_INFO = "can_init,Vivado 2023.2" *)
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module design_1_can_init_0_0(clk, rst_n, m_axi_awvalid, m_axi_awready,
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m_axi_awaddr, m_axi_wvalid, m_axi_wready, m_axi_wdata, m_axi_wstrb, m_axi_bvalid,
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m_axi_bready, init_done, state);
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input clk /* synthesis syn_isclock = 1 */;
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input rst_n;
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output m_axi_awvalid;
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input m_axi_awready;
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output [31:0]m_axi_awaddr;
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output m_axi_wvalid;
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input m_axi_wready;
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output [31:0]m_axi_wdata;
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output [3:0]m_axi_wstrb;
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input m_axi_bvalid;
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output m_axi_bready;
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output init_done;
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output [5:0]state;
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endmodule
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@@ -1,41 +0,0 @@
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
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// Please paste the declaration into a Verilog source file or add the file as an additional source.
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(* X_CORE_INFO = "can_rx_parse_axi,Vivado 2023.2" *)
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module design_1_can_rx_parse_axi_0_0(aclk, aresetn, m_axi_araddr, m_axi_arvalid,
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m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready, m_axi_awaddr,
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m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, m_axi_wready,
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m_axi_bresp, m_axi_bvalid, m_axi_bready, tlm_record_task_id, tlm_downlink_task_id,
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tlm_disk_status, tlm_cam_dt_status, tlm_async_serial, tlm_lvds, tlm_reconfig,
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tlm_fpga_temp, tlm_compress_flash);
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input aclk /* synthesis syn_isclock = 1 */;
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input aresetn;
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output [31:0]m_axi_araddr;
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output m_axi_arvalid;
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input m_axi_arready;
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input [31:0]m_axi_rdata;
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input [1:0]m_axi_rresp;
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input m_axi_rvalid;
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output m_axi_rready;
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output [31:0]m_axi_awaddr;
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output m_axi_awvalid;
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input m_axi_awready;
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output [31:0]m_axi_wdata;
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output [3:0]m_axi_wstrb;
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output m_axi_wvalid;
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input m_axi_wready;
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input [1:0]m_axi_bresp;
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input m_axi_bvalid;
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output m_axi_bready;
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input [31:0]tlm_record_task_id;
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input [31:0]tlm_downlink_task_id;
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input [15:0]tlm_disk_status;
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input [439:0]tlm_cam_dt_status;
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input [47:0]tlm_async_serial;
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input [47:0]tlm_lvds;
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input [55:0]tlm_reconfig;
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input [15:0]tlm_fpga_temp;
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input [7:0]tlm_compress_flash;
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endmodule
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@@ -1,11 +0,0 @@
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
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// Please paste the declaration into a Verilog source file or add the file as an additional source.
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module design_1_clk_wiz_0_0(clk_out1, reset, locked, clk_in1);
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output clk_out1 /* synthesis syn_isclock = 1 */;
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input reset;
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output locked;
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input clk_in1;
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endmodule
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@@ -1,10 +0,0 @@
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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||||
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||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
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// Please paste the declaration into a Verilog source file or add the file as an additional source.
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(* X_CORE_INFO = "ibufg_user,Vivado 2023.2" *)
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module design_1_ibufg_user_0_0(sys_clk, clk_out);
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input sys_clk;
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output clk_out /* synthesis syn_isclock = 1 */;
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endmodule
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@@ -1,92 +0,0 @@
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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||||
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||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
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// Please paste the declaration into a Verilog source file or add the file as an additional source.
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(* X_CORE_INFO = "bd_48ac,Vivado 2023.2" *)
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module design_1_smartconnect_0_0(aclk, aresetn, S00_AXI_awaddr, S00_AXI_awprot,
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S00_AXI_awvalid, S00_AXI_awready, S00_AXI_wdata, S00_AXI_wstrb, S00_AXI_wvalid,
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S00_AXI_wready, S00_AXI_bresp, S00_AXI_bvalid, S00_AXI_bready, S01_AXI_awaddr,
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S01_AXI_awprot, S01_AXI_awvalid, S01_AXI_awready, S01_AXI_wdata, S01_AXI_wstrb,
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S01_AXI_wvalid, S01_AXI_wready, S01_AXI_bresp, S01_AXI_bvalid, S01_AXI_bready,
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S01_AXI_araddr, S01_AXI_arprot, S01_AXI_arvalid, S01_AXI_arready, S01_AXI_rdata,
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S01_AXI_rresp, S01_AXI_rvalid, S01_AXI_rready, M00_AXI_awaddr, M00_AXI_awprot,
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M00_AXI_awvalid, M00_AXI_awready, M00_AXI_wdata, M00_AXI_wstrb, M00_AXI_wvalid,
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M00_AXI_wready, M00_AXI_bresp, M00_AXI_bvalid, M00_AXI_bready, M00_AXI_araddr,
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M00_AXI_arprot, M00_AXI_arvalid, M00_AXI_arready, M00_AXI_rdata, M00_AXI_rresp,
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M00_AXI_rvalid, M00_AXI_rready, M01_AXI_awaddr, M01_AXI_awprot, M01_AXI_awvalid,
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M01_AXI_awready, M01_AXI_wdata, M01_AXI_wstrb, M01_AXI_wvalid, M01_AXI_wready,
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M01_AXI_bresp, M01_AXI_bvalid, M01_AXI_bready, M01_AXI_araddr, M01_AXI_arprot,
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M01_AXI_arvalid, M01_AXI_arready, M01_AXI_rdata, M01_AXI_rresp, M01_AXI_rvalid,
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M01_AXI_rready);
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input aclk /* synthesis syn_isclock = 1 */;
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input aresetn;
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input [31:0]S00_AXI_awaddr;
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input [2:0]S00_AXI_awprot;
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input S00_AXI_awvalid;
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output S00_AXI_awready;
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input [31:0]S00_AXI_wdata;
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input [3:0]S00_AXI_wstrb;
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input S00_AXI_wvalid;
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output S00_AXI_wready;
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output [1:0]S00_AXI_bresp;
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output S00_AXI_bvalid;
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input S00_AXI_bready;
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input [31:0]S01_AXI_awaddr;
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input [2:0]S01_AXI_awprot;
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input S01_AXI_awvalid;
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output S01_AXI_awready;
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input [31:0]S01_AXI_wdata;
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input [3:0]S01_AXI_wstrb;
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input S01_AXI_wvalid;
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output S01_AXI_wready;
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output [1:0]S01_AXI_bresp;
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output S01_AXI_bvalid;
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input S01_AXI_bready;
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input [31:0]S01_AXI_araddr;
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input [2:0]S01_AXI_arprot;
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input S01_AXI_arvalid;
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output S01_AXI_arready;
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output [31:0]S01_AXI_rdata;
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output [1:0]S01_AXI_rresp;
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output S01_AXI_rvalid;
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input S01_AXI_rready;
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output [7:0]M00_AXI_awaddr;
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output [2:0]M00_AXI_awprot;
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output M00_AXI_awvalid;
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input M00_AXI_awready;
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output [31:0]M00_AXI_wdata;
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output [3:0]M00_AXI_wstrb;
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output M00_AXI_wvalid;
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input M00_AXI_wready;
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input [1:0]M00_AXI_bresp;
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input M00_AXI_bvalid;
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output M00_AXI_bready;
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output [7:0]M00_AXI_araddr;
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output [2:0]M00_AXI_arprot;
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output M00_AXI_arvalid;
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input M00_AXI_arready;
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input [31:0]M00_AXI_rdata;
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input [1:0]M00_AXI_rresp;
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input M00_AXI_rvalid;
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output M00_AXI_rready;
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output [7:0]M01_AXI_awaddr;
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output [2:0]M01_AXI_awprot;
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output M01_AXI_awvalid;
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input M01_AXI_awready;
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output [31:0]M01_AXI_wdata;
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output [3:0]M01_AXI_wstrb;
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output M01_AXI_wvalid;
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input M01_AXI_wready;
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input [1:0]M01_AXI_bresp;
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input M01_AXI_bvalid;
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output M01_AXI_bready;
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output [7:0]M01_AXI_araddr;
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output [2:0]M01_AXI_arprot;
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output M01_AXI_arvalid;
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input M01_AXI_arready;
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input [31:0]M01_AXI_rdata;
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input [1:0]M01_AXI_rresp;
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input M01_AXI_rvalid;
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output M01_AXI_rready;
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endmodule
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@@ -1,12 +0,0 @@
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
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||||
(* X_CORE_INFO = "uart_parse_real,Vivado 2023.2" *)
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module design_1_uart_parse_real_0_0(clk, rstn, rx_i, async_serial);
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input clk /* synthesis syn_isclock = 1 */;
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input rstn;
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input rx_i;
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output [47:0]async_serial;
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||||
endmodule
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||||
@@ -1,10 +0,0 @@
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||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "util_vector_logic_v2_0_3_util_vector_logic,Vivado 2023.2" *)
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||||
module design_1_util_vector_logic_0_0(Op1, Res);
|
||||
input [0:0]Op1;
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||||
output [0:0]Res;
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||||
endmodule
|
||||
@@ -1,11 +0,0 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "util_vector_logic_v2_0_3_util_vector_logic,Vivado 2023.2" *)
|
||||
module design_1_util_vector_logic_0_1(Op1, Op2, Res);
|
||||
input [0:0]Op1;
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||||
input [0:0]Op2;
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||||
output [0:0]Res;
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||||
endmodule
|
||||
@@ -1,138 +0,0 @@
|
||||
#
|
||||
# Synthesis run script generated by Vivado
|
||||
#
|
||||
|
||||
namespace eval rt {
|
||||
variable rc
|
||||
}
|
||||
set rt::rc [catch {
|
||||
uplevel #0 {
|
||||
set ::env(BUILTIN_SYNTH) true
|
||||
source $::env(HRT_TCL_PATH)/rtSynthPrep.tcl
|
||||
rt::HARTNDb_resetJobStats
|
||||
rt::HARTNDb_resetSystemStats
|
||||
rt::HARTNDb_startSystemStats
|
||||
rt::HARTNDb_startJobStats
|
||||
set rt::cmdEcho 0
|
||||
rt::set_parameter writeXmsg true
|
||||
rt::set_parameter enableParallelHelperSpawn true
|
||||
set ::env(RT_TMP) "C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/tmp"
|
||||
if { [ info exists ::env(RT_TMP) ] } {
|
||||
file delete -force $::env(RT_TMP)
|
||||
file mkdir $::env(RT_TMP)
|
||||
}
|
||||
|
||||
rt::delete_design
|
||||
|
||||
rt::set_parameter datapathDensePacking false
|
||||
set rt::partid xc7vx690tffg1761-2
|
||||
source $::env(HRT_TCL_PATH)/rtSynthParallelPrep.tcl
|
||||
file delete -force synth_hints.os
|
||||
|
||||
set rt::multiChipSynthesisFlow false
|
||||
source $::env(SYNTH_COMMON)/common.tcl
|
||||
set rt::defaultWorkLibName xil_defaultlib
|
||||
rt::set_parameter defaultVhdlWorkLib xil_defaultlib
|
||||
|
||||
rt::set_parameter loadVhdl2008Libs false
|
||||
rt::set_parameter loadVhdl2019Libs false
|
||||
rt::set_parameter deferParseUntilElab true
|
||||
rt::set_parameter sortHdlCommandLine true
|
||||
set rt::useElabCache false
|
||||
if {$rt::useElabCache == false} {
|
||||
rt::read_verilog -sv -include {
|
||||
c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_uart_parse_real_0_0/src/ila_0/hdl/verilog
|
||||
c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ipshared/c2c6
|
||||
c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog
|
||||
c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ipshared/35de/hdl/verilog
|
||||
} {
|
||||
C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv
|
||||
C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv
|
||||
C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv
|
||||
}
|
||||
rt::read_verilog -include {
|
||||
c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_uart_parse_real_0_0/src/ila_0/hdl/verilog
|
||||
c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ipshared/c2c6
|
||||
c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ipshared/f0b6/hdl/verilog
|
||||
c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ipshared/35de/hdl/verilog
|
||||
} {
|
||||
C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_can_init_0_0_stub.v
|
||||
C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_can_rx_parse_axi_0_0_stub.v
|
||||
C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_uart_parse_real_0_0_stub.v
|
||||
C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_ibufg_user_0_0_stub.v
|
||||
C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_clk_wiz_0_0_stub.v
|
||||
C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_util_vector_logic_0_0_stub.v
|
||||
C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_util_vector_logic_0_1_stub.v
|
||||
C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_can_0_2_stub.v
|
||||
C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_can_0_3_stub.v
|
||||
C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_smartconnect_0_0_stub.v
|
||||
c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/synth/design_1.v
|
||||
c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
|
||||
}
|
||||
rt::read_vhdl -lib xpm C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_VCOMP.vhd
|
||||
rt::filesetChecksum
|
||||
}
|
||||
rt::set_parameter usePostFindUniquification false
|
||||
set rt::top design_1_wrapper
|
||||
rt::set_parameter enableIncremental true
|
||||
rt::set_parameter markDebugPreservationLevel "enable"
|
||||
set rt::reportTiming false
|
||||
rt::set_parameter elaborateOnly true
|
||||
rt::set_parameter elaborateRtl true
|
||||
rt::set_parameter eliminateRedundantBitOperator false
|
||||
rt::set_parameter dataflowBusHighlighting false
|
||||
rt::set_parameter generateDataflowBusNetlist false
|
||||
rt::set_parameter dataFlowViewInElab false
|
||||
rt::set_parameter busViewFixBrokenConnections false
|
||||
rt::set_parameter elaborateRtlOnlyFlow true
|
||||
rt::set_parameter writeBlackboxInterface true
|
||||
rt::set_parameter merge_flipflops true
|
||||
rt::set_parameter srlDepthThreshold 3
|
||||
rt::set_parameter rstSrlDepthThreshold 4
|
||||
# MODE:
|
||||
rt::set_parameter webTalkPath {}
|
||||
rt::set_parameter synthDebugLog false
|
||||
rt::set_parameter printModuleName false
|
||||
rt::set_parameter enableSplitFlowPath "C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/"
|
||||
set ok_to_delete_rt_tmp true
|
||||
if { [rt::get_parameter parallelDebug] } {
|
||||
set ok_to_delete_rt_tmp false
|
||||
}
|
||||
if {$rt::useElabCache == false} {
|
||||
set oldMIITMVal [rt::get_parameter maxInputIncreaseToMerge]; rt::set_parameter maxInputIncreaseToMerge 1000
|
||||
set oldCDPCRL [rt::get_parameter createDfgPartConstrRecurLimit]; rt::set_parameter createDfgPartConstrRecurLimit 1
|
||||
$rt::db readXRFFile
|
||||
rt::run_rtlelab -module $rt::top
|
||||
rt::set_parameter maxInputIncreaseToMerge $oldMIITMVal
|
||||
rt::set_parameter createDfgPartConstrRecurLimit $oldCDPCRL
|
||||
}
|
||||
|
||||
set rt::flowresult [ source $::env(SYNTH_COMMON)/flow.tcl ]
|
||||
rt::HARTNDb_stopJobStats
|
||||
if { $rt::flowresult == 1 } { return -code error }
|
||||
|
||||
|
||||
set hsKey [rt::get_parameter helper_shm_key]
|
||||
if { $hsKey != "" && [info exists ::env(BUILTIN_SYNTH)] && [rt::get_parameter enableParallelHelperSpawn] } {
|
||||
$rt::db killSynthHelper $hsKey
|
||||
}
|
||||
rt::set_parameter helper_shm_key ""
|
||||
if { [ info exists ::env(RT_TMP) ] } {
|
||||
if { [info exists ok_to_delete_rt_tmp] && $ok_to_delete_rt_tmp } {
|
||||
file delete -force $::env(RT_TMP)
|
||||
}
|
||||
}
|
||||
|
||||
source $::env(HRT_TCL_PATH)/rtSynthCleanup.tcl
|
||||
} ; #end uplevel
|
||||
} rt::result]
|
||||
|
||||
if { $rt::rc } {
|
||||
$rt::db resetHdlParse
|
||||
set hsKey [rt::get_parameter helper_shm_key]
|
||||
if { $hsKey != "" && [info exists ::env(BUILTIN_SYNTH)] && [rt::get_parameter enableParallelHelperSpawn] } {
|
||||
$rt::db killSynthHelper $hsKey
|
||||
}
|
||||
source $::env(HRT_TCL_PATH)/rtSynthCleanup.tcl
|
||||
return -code "error" $rt::result
|
||||
}
|
||||
@@ -1 +0,0 @@
|
||||
CRC performance measure: elapsed=00:00:00.001s;;memory_peak=2503.066MB;;memory_gain=0.000MB
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user