2341 lines
303 KiB
Plaintext
2341 lines
303 KiB
Plaintext
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#-----------------------------------------------------------
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# Vivado v2023.2 (64-bit)
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# SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023
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# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
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# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
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# Start of session at: Tue May 26 23:59:08 2026
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# Process ID: 26204
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# Current directory: C:/proj/pro_finish/can_parse_ctrl
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# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent27284 C:\proj\pro_finish\can_parse_ctrl\can_parse_ctrl.xpr
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# Log file: C:/proj/pro_finish/can_parse_ctrl/vivado.log
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# Journal file: C:/proj/pro_finish/can_parse_ctrl\vivado.jou
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# Running On: DESKTOP-EB3SDQ2, OS: Windows, CPU Frequency: 2112 MHz, CPU Physical cores: 16, Host memory: 16817 MB
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#-----------------------------------------------------------
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start_gui
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open_project C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.xpr
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.1 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.1/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.0 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.0/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.1 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.1/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.1 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.1/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
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INFO: [Project 1-313] Project file moved from 'E:/proj/proj_521/can_parse_ctrl' since last save.
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WARNING: [filemgmt 56-2] IP Repository Path: Could not find the directory 'C:/proj/proj_518/FPGA_DESIGN_IP/FPGA_DESIGN_IP', nor could it be found using path 'E:/proj/proj_518/FPGA_DESIGN_IP/FPGA_DESIGN_IP'.
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Scanning sources...
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Finished scanning sources
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INFO: [IP_Flow 19-234] Refreshing IP repositories
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WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'c:/proj/proj_518/FPGA_DESIGN_IP/FPGA_DESIGN_IP'; Can't find the specified path.
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If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
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INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2023.2/data/ip'.
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WARNING: [IP_Flow 19-3664] IP 'design_1_can_init_0_0' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_init_0_0/design_1_can_init_0_0.dcp'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_can_init_0_0' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_init_0_0/design_1_can_init_0_0_stub.v'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_can_init_0_0' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_init_0_0/design_1_can_init_0_0_stub.vhdl'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_can_init_0_0' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_init_0_0/design_1_can_init_0_0_sim_netlist.v'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_can_init_0_0' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_init_0_0/design_1_can_init_0_0_sim_netlist.vhdl'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_can_rx_parse_axi_0_0' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_rx_parse_axi_0_0/design_1_can_rx_parse_axi_0_0.dcp'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_can_rx_parse_axi_0_0' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_rx_parse_axi_0_0/design_1_can_rx_parse_axi_0_0_stub.v'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_can_rx_parse_axi_0_0' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_rx_parse_axi_0_0/design_1_can_rx_parse_axi_0_0_stub.vhdl'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_can_rx_parse_axi_0_0' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_rx_parse_axi_0_0/design_1_can_rx_parse_axi_0_0_sim_netlist.v'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_can_rx_parse_axi_0_0' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_rx_parse_axi_0_0/design_1_can_rx_parse_axi_0_0_sim_netlist.vhdl'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_uart_parse_real_0_0' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_uart_parse_real_0_0/design_1_uart_parse_real_0_0.dcp'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_uart_parse_real_0_0' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_uart_parse_real_0_0/design_1_uart_parse_real_0_0_stub.v'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_uart_parse_real_0_0' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_uart_parse_real_0_0/design_1_uart_parse_real_0_0_stub.vhdl'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_uart_parse_real_0_0' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_uart_parse_real_0_0/design_1_uart_parse_real_0_0_sim_netlist.v'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_uart_parse_real_0_0' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_uart_parse_real_0_0/design_1_uart_parse_real_0_0_sim_netlist.vhdl'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_ibufg_user_0_0' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_ibufg_user_0_0/design_1_ibufg_user_0_0.dcp'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_ibufg_user_0_0' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_ibufg_user_0_0/design_1_ibufg_user_0_0_stub.v'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_ibufg_user_0_0' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_ibufg_user_0_0/design_1_ibufg_user_0_0_stub.vhdl'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_ibufg_user_0_0' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_ibufg_user_0_0/design_1_ibufg_user_0_0_sim_netlist.v'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_ibufg_user_0_0' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_ibufg_user_0_0/design_1_ibufg_user_0_0_sim_netlist.vhdl'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_clk_wiz_0_0' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.dcp'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_clk_wiz_0_0' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_stub.v'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_clk_wiz_0_0' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_stub.vhdl'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_clk_wiz_0_0' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_sim_netlist.v'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_clk_wiz_0_0' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_sim_netlist.vhdl'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_util_vector_logic_0_0' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_0/design_1_util_vector_logic_0_0.dcp'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_util_vector_logic_0_0' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_0/design_1_util_vector_logic_0_0_stub.v'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_util_vector_logic_0_0' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_0/design_1_util_vector_logic_0_0_stub.vhdl'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_util_vector_logic_0_0' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_0/design_1_util_vector_logic_0_0_sim_netlist.v'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_util_vector_logic_0_0' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_0/design_1_util_vector_logic_0_0_sim_netlist.vhdl'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_util_vector_logic_0_1' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_1/design_1_util_vector_logic_0_1.dcp'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_util_vector_logic_0_1' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_1/design_1_util_vector_logic_0_1_stub.v'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_util_vector_logic_0_1' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_1/design_1_util_vector_logic_0_1_stub.vhdl'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_util_vector_logic_0_1' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_1/design_1_util_vector_logic_0_1_sim_netlist.v'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_util_vector_logic_0_1' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_1/design_1_util_vector_logic_0_1_sim_netlist.vhdl'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_can_0_2' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_0_2/design_1_can_0_2.dcp'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_can_0_2' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_0_2/design_1_can_0_2_stub.v'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_can_0_2' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_0_2/design_1_can_0_2_stub.vhdl'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_can_0_2' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_0_2/design_1_can_0_2_sim_netlist.v'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_can_0_2' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_0_2/design_1_can_0_2_sim_netlist.vhdl'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_can_0_3' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_0_3/design_1_can_0_3.dcp'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_can_0_3' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_0_3/design_1_can_0_3_stub.v'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_can_0_3' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_0_3/design_1_can_0_3_stub.vhdl'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_can_0_3' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_0_3/design_1_can_0_3_sim_netlist.v'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_can_0_3' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_0_3/design_1_can_0_3_sim_netlist.vhdl'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_smartconnect_0_0' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/design_1_smartconnect_0_0.dcp'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_smartconnect_0_0' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/design_1_smartconnect_0_0_stub.v'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_smartconnect_0_0' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/design_1_smartconnect_0_0_stub.vhdl'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_smartconnect_0_0' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/design_1_smartconnect_0_0_sim_netlist.v'. Please regenerate to continue.
|
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WARNING: [IP_Flow 19-3664] IP 'design_1_smartconnect_0_0' generated file not found 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/design_1_smartconnect_0_0_sim_netlist.vhdl'. Please regenerate to continue.
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WARNING: [BD 41-1661] One or more IPs have been locked in the design 'design_1.bd'. Please run report_ip_status for more details and recommendations on how to fix this issue.
|
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List of locked IPs:
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design_1_can_init_0_0
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design_1_can_rx_parse_axi_0_0
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|
|
design_1_ibufg_user_0_0
|
|||
|
|
design_1_uart_parse_real_0_0
|
|||
|
|
|
|||
|
|
open_project: Time (s): cpu = 00:00:16 ; elapsed = 00:00:09 . Memory (MB): peak = 1676.398 ; gain = 238.066
|
|||
|
|
update_compile_order -fileset sources_1
|
|||
|
|
open_bd_design {C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd}
|
|||
|
|
Reading block design file <C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd>...
|
|||
|
|
Adding component instance block -- xilinx.com:user:can_init:1.0 - can_init_0
|
|||
|
|
Adding component instance block -- xilinx.com:user:can_rx_parse_axi:1.0 - can_rx_parse_axi_0
|
|||
|
|
Adding component instance block -- xilinx.com:user:uart_parse_real:1.0 - uart_parse_real_0
|
|||
|
|
Adding component instance block -- xilinx.com:user:ibufg_user:1.0 - ibufg_user_0
|
|||
|
|
Adding component instance block -- xilinx.com:ip:clk_wiz:6.0 - clk_wiz_0
|
|||
|
|
Adding component instance block -- xilinx.com:ip:util_vector_logic:2.0 - util_vector_logic_0
|
|||
|
|
Adding component instance block -- xilinx.com:ip:util_vector_logic:2.0 - util_vector_logic_1
|
|||
|
|
Adding component instance block -- xilinx.com:ip:can:5.1 - can_0
|
|||
|
|
Adding component instance block -- xilinx.com:ip:can:5.1 - can_1
|
|||
|
|
Adding component instance block -- xilinx.com:ip:smartconnect:1.0 - smartconnect_0
|
|||
|
|
Successfully read diagram <design_1> from block design file <C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd>
|
|||
|
|
make_wrapper -files [get_files C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd] -top
|
|||
|
|
ERROR: [BD 41-1665] Unable to generate top-level wrapper HDL for the block design 'design_1.bd' is locked. Locked reason(s):
|
|||
|
|
* Block design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue.
|
|||
|
|
List of locked IPs:
|
|||
|
|
design_1_can_init_0_0
|
|||
|
|
design_1_can_rx_parse_axi_0_0
|
|||
|
|
design_1_ibufg_user_0_0
|
|||
|
|
design_1_uart_parse_real_0_0
|
|||
|
|
|
|||
|
|
ERROR: [Common 17-39] 'make_wrapper' failed due to earlier errors.
|
|||
|
|
update_ip_catalog -rebuild
|
|||
|
|
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
|||
|
|
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'c:/proj/proj_518/FPGA_DESIGN_IP/FPGA_DESIGN_IP'; Can't find the specified path.
|
|||
|
|
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
|
|||
|
|
update_ip_catalog -rebuild
|
|||
|
|
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
|||
|
|
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'c:/proj/proj_518/FPGA_DESIGN_IP/FPGA_DESIGN_IP'; Can't find the specified path.
|
|||
|
|
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
|
|||
|
|
set_property ip_repo_paths {} [current_project]
|
|||
|
|
update_ip_catalog
|
|||
|
|
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
|||
|
|
INFO: [IP_Flow 19-1704] No user IP repositories specified
|
|||
|
|
set_property ip_repo_paths C:/proj/FPGA_DESIGN_IP [current_project]
|
|||
|
|
update_ip_catalog
|
|||
|
|
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
|||
|
|
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/proj/FPGA_DESIGN_IP'.
|
|||
|
|
reset_run design_1_util_vector_logic_0_1_synth_1
|
|||
|
|
reset_run design_1_can_0_3_synth_1
|
|||
|
|
reset_run design_1_can_init_0_0_synth_1
|
|||
|
|
WARNING: [Vivado 12-1017] Problems encountered:
|
|||
|
|
1. Process appears to be on host 'DESKTOP-UONVKRQ' and cannot be killed from host 'DESKTOP-EB3SDQ2'
|
|||
|
|
|
|||
|
|
reset_run design_1_can_rx_parse_axi_0_0_synth_1
|
|||
|
|
WARNING: [Vivado 12-1017] Problems encountered:
|
|||
|
|
1. Process appears to be on host 'DESKTOP-UONVKRQ' and cannot be killed from host 'DESKTOP-EB3SDQ2'
|
|||
|
|
|
|||
|
|
reset_run design_1_uart_parse_real_0_0_synth_1
|
|||
|
|
WARNING: [Vivado 12-1017] Problems encountered:
|
|||
|
|
1. Process appears to be on host 'DESKTOP-UONVKRQ' and cannot be killed from host 'DESKTOP-EB3SDQ2'
|
|||
|
|
|
|||
|
|
reset_run design_1_ibufg_user_0_0_synth_1
|
|||
|
|
WARNING: [Vivado 12-1017] Problems encountered:
|
|||
|
|
1. Process appears to be on host 'DESKTOP-UONVKRQ' and cannot be killed from host 'DESKTOP-EB3SDQ2'
|
|||
|
|
|
|||
|
|
reset_run design_1_clk_wiz_0_0_synth_1
|
|||
|
|
WARNING: [Vivado 12-1017] Problems encountered:
|
|||
|
|
1. Process appears to be on host 'DESKTOP-UONVKRQ' and cannot be killed from host 'DESKTOP-EB3SDQ2'
|
|||
|
|
|
|||
|
|
reset_run design_1_util_vector_logic_0_0_synth_1
|
|||
|
|
WARNING: [Vivado 12-1017] Problems encountered:
|
|||
|
|
1. Process appears to be on host 'DESKTOP-UONVKRQ' and cannot be killed from host 'DESKTOP-EB3SDQ2'
|
|||
|
|
|
|||
|
|
reset_run design_1_can_0_2_synth_1
|
|||
|
|
WARNING: [Vivado 12-1017] Problems encountered:
|
|||
|
|
1. Process appears to be on host 'DESKTOP-UONVKRQ' and cannot be killed from host 'DESKTOP-EB3SDQ2'
|
|||
|
|
|
|||
|
|
reset_run design_1_smartconnect_0_0_synth_1
|
|||
|
|
WARNING: [Vivado 12-1017] Problems encountered:
|
|||
|
|
1. Process appears to be on host 'DESKTOP-UONVKRQ' and cannot be killed from host 'DESKTOP-EB3SDQ2'
|
|||
|
|
|
|||
|
|
regenerate_bd_layout
|
|||
|
|
validate_bd_design -force
|
|||
|
|
CRITICAL WARNING: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_0: The device(s) attached to /M00_AXI do not share a common clock domain with this smartconnect instance. Modify the clock domain values of the attached device(s) or re-customize this AXI SmartConnect instance to add a new clock pin and connect it to the same clock source of the IP attached to /M00_AXI to prevent further clock DRC violations.
|
|||
|
|
CRITICAL WARNING: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_0: The device(s) attached to /M01_AXI do not share a common clock domain with this smartconnect instance. Modify the clock domain values of the attached device(s) or re-customize this AXI SmartConnect instance to add a new clock pin and connect it to the same clock source of the IP attached to /M01_AXI to prevent further clock DRC violations.
|
|||
|
|
CRITICAL WARNING: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_0: The device(s) attached to /S00_AXI do not share a common clock domain with this smartconnect instance. Modify the clock domain values of the attached device(s) or re-customize this AXI SmartConnect instance to add a new clock pin and connect it to the same clock source of the IP attached to /S00_AXI to prevent further clock DRC violations.
|
|||
|
|
CRITICAL WARNING: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_0: The device(s) attached to /S00_AXI do not share a common clock frequency with this smartconnect instance. Modify the clock frequency values of the attached device(s) or re-customize this AXI SmartConnect instance to add a new clock pin and connect it to the same clock source of the IP attached to /S00_AXI to prevent further clock DRC violations.
|
|||
|
|
CRITICAL WARNING: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_0: The device(s) attached to /S01_AXI do not share a common clock domain with this smartconnect instance. Modify the clock domain values of the attached device(s) or re-customize this AXI SmartConnect instance to add a new clock pin and connect it to the same clock source of the IP attached to /S01_AXI to prevent further clock DRC violations.
|
|||
|
|
CRITICAL WARNING: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_0: The device(s) attached to /S01_AXI do not share a common clock frequency with this smartconnect instance. Modify the clock frequency values of the attached device(s) or re-customize this AXI SmartConnect instance to add a new clock pin and connect it to the same clock source of the IP attached to /S01_AXI to prevent further clock DRC violations.
|
|||
|
|
INFO: [BD 5-943] Reserving offset range <0x44A0_0000 [ 64K ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|||
|
|
INFO: [BD 5-943] Reserving offset range <0x44A1_0000 [ 64K ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|||
|
|
INFO: [BD 5-943] Reserving offset range <0x44A0_0000 [ 64K ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|||
|
|
INFO: [BD 5-943] Reserving offset range <0x44A1_0000 [ 64K ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|||
|
|
INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_0: SmartConnect design_1_smartconnect_0_0 is in Low-Area Mode.
|
|||
|
|
INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_0 clk_wiz propagate
|
|||
|
|
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
|
|||
|
|
Please check your design and connect them as needed:
|
|||
|
|
/can_rx_parse_axi_0/tlm_record_task_id
|
|||
|
|
/can_rx_parse_axi_0/tlm_downlink_task_id
|
|||
|
|
/can_rx_parse_axi_0/tlm_disk_status
|
|||
|
|
/can_rx_parse_axi_0/tlm_cam_dt_status
|
|||
|
|
/can_rx_parse_axi_0/tlm_lvds
|
|||
|
|
/can_rx_parse_axi_0/tlm_reconfig
|
|||
|
|
/can_rx_parse_axi_0/tlm_fpga_temp
|
|||
|
|
/can_rx_parse_axi_0/tlm_compress_flash
|
|||
|
|
|
|||
|
|
make_wrapper -files [get_files C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd] -top
|
|||
|
|
INFO: [BD 41-1662] The design 'design_1.bd' is already validated. Therefore parameter propagation will not be re-run.
|
|||
|
|
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
|
|||
|
|
Please check your design and connect them as needed:
|
|||
|
|
/can_rx_parse_axi_0/tlm_record_task_id
|
|||
|
|
/can_rx_parse_axi_0/tlm_downlink_task_id
|
|||
|
|
/can_rx_parse_axi_0/tlm_disk_status
|
|||
|
|
/can_rx_parse_axi_0/tlm_cam_dt_status
|
|||
|
|
/can_rx_parse_axi_0/tlm_lvds
|
|||
|
|
/can_rx_parse_axi_0/tlm_reconfig
|
|||
|
|
/can_rx_parse_axi_0/tlm_fpga_temp
|
|||
|
|
/can_rx_parse_axi_0/tlm_compress_flash
|
|||
|
|
|
|||
|
|
WARNING: [BD 41-2671] The dangling interface net <m00_aw_node_M_AXIS_ARB> will not be written out to the BD file.
|
|||
|
|
WARNING: [BD 41-2671] The dangling interface net <m01_aw_node_M_AXIS_ARB> will not be written out to the BD file.
|
|||
|
|
Wrote : <C:\proj\pro_finish\can_parse_ctrl\can_parse_ctrl.srcs\sources_1\bd\design_1\design_1.bd>
|
|||
|
|
Wrote : <C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
|
|||
|
|
Verilog Output written to : c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/synth/design_1.v
|
|||
|
|
Verilog Output written to : c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/sim/design_1.v
|
|||
|
|
Verilog Output written to : c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
|
|||
|
|
add_files -norecurse c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
|
|||
|
|
launch_runs impl_1 -to_step write_bitstream -jobs 24
|
|||
|
|
INFO: [BD 41-1662] The design 'design_1.bd' is already validated. Therefore parameter propagation will not be re-run.
|
|||
|
|
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
|
|||
|
|
Please check your design and connect them as needed:
|
|||
|
|
/can_rx_parse_axi_0/tlm_record_task_id
|
|||
|
|
/can_rx_parse_axi_0/tlm_downlink_task_id
|
|||
|
|
/can_rx_parse_axi_0/tlm_disk_status
|
|||
|
|
/can_rx_parse_axi_0/tlm_cam_dt_status
|
|||
|
|
/can_rx_parse_axi_0/tlm_lvds
|
|||
|
|
/can_rx_parse_axi_0/tlm_reconfig
|
|||
|
|
/can_rx_parse_axi_0/tlm_fpga_temp
|
|||
|
|
/can_rx_parse_axi_0/tlm_compress_flash
|
|||
|
|
|
|||
|
|
Verilog Output written to : c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/synth/design_1.v
|
|||
|
|
Verilog Output written to : c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/sim/design_1.v
|
|||
|
|
Verilog Output written to : c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
|
|||
|
|
Exporting to file c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/hw_handoff/design_1_smartconnect_0_0.hwh
|
|||
|
|
Generated Hardware Definition File c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/synth/design_1_smartconnect_0_0.hwdef
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block smartconnect_0 .
|
|||
|
|
Exporting to file c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh
|
|||
|
|
Generated Hardware Definition File c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/synth/design_1.hwdef
|
|||
|
|
INFO: [IP_Flow 19-6930] IPCACHE: runCacheChecks() number of threads = 8
|
|||
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_can_0_2
|
|||
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_can_0_3
|
|||
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_can_init_0_0
|
|||
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_can_rx_parse_axi_0_0
|
|||
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_clk_wiz_0_0
|
|||
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_ibufg_user_0_0
|
|||
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_smartconnect_0_0
|
|||
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_uart_parse_real_0_0
|
|||
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_util_vector_logic_0_0
|
|||
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_util_vector_logic_0_1
|
|||
|
|
INFO: [IP_Flow 19-8020] IPCACHE: runCacheChecks() calling threadPool finishWork()
|
|||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_can_0_2
|
|||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_clk_wiz_0_0
|
|||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_can_0_3
|
|||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_can_init_0_0
|
|||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_can_rx_parse_axi_0_0
|
|||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ibufg_user_0_0
|
|||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_smartconnect_0_0
|
|||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_uart_parse_real_0_0
|
|||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_util_vector_logic_0_0
|
|||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_util_vector_logic_0_1
|
|||
|
|
[Wed May 27 00:02:53 2026] Launched design_1_can_init_0_0_synth_1, design_1_can_rx_parse_axi_0_0_synth_1, design_1_uart_parse_real_0_0_synth_1, design_1_ibufg_user_0_0_synth_1, design_1_clk_wiz_0_0_synth_1, design_1_util_vector_logic_0_0_synth_1, design_1_util_vector_logic_0_1_synth_1, design_1_can_0_2_synth_1, design_1_can_0_3_synth_1, design_1_smartconnect_0_0_synth_1, synth_1...
|
|||
|
|
Run output will be captured here:
|
|||
|
|
design_1_can_init_0_0_synth_1: C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.runs/design_1_can_init_0_0_synth_1/runme.log
|
|||
|
|
design_1_can_rx_parse_axi_0_0_synth_1: C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.runs/design_1_can_rx_parse_axi_0_0_synth_1/runme.log
|
|||
|
|
design_1_uart_parse_real_0_0_synth_1: C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.runs/design_1_uart_parse_real_0_0_synth_1/runme.log
|
|||
|
|
design_1_ibufg_user_0_0_synth_1: C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.runs/design_1_ibufg_user_0_0_synth_1/runme.log
|
|||
|
|
design_1_clk_wiz_0_0_synth_1: C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.runs/design_1_clk_wiz_0_0_synth_1/runme.log
|
|||
|
|
design_1_util_vector_logic_0_0_synth_1: C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.runs/design_1_util_vector_logic_0_0_synth_1/runme.log
|
|||
|
|
design_1_util_vector_logic_0_1_synth_1: C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.runs/design_1_util_vector_logic_0_1_synth_1/runme.log
|
|||
|
|
design_1_can_0_2_synth_1: C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.runs/design_1_can_0_2_synth_1/runme.log
|
|||
|
|
design_1_can_0_3_synth_1: C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.runs/design_1_can_0_3_synth_1/runme.log
|
|||
|
|
design_1_smartconnect_0_0_synth_1: C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.runs/design_1_smartconnect_0_0_synth_1/runme.log
|
|||
|
|
synth_1: C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.runs/synth_1/runme.log
|
|||
|
|
[Wed May 27 00:02:54 2026] Launched impl_1...
|
|||
|
|
Run output will be captured here: C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.runs/impl_1/runme.log
|
|||
|
|
launch_runs: Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2183.352 ; gain = 84.348
|
|||
|
|
file mkdir C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/constrs_1
|
|||
|
|
file mkdir C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/constrs_1/new
|
|||
|
|
close [ open C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/constrs_1/new/can_parse_ctrl.xdc w ]
|
|||
|
|
add_files -fileset constrs_1 C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/constrs_1/new/can_parse_ctrl.xdc
|
|||
|
|
reset_run synth_1
|
|||
|
|
INFO: [Project 1-1160] Copying file C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.runs/synth_1/design_1_wrapper.dcp to C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/utils_1/imports/synth_1 and adding it to utils fileset
|
|||
|
|
launch_runs impl_1 -to_step write_bitstream -jobs 24
|
|||
|
|
[Wed May 27 00:20:41 2026] Launched synth_1...
|
|||
|
|
Run output will be captured here: C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.runs/synth_1/runme.log
|
|||
|
|
[Wed May 27 00:20:41 2026] Launched impl_1...
|
|||
|
|
Run output will be captured here: C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.runs/impl_1/runme.log
|
|||
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd]
|
|||
|
|
synth_design -rtl -rtl_skip_mlo -name rtl_1
|
|||
|
|
Command: synth_design -rtl -rtl_skip_mlo -name rtl_1
|
|||
|
|
Starting synth_design
|
|||
|
|
Using part: xc7vx690tffg1761-2
|
|||
|
|
Top: design_1_wrapper
|
|||
|
|
INFO: [Device 21-403] Loading part xc7vx690tffg1761-2
|
|||
|
|
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
|
|||
|
|
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
|
|||
|
|
INFO: [Synth 8-7075] Helper process launched with PID 27376
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2941.422 ; gain = 438.355
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'design_1_wrapper' [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v:13]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'design_1' [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/synth/design_1.v:13]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'design_1_can_0_2' [C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_can_0_2_stub.v:6]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'design_1_can_0_2' (0#1) [C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_can_0_2_stub.v:6]
|
|||
|
|
WARNING: [Synth 8-7071] port 'ip2bus_intrevent' of module 'design_1_can_0_2' is unconnected for instance 'can_0' [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/synth/design_1.v:111]
|
|||
|
|
WARNING: [Synth 8-7023] instance 'can_0' of module 'design_1_can_0_2' has 23 connections declared, but only 22 given [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/synth/design_1.v:111]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'design_1_can_0_3' [C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_can_0_3_stub.v:6]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'design_1_can_0_3' (0#1) [C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_can_0_3_stub.v:6]
|
|||
|
|
WARNING: [Synth 8-7071] port 'ip2bus_intrevent' of module 'design_1_can_0_3' is unconnected for instance 'can_1' [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/synth/design_1.v:134]
|
|||
|
|
WARNING: [Synth 8-7023] instance 'can_1' of module 'design_1_can_0_3' has 23 connections declared, but only 22 given [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/synth/design_1.v:134]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'design_1_can_init_0_0' [C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_can_init_0_0_stub.v:6]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'design_1_can_init_0_0' (0#1) [C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_can_init_0_0_stub.v:6]
|
|||
|
|
WARNING: [Synth 8-7071] port 'init_done' of module 'design_1_can_init_0_0' is unconnected for instance 'can_init_0' [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/synth/design_1.v:157]
|
|||
|
|
WARNING: [Synth 8-7071] port 'state' of module 'design_1_can_init_0_0' is unconnected for instance 'can_init_0' [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/synth/design_1.v:157]
|
|||
|
|
WARNING: [Synth 8-7023] instance 'can_init_0' of module 'design_1_can_init_0_0' has 13 connections declared, but only 11 given [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/synth/design_1.v:157]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'design_1_can_rx_parse_axi_0_0' [C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_can_rx_parse_axi_0_0_stub.v:6]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'design_1_can_rx_parse_axi_0_0' (0#1) [C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_can_rx_parse_axi_0_0_stub.v:6]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'design_1_clk_wiz_0_0' [C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_clk_wiz_0_0_stub.v:6]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'design_1_clk_wiz_0_0' (0#1) [C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_clk_wiz_0_0_stub.v:6]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'design_1_ibufg_user_0_0' [C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_ibufg_user_0_0_stub.v:6]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'design_1_ibufg_user_0_0' (0#1) [C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_ibufg_user_0_0_stub.v:6]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'design_1_smartconnect_0_0' [C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_smartconnect_0_0_stub.v:6]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'design_1_smartconnect_0_0' (0#1) [C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_smartconnect_0_0_stub.v:6]
|
|||
|
|
WARNING: [Synth 8-7071] port 'S00_AXI_bresp' of module 'design_1_smartconnect_0_0' is unconnected for instance 'smartconnect_0' [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/synth/design_1.v:206]
|
|||
|
|
WARNING: [Synth 8-7071] port 'M00_AXI_awprot' of module 'design_1_smartconnect_0_0' is unconnected for instance 'smartconnect_0' [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/synth/design_1.v:206]
|
|||
|
|
WARNING: [Synth 8-7071] port 'M00_AXI_arprot' of module 'design_1_smartconnect_0_0' is unconnected for instance 'smartconnect_0' [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/synth/design_1.v:206]
|
|||
|
|
WARNING: [Synth 8-7071] port 'M01_AXI_awprot' of module 'design_1_smartconnect_0_0' is unconnected for instance 'smartconnect_0' [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/synth/design_1.v:206]
|
|||
|
|
WARNING: [Synth 8-7071] port 'M01_AXI_arprot' of module 'design_1_smartconnect_0_0' is unconnected for instance 'smartconnect_0' [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/synth/design_1.v:206]
|
|||
|
|
WARNING: [Synth 8-7023] instance 'smartconnect_0' of module 'design_1_smartconnect_0_0' has 70 connections declared, but only 65 given [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/synth/design_1.v:206]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'design_1_uart_parse_real_0_0' [C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_uart_parse_real_0_0_stub.v:6]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'design_1_uart_parse_real_0_0' (0#1) [C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_uart_parse_real_0_0_stub.v:6]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'design_1_util_vector_logic_0_0' [C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_util_vector_logic_0_0_stub.v:6]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'design_1_util_vector_logic_0_0' (0#1) [C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_util_vector_logic_0_0_stub.v:6]
|
|||
|
|
INFO: [Synth 8-6157] synthesizing module 'design_1_util_vector_logic_0_1' [C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_util_vector_logic_0_1_stub.v:6]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'design_1_util_vector_logic_0_1' (0#1) [C:/proj/pro_finish/can_parse_ctrl/.Xil/Vivado-26204-DESKTOP-EB3SDQ2/realtime/design_1_util_vector_logic_0_1_stub.v:6]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'design_1' (0#1) [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/synth/design_1.v:13]
|
|||
|
|
INFO: [Synth 8-6155] done synthesizing module 'design_1_wrapper' (0#1) [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v:13]
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 3055.828 ; gain = 552.762
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Start Handling Custom Attributes
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 3073.730 ; gain = 570.664
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 3073.730 ; gain = 570.664
|
|||
|
|
---------------------------------------------------------------------------------
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_0_2/design_1_can_0_2.dcp' for cell 'design_1_i/can_0'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_0_3/design_1_can_0_3.dcp' for cell 'design_1_i/can_1'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_init_0_0/design_1_can_init_0_0.dcp' for cell 'design_1_i/can_init_0'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_rx_parse_axi_0_0/design_1_can_rx_parse_axi_0_0.dcp' for cell 'design_1_i/can_rx_parse_axi_0'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.dcp' for cell 'design_1_i/clk_wiz_0'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_ibufg_user_0_0/design_1_ibufg_user_0_0.dcp' for cell 'design_1_i/ibufg_user_0'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/design_1_smartconnect_0_0.dcp' for cell 'design_1_i/smartconnect_0'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_uart_parse_real_0_0/design_1_uart_parse_real_0_0.dcp' for cell 'design_1_i/uart_parse_real_0'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_0/design_1_util_vector_logic_0_0.dcp' for cell 'design_1_i/util_vector_logic_0'
|
|||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_1/design_1_util_vector_logic_0_1.dcp' for cell 'design_1_i/util_vector_logic_1'
|
|||
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.180 . Memory (MB): peak = 3104.293 ; gain = 0.000
|
|||
|
|
INFO: [Netlist 29-17] Analyzing 455 Unisim elements for replacement
|
|||
|
|
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
|||
|
|
INFO: [Project 1-479] Netlist was created with Vivado 2023.2
|
|||
|
|
INFO: [Project 1-570] Preparing netlist for logic optimization
|
|||
|
|
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'design_1_i/clk_wiz_0/clk_in1' is not directly connected to top level port. 'IBUF_LOW_PWR' is ignored for synthesis but preserved for implementation.
|
|||
|
|
|
|||
|
|
Processing XDC Constraints
|
|||
|
|
Initializing timing engine
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_uart_parse_real_0_0/src/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/uart_parse_real_0/inst/u_dut/u_uart_data_parse/u_ila_uart_data_parse/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_uart_parse_real_0_0/src/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/uart_parse_real_0/inst/u_dut/u_uart_data_parse/u_ila_uart_data_parse/inst'
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_board.xdc] for cell 'design_1_i/clk_wiz_0/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_board.xdc] for cell 'design_1_i/clk_wiz_0/inst'
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xdc] for cell 'design_1_i/clk_wiz_0/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xdc] for cell 'design_1_i/clk_wiz_0/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_0_2/design_1_can_0_2.xdc] for cell 'design_1_i/can_0/U0'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_0_2/design_1_can_0_2.xdc] for cell 'design_1_i/can_0/U0'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_0_2/design_1_can_0_2.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_0_3/design_1_can_0_3.xdc] for cell 'design_1_i/can_1/U0'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_0_3/design_1_can_0_3.xdc] for cell 'design_1_i/can_1/U0'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_0_3/design_1_can_0_3.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_1/bd_48ac_psr_aclk_0_board.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_1/bd_48ac_psr_aclk_0_board.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_1/bd_48ac_psr_aclk_0.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_1/bd_48ac_psr_aclk_0.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_1/bd_48ac_psr_aclk_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_12/bd_48ac_arni_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/switchboards/i_nodes/i_ar_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_12/bd_48ac_arni_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/switchboards/i_nodes/i_ar_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_12/bd_48ac_arni_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_13/bd_48ac_rni_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/switchboards/i_nodes/i_r_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_13/bd_48ac_rni_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/switchboards/i_nodes/i_r_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_13/bd_48ac_rni_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_14/bd_48ac_awni_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/switchboards/i_nodes/i_aw_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_14/bd_48ac_awni_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/switchboards/i_nodes/i_aw_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_14/bd_48ac_awni_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_15/bd_48ac_wni_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/switchboards/i_nodes/i_w_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_15/bd_48ac_wni_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/switchboards/i_nodes/i_w_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_15/bd_48ac_wni_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_16/bd_48ac_bni_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/switchboards/i_nodes/i_b_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_16/bd_48ac_bni_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/switchboards/i_nodes/i_b_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_16/bd_48ac_bni_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_21/bd_48ac_sawn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s00_nodes/s00_aw_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_21/bd_48ac_sawn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s00_nodes/s00_aw_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_21/bd_48ac_sawn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_22/bd_48ac_swn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s00_nodes/s00_w_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_22/bd_48ac_swn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s00_nodes/s00_w_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_22/bd_48ac_swn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_23/bd_48ac_sbn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s00_nodes/s00_b_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_23/bd_48ac_sbn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s00_nodes/s00_b_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_23/bd_48ac_sbn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_28/bd_48ac_sarn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_ar_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_28/bd_48ac_sarn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_ar_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_28/bd_48ac_sarn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_29/bd_48ac_srn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_r_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_29/bd_48ac_srn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_r_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_29/bd_48ac_srn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_30/bd_48ac_sawn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_30/bd_48ac_sawn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_30/bd_48ac_sawn_1_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_31/bd_48ac_swn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_31/bd_48ac_swn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_31/bd_48ac_swn_1_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_32/bd_48ac_sbn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_32/bd_48ac_sbn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_32/bd_48ac_sbn_1_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_34/bd_48ac_m00arn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_34/bd_48ac_m00arn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_34/bd_48ac_m00arn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_35/bd_48ac_m00rn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_35/bd_48ac_m00rn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_35/bd_48ac_m00rn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_36/bd_48ac_m00awn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_36/bd_48ac_m00awn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_36/bd_48ac_m00awn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_37/bd_48ac_m00wn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_37/bd_48ac_m00wn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_37/bd_48ac_m00wn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_38/bd_48ac_m00bn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_38/bd_48ac_m00bn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_38/bd_48ac_m00bn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_41/bd_48ac_m01arn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_ar_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_41/bd_48ac_m01arn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_ar_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_41/bd_48ac_m01arn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_42/bd_48ac_m01rn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_r_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_42/bd_48ac_m01rn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_r_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_42/bd_48ac_m01rn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_43/bd_48ac_m01awn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_aw_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_43/bd_48ac_m01awn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_aw_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_43/bd_48ac_m01awn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_44/bd_48ac_m01wn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_w_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_44/bd_48ac_m01wn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_w_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_44/bd_48ac_m01wn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_45/bd_48ac_m01bn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_b_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_45/bd_48ac_m01bn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_b_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_45/bd_48ac_m01bn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/smartconnect.xdc] for cell 'design_1_i/smartconnect_0/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/smartconnect.xdc] for cell 'design_1_i/smartconnect_0/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/smartconnect.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
INFO: [Timing 38-2] Deriving generated clocks
|
|||
|
|
Parsing XDC File [C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/constrs_1/new/can_parse_ctrl.xdc]
|
|||
|
|
WARNING: [Vivado 12-584] No ports matched 'rx_i'. [C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/constrs_1/new/can_parse_ctrl.xdc:14]
|
|||
|
|
WARNING: [Vivado 12-584] No ports matched 'rx_i'. [C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/constrs_1/new/can_parse_ctrl.xdc:15]
|
|||
|
|
Finished Parsing XDC File [C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/constrs_1/new/can_parse_ctrl.xdc]
|
|||
|
|
WARNING: [Project 1-498] One or more constraints failed evaluation while reading constraint file [C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/constrs_1/new/can_parse_ctrl.xdc] and the design contains unresolved black boxes. These constraints will be read post-synthesis (as long as their source constraint file is marked as used_in_implementation) and should be applied correctly then. You should review the constraints listed in the file [.Xil/design_1_wrapper_propImpl.xdc] and check the run log file to verify that these constraints were correctly applied.
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
INFO: [Project 1-1714] 78 XPM XDC files have been applied to the design.
|
|||
|
|
Completed Processing XDC Constraints
|
|||
|
|
|
|||
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 3206.027 ; gain = 0.000
|
|||
|
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
|||
|
|
A total of 122 instances were transformed.
|
|||
|
|
CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 120 instances
|
|||
|
|
RAM16X1D => RAM32X1D (RAMD32(x2)): 2 instances
|
|||
|
|
|
|||
|
|
RTL Elaboration Complete: : Time (s): cpu = 00:00:16 ; elapsed = 00:00:12 . Memory (MB): peak = 3620.969 ; gain = 1117.902
|
|||
|
|
77 Infos, 17 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
|||
|
|
synth_design completed successfully
|
|||
|
|
synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:17 . Memory (MB): peak = 3625.852 ; gain = 1432.227
|
|||
|
|
place_ports rx_i_0 K38
|
|||
|
|
set_property IOSTANDARD HSTL_I_12 [get_ports [list rx_i_0]]
|
|||
|
|
set_property IOSTANDARD HSTL_I_12 [get_ports [list rx_i_0]]
|
|||
|
|
set_property IOSTANDARD LVCMOS18 [get_ports [list rx_i_0]]
|
|||
|
|
set_property IOSTANDARD LVCMOS18 [get_ports [list can_phy_rx_0]]
|
|||
|
|
set_property target_constrs_file C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/constrs_1/new/can_parse_ctrl.xdc [current_fileset -constrset]
|
|||
|
|
save_constraints -force
|
|||
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd]
|
|||
|
|
refresh_design
|
|||
|
|
INFO: [Project 1-570] Preparing netlist for logic optimization
|
|||
|
|
|
|||
|
|
Processing XDC Constraints
|
|||
|
|
Initializing timing engine
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_uart_parse_real_0_0/src/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/uart_parse_real_0/inst/u_dut/u_uart_data_parse/u_ila_uart_data_parse/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_uart_parse_real_0_0/src/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/uart_parse_real_0/inst/u_dut/u_uart_data_parse/u_ila_uart_data_parse/inst'
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_board.xdc] for cell 'design_1_i/clk_wiz_0/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_board.xdc] for cell 'design_1_i/clk_wiz_0/inst'
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xdc] for cell 'design_1_i/clk_wiz_0/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xdc] for cell 'design_1_i/clk_wiz_0/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_0_2/design_1_can_0_2.xdc] for cell 'design_1_i/can_0/U0'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_0_2/design_1_can_0_2.xdc] for cell 'design_1_i/can_0/U0'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_0_2/design_1_can_0_2.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_0_3/design_1_can_0_3.xdc] for cell 'design_1_i/can_1/U0'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_0_3/design_1_can_0_3.xdc] for cell 'design_1_i/can_1/U0'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_0_3/design_1_can_0_3.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_1/bd_48ac_psr_aclk_0_board.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_1/bd_48ac_psr_aclk_0_board.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_1/bd_48ac_psr_aclk_0.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_1/bd_48ac_psr_aclk_0.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_1/bd_48ac_psr_aclk_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_12/bd_48ac_arni_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/switchboards/i_nodes/i_ar_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_12/bd_48ac_arni_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/switchboards/i_nodes/i_ar_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_12/bd_48ac_arni_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_13/bd_48ac_rni_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/switchboards/i_nodes/i_r_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_13/bd_48ac_rni_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/switchboards/i_nodes/i_r_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_13/bd_48ac_rni_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_14/bd_48ac_awni_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/switchboards/i_nodes/i_aw_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_14/bd_48ac_awni_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/switchboards/i_nodes/i_aw_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_14/bd_48ac_awni_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_15/bd_48ac_wni_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/switchboards/i_nodes/i_w_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_15/bd_48ac_wni_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/switchboards/i_nodes/i_w_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_15/bd_48ac_wni_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_16/bd_48ac_bni_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/switchboards/i_nodes/i_b_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_16/bd_48ac_bni_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/switchboards/i_nodes/i_b_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_16/bd_48ac_bni_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_21/bd_48ac_sawn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s00_nodes/s00_aw_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_21/bd_48ac_sawn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s00_nodes/s00_aw_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_21/bd_48ac_sawn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_22/bd_48ac_swn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s00_nodes/s00_w_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_22/bd_48ac_swn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s00_nodes/s00_w_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_22/bd_48ac_swn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_23/bd_48ac_sbn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s00_nodes/s00_b_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_23/bd_48ac_sbn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s00_nodes/s00_b_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_23/bd_48ac_sbn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_28/bd_48ac_sarn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_ar_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_28/bd_48ac_sarn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_ar_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_28/bd_48ac_sarn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_29/bd_48ac_srn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_r_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_29/bd_48ac_srn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_r_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_29/bd_48ac_srn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_30/bd_48ac_sawn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_30/bd_48ac_sawn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_30/bd_48ac_sawn_1_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_31/bd_48ac_swn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_31/bd_48ac_swn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_31/bd_48ac_swn_1_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_32/bd_48ac_sbn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_32/bd_48ac_sbn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_32/bd_48ac_sbn_1_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_34/bd_48ac_m00arn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_34/bd_48ac_m00arn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_34/bd_48ac_m00arn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_35/bd_48ac_m00rn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_35/bd_48ac_m00rn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_35/bd_48ac_m00rn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_36/bd_48ac_m00awn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_36/bd_48ac_m00awn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_36/bd_48ac_m00awn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_37/bd_48ac_m00wn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_37/bd_48ac_m00wn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_37/bd_48ac_m00wn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_38/bd_48ac_m00bn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_38/bd_48ac_m00bn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_38/bd_48ac_m00bn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_41/bd_48ac_m01arn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_ar_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_41/bd_48ac_m01arn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_ar_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_41/bd_48ac_m01arn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_42/bd_48ac_m01rn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_r_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_42/bd_48ac_m01rn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_r_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_42/bd_48ac_m01rn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_43/bd_48ac_m01awn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_aw_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_43/bd_48ac_m01awn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_aw_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_43/bd_48ac_m01awn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_44/bd_48ac_m01wn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_w_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_44/bd_48ac_m01wn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_w_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_44/bd_48ac_m01wn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_45/bd_48ac_m01bn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_b_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_45/bd_48ac_m01bn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_b_node/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_45/bd_48ac_m01bn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/smartconnect.xdc] for cell 'design_1_i/smartconnect_0/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/smartconnect.xdc] for cell 'design_1_i/smartconnect_0/inst'
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/smartconnect.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
INFO: [Timing 38-2] Deriving generated clocks
|
|||
|
|
Parsing XDC File [C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/constrs_1/new/can_parse_ctrl.xdc]
|
|||
|
|
Finished Parsing XDC File [C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/constrs_1/new/can_parse_ctrl.xdc]
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|||
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|||
|
|
INFO: [Project 1-1714] 78 XPM XDC files have been applied to the design.
|
|||
|
|
Completed Processing XDC Constraints
|
|||
|
|
|
|||
|
|
reset_run synth_1
|
|||
|
|
INFO: [Project 1-1161] Replacing file C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/utils_1/imports/synth_1/design_1_wrapper.dcp with file C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.runs/synth_1/design_1_wrapper.dcp
|
|||
|
|
launch_runs impl_1 -to_step write_bitstream -jobs 24
|
|||
|
|
[Wed May 27 00:40:52 2026] Launched synth_1...
|
|||
|
|
Run output will be captured here: C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.runs/synth_1/runme.log
|
|||
|
|
[Wed May 27 00:40:52 2026] Launched impl_1...
|
|||
|
|
Run output will be captured here: C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.runs/impl_1/runme.log
|
|||
|
|
open_bd_design {C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd}
|
|||
|
|
get_property CLK_DOMAIN [get_pins design_1_smartconnect_0_0/aclk]
|
|||
|
|
WARNING: [Vivado 12-508] No pins matched 'design_1_smartconnect_0_0/aclk'.
|
|||
|
|
ERROR: [Common 17-55] 'get_property' expects at least one object.
|
|||
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|||
|
|
get_property CLK_DOMAIN [get_pins design_1_smartconnect_0/aclk]
|
|||
|
|
WARNING: [Vivado 12-508] No pins matched 'design_1_smartconnect_0/aclk'.
|
|||
|
|
ERROR: [Common 17-55] 'get_property' expects at least one object.
|
|||
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|||
|
|
get_pins -hierarchical -filter {NAME=~ *smartconnect*/aclk}
|
|||
|
|
design_1_i/smartconnect_0/aclk design_1_i/smartconnect_0/inst/aclk design_1_i/smartconnect_0/inst/clk_map/aclk design_1_i/smartconnect_0/inst/m00_exit_pipeline/aclk design_1_i/smartconnect_0/inst/m00_nodes/aclk design_1_i/smartconnect_0/inst/m01_exit_pipeline/aclk design_1_i/smartconnect_0/inst/m01_nodes/aclk design_1_i/smartconnect_0/inst/s00_entry_pipeline/aclk design_1_i/smartconnect_0/inst/s00_nodes/aclk design_1_i/smartconnect_0/inst/s01_entry_pipeline/aclk design_1_i/smartconnect_0/inst/s01_nodes/aclk design_1_i/smartconnect_0/inst/switchboards/aclk design_1_i/smartconnect_0/inst/clk_map/psr_aclk/aclk design_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0/aclk design_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0/EXT_LPF/aclk design_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0/SEQ/aclk design_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/aclk design_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0/SEQ/SEQ_COUNTER/aclk design_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/aclk design_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/aclk design_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/exit_inst/aclk design_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/aclk design_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/aclk design_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/aclk design_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/aclk design_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/aclk design_1_i/smartconnect_0/inst/m00_sc2axi/inst/aclk design_1_i/smartconnect_0/inst/m01_exit_pipeline/m01_exit/aclk design_1_i/smartconnect_0/inst/m01_exit_pipeline/m01_exit/inst/aclk design_1_i/smartconnect_0/inst/m01_exit_pipeline/m01_exit/inst/exit_inst/aclk design_1_i/smartconnect_0/inst/m01_nodes/m01_ar_node/aclk design_1_i/smartconnect_0/inst/m01_nodes/m01_aw_node/aclk design_1_i/smartconnect_0/inst/m01_nodes/m01_b_node/aclk design_1_i/smartconnect_0/inst/m01_nodes/m01_r_node/aclk design_1_i/smartconnect_0/inst/m01_nodes/m01_w_node/aclk design_1_i/smartconnect_0/inst/m01_sc2axi/inst/aclk design_1_i/smartconnect_0/inst/s00_axi2sc/inst/aclk design_1_i/smartconnect_0/inst/s00_entry_pipeline/s00_mmu/aclk design_1_i/smartconnect_0/inst/s00_entry_pipeline/s00_si_converter/aclk design_1_i/smartconnect_0/inst/s00_entry_pipeline/s00_transaction_regulator/aclk design_1_i/smartconnect_0/inst/s00_entry_pipeline/s00_mmu/inst/aclk design_1_i/smartconnect_0/inst/s00_entry_pipeline/s00_mmu/inst/aw_reg_stall/aclk design_1_i/smartconnect_0/inst/s00_entry_pipeline/s00_mmu/inst/gen_endpoint.decerr_slave_inst/aclk design_1_i/smartconnect_0/inst/s00_entry_pipeline/s00_mmu/inst/gen_wroute_reg.wroute_split/aclk design_1_i/smartconnect_0/inst/s00_entry_pipeline/s00_si_converter/inst/aclk design_1_i/smartconnect_0/inst/s00_entry_pipeline/s00_si_converter/inst/gen_normal.splitter_inst/aclk design_1_i/smartconnect_0/inst/s00_entry_pipeline/s00_transaction_regulator/inst/aclk design_1_i/smartconnect_0/inst/s00_entry_pipeline/s00_transaction_regulator/inst/gen_endpoint.gen_w_singleorder.w_singleorder/aclk design_1_i/smartconnect_0/inst/s00_nodes/s00_aw_node/aclk design_1_i/smartconnect_0/inst/s00_nodes/s00_b_node/aclk design_1_i/smartconnect_0/inst/s00_nodes/s00_w_node/aclk design_1_i/smartconnect_0/inst/s01_axi2sc/inst/aclk design_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_mmu/aclk design_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_si_converter/aclk design_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_transaction_regulator/aclk design_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_mmu/inst/aclk design_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_mmu/inst/ar_reg_stall/aclk design_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_mmu/inst/aw_reg_stall/aclk design_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_mmu/inst/gen_endpoint.decerr_slave_inst/aclk design_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_mmu/inst/gen_wroute_reg.wroute_split/aclk design_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_si_converter/inst/aclk design_1_i/smartconnect_0/inst/s01_entry_pipeline/s01_si_converter/inst/gen_normal.splitter_
|
|||
|
|
get_property CLK_DOMAIN [get_pins design_1_i/can_0/aclk]
|
|||
|
|
WARNING: [Vivado 12-508] No pins matched 'design_1_i/can_0/aclk'.
|
|||
|
|
ERROR: [Common 17-55] 'get_property' expects at least one object.
|
|||
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|||
|
|
get_property CLK_DOMAIN [get_pins design_1_i/smartconnect_0/aclk]
|
|||
|
|
get_property CLK_DOMAIN [get_pins design_1_i/can_0/aclk]
|
|||
|
|
WARNING: [Vivado 12-508] No pins matched 'design_1_i/can_0/aclk'.
|
|||
|
|
ERROR: [Common 17-55] 'get_property' expects at least one object.
|
|||
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|||
|
|
get_pins -of_objects [get_cells design_1_i/can_0] -filter {DIRECTION == IN && NAME =~ *clk*}
|
|||
|
|
design_1_i/can_0/can_clk design_1_i/can_0/s_axi_aclk
|
|||
|
|
get_property CLK_DOMAIN [get_pins design_1_i/can_0/s_axi_aclk]
|
|||
|
|
get_property CLK_DOMAIN [get_pins design_1_i/can_0/can_clk]
|
|||
|
|
get_property CLK_DOMAIN [get_pins design_1_i/smartconnect_0/aclk]
|
|||
|
|
get_property CLK_DOMAIN [get_pins design_1_i/can_1/s_axi_aclk]
|
|||
|
|
get_property PERIOD [get_clocks -of_objects [get_pins design_1_i/can_0/s_axi_aclk]]
|
|||
|
|
WARNING: [Vivado 12-1008] No clocks found for command 'get_clocks -of_objects [get_pins design_1_i/can_0/s_axi_aclk]'.
|
|||
|
|
Resolution: Verify the create_clock command was called to create the clock object before it is referenced.
|
|||
|
|
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks.
|
|||
|
|
ERROR: [Common 17-55] 'get_property' expects at least one object.
|
|||
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|||
|
|
write_bd_layout -format pdf -orientation portrait -force C:/Users/zhaoms/Desktop/design_1.pdf
|
|||
|
|
C:/Users/zhaoms/Desktop/design_1.pdf
|
|||
|
|
set_property ALLOW_COMBINING true [get_pins design_1_smartconnect_0/aclk]
|
|||
|
|
WARNING: [Vivado 12-508] No pins matched 'design_1_smartconnect_0/aclk'.
|
|||
|
|
ERROR: [Common 17-55] 'set_property' expects at least one object.
|
|||
|
|
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
|
|||
|
|
set sc_inst [get_bd_cells smartconnect_0]
|
|||
|
|
/smartconnect_0
|
|||
|
|
list_property $sc_inst
|
|||
|
|
ALLOWED_SIM_MODELS CLASS COMBINED_SIM_MODEL CONFIG.ADVANCED_PROPERTIES CONFIG.Component_Name CONFIG.HAS_ARESETN CONFIG.NUM_CLKS CONFIG.NUM_MI CONFIG.NUM_SI CUSTOMIZATION_CRC LOCATION NAME PATH SCREENSIZE SDX_KERNEL SELECTED_SIM_MODEL TYPE VLNV
|
|||
|
|
get_property -all CONFIG.* $sc_inst | grep -i clock
|
|||
|
|
ERROR: [Common 17-170] Unknown option '-all', please type 'get_property -help' for usage info.
|
|||
|
|
# 1. <20>鿴<EFBFBD><E9BFB4>ǰʱ<C7B0><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
|
get_property CONFIG.NUM_CLKS [get_bd_cells smartconnect_0]
|
|||
|
|
1
|
|||
|
|
# 2. <20><EFBFBD>Ϊ 4 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD>ӣ<EFBFBD><D3A3><EFBFBD>Ӧ S00<30><30>S01<30><31>M00<30><30>M01<30><31>
|
|||
|
|
set_property CONFIG.NUM_CLKS 4 [get_bd_cells smartconnect_0]
|
|||
|
|
4
|
|||
|
|
# 3. ˢ<><CBA2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
|
regenerate_bd_layout
|
|||
|
|
# 4. <20>鿴<EFBFBD><E9BFB4><EFBFBD><EFBFBD><EFBFBD>ɵ<EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
|
get_pins -of_objects [get_bd_cells smartconnect_0] -filter {DIRECTION == IN && NAME =~ *aclk*}
|
|||
|
|
ERROR: [Common 17-679] Invalid object type, 'bd_cell', used with '-of_objects' switch. Supported types are: 'cell, clock, timing path, constant path, net, drc violation'.
|
|||
|
|
WARNING: [Vivado 12-508] No pins matched 'get_pins -of_objects /smartconnect_0 -filter {DIRECTION == IN && NAME =~ *aclk*}'.
|
|||
|
|
ERROR: [Common 17-39] 'get_pins' failed due to earlier errors.
|
|||
|
|
delete_bd_objs [get_bd_nets clk_in1_0_1] [get_bd_cells ibufg_user_0]
|
|||
|
|
undo
|
|||
|
|
INFO: [Common 17-17] undo 'delete_bd_objs [get_bd_nets clk_in1_0_1] [get_bd_cells ibufg_user_0]'
|
|||
|
|
undo
|
|||
|
|
INFO: [Common 17-17] undo 'regenerate_bd_layout'
|
|||
|
|
undo
|
|||
|
|
INFO: [Common 17-17] undo 'set_property CONFIG.NUM_CLKS 4 [get_bd_cells smartconnect_0]'
|
|||
|
|
delete_bd_objs [get_bd_nets clk_in1_0_1] [get_bd_cells ibufg_user_0]
|
|||
|
|
connect_bd_net [get_bd_ports clk_in1_0] [get_bd_pins clk_wiz_0/clk_in1]
|
|||
|
|
save_bd_design
|
|||
|
|
Wrote : <C:\proj\pro_finish\can_parse_ctrl\can_parse_ctrl.srcs\sources_1\bd\design_1\design_1.bd>
|
|||
|
|
Wrote : <C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
|
|||
|
|
regenerate_bd_layout
|
|||
|
|
regenerate_bd_layout
|
|||
|
|
validate_bd_design
|
|||
|
|
CRITICAL WARNING: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_0: The device(s) attached to /S00_AXI do not share a common clock frequency with this smartconnect instance. Modify the clock frequency values of the attached device(s) or re-customize this AXI SmartConnect instance to add a new clock pin and connect it to the same clock source of the IP attached to /S00_AXI to prevent further clock DRC violations.
|
|||
|
|
CRITICAL WARNING: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_0: The device(s) attached to /S01_AXI do not share a common clock frequency with this smartconnect instance. Modify the clock frequency values of the attached device(s) or re-customize this AXI SmartConnect instance to add a new clock pin and connect it to the same clock source of the IP attached to /S01_AXI to prevent further clock DRC violations.
|
|||
|
|
INFO: [BD 5-943] Reserving offset range <0x44A0_0000 [ 64K ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|||
|
|
INFO: [BD 5-943] Reserving offset range <0x44A1_0000 [ 64K ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|||
|
|
INFO: [BD 5-943] Reserving offset range <0x44A0_0000 [ 64K ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|||
|
|
INFO: [BD 5-943] Reserving offset range <0x44A1_0000 [ 64K ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|||
|
|
INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_0: SmartConnect design_1_smartconnect_0_0 is in Low-Area Mode.
|
|||
|
|
INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_0 clk_wiz propagate
|
|||
|
|
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
|
|||
|
|
Please check your design and connect them as needed:
|
|||
|
|
/can_rx_parse_axi_0/tlm_record_task_id
|
|||
|
|
/can_rx_parse_axi_0/tlm_downlink_task_id
|
|||
|
|
/can_rx_parse_axi_0/tlm_disk_status
|
|||
|
|
/can_rx_parse_axi_0/tlm_cam_dt_status
|
|||
|
|
/can_rx_parse_axi_0/tlm_lvds
|
|||
|
|
/can_rx_parse_axi_0/tlm_reconfig
|
|||
|
|
/can_rx_parse_axi_0/tlm_fpga_temp
|
|||
|
|
/can_rx_parse_axi_0/tlm_compress_flash
|
|||
|
|
|
|||
|
|
undo
|
|||
|
|
INFO: [Common 17-17] undo 'regenerate_bd_layout'
|
|||
|
|
undo
|
|||
|
|
INFO: [Common 17-17] undo 'regenerate_bd_layout'
|
|||
|
|
undo
|
|||
|
|
INFO: [Common 17-17] undo 'connect_bd_net [get_bd_ports clk_in1_0] [get_bd_pins clk_wiz_0/clk_in1]'
|
|||
|
|
undo
|
|||
|
|
INFO: [Common 17-17] undo 'delete_bd_objs [get_bd_nets clk_in1_0_1] [get_bd_cells ibufg_user_0]'
|
|||
|
|
startgroup
|
|||
|
|
create_bd_cell -type ip -vlnv xilinx.com:user:ibufg_user:1.0 ibufg_user_1
|
|||
|
|
endgroup
|
|||
|
|
delete_bd_objs [get_bd_cells ibufg_user_1]
|
|||
|
|
regenerate_bd_layout
|
|||
|
|
set_property SOURCE_SET sources_1 [get_filesets sim_1]
|
|||
|
|
add_files -fileset sim_1 -norecurse C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/tb_design_1_wrapper.v
|
|||
|
|
update_compile_order -fileset sim_1
|
|||
|
|
update_compile_order -fileset sim_1
|
|||
|
|
WARNING: [IP_Flow 19-4318] IP-XACT file does not exist: c:/proj/FPGA_DESIGN_IP/ibufg/component.xml. It will be created.
|
|||
|
|
WARNING: [IP_Flow 19-4318] IP-XACT file does not exist: c:/proj/FPGA_DESIGN_IP/ibufg/component.xml. It will be created.
|
|||
|
|
WARNING: [IP_Flow 19-4318] IP-XACT file does not exist: c:/proj/FPGA_DESIGN_IP/ibufg/component.xml. It will be created.
|
|||
|
|
WARNING: [IP_Flow 19-395] Problem validating against XML schema: : Unexpected end of message
|
|||
|
|
open_bd_design {C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd}
|
|||
|
|
update_ip_catalog -rebuild -scan_changes
|
|||
|
|
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
|||
|
|
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/proj/FPGA_DESIGN_IP'.
|
|||
|
|
report_ip_status -name ip_status
|
|||
|
|
upgrade_ip [get_ips {design_1_can_init_0_0 design_1_ibufg_user_0_0}] -log ip_upgrade.log
|
|||
|
|
Upgrading 'C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd'
|
|||
|
|
INFO: [IP_Flow 19-3420] Updated design_1_can_init_0_0 to use current project options
|
|||
|
|
INFO: [IP_Flow 19-3420] Updated design_1_ibufg_user_0_0 to use current project options
|
|||
|
|
WARNING: [BD 41-2671] The dangling interface net <m00_aw_node_M_AXIS_ARB> will not be written out to the BD file.
|
|||
|
|
WARNING: [BD 41-2671] The dangling interface net <m01_aw_node_M_AXIS_ARB> will not be written out to the BD file.
|
|||
|
|
Wrote : <C:\proj\pro_finish\can_parse_ctrl\can_parse_ctrl.srcs\sources_1\bd\design_1\design_1.bd>
|
|||
|
|
Wrote : <C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
|
|||
|
|
INFO: [Coretcl 2-1525] Wrote upgrade log to 'C:/proj/pro_finish/can_parse_ctrl/ip_upgrade.log'.
|
|||
|
|
export_ip_user_files -of_objects [get_ips {design_1_can_init_0_0 design_1_ibufg_user_0_0}] -no_script -sync -force -quiet
|
|||
|
|
generate_target all [get_files C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd]
|
|||
|
|
CRITICAL WARNING: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_0: The device(s) attached to /S00_AXI do not share a common clock domain with this smartconnect instance. Modify the clock domain values of the attached device(s) or re-customize this AXI SmartConnect instance to add a new clock pin and connect it to the same clock source of the IP attached to /S00_AXI to prevent further clock DRC violations.
|
|||
|
|
CRITICAL WARNING: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_0: The device(s) attached to /S00_AXI do not share a common clock frequency with this smartconnect instance. Modify the clock frequency values of the attached device(s) or re-customize this AXI SmartConnect instance to add a new clock pin and connect it to the same clock source of the IP attached to /S00_AXI to prevent further clock DRC violations.
|
|||
|
|
CRITICAL WARNING: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_0: The device(s) attached to /S01_AXI do not share a common clock frequency with this smartconnect instance. Modify the clock frequency values of the attached device(s) or re-customize this AXI SmartConnect instance to add a new clock pin and connect it to the same clock source of the IP attached to /S01_AXI to prevent further clock DRC violations.
|
|||
|
|
INFO: [BD 5-943] Reserving offset range <0x44A0_0000 [ 64K ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|||
|
|
INFO: [BD 5-943] Reserving offset range <0x44A1_0000 [ 64K ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|||
|
|
INFO: [BD 5-943] Reserving offset range <0x44A0_0000 [ 64K ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|||
|
|
INFO: [BD 5-943] Reserving offset range <0x44A1_0000 [ 64K ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|||
|
|
INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_0: SmartConnect design_1_smartconnect_0_0 is in Low-Area Mode.
|
|||
|
|
INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_0 clk_wiz propagate
|
|||
|
|
ERROR: [BD 41-237] Bus Interface property FREQ_HZ does not match between /smartconnect_0/S00_AXI(50000000) and /can_init_0/m_axi(100000000)
|
|||
|
|
ERROR: [BD 41-1031] Hdl Generation failed for the IP Integrator design C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd
|
|||
|
|
generate_target: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 3952.781 ; gain = 0.000
|
|||
|
|
ERROR: [Common 17-39] 'generate_target' failed due to earlier errors.
|
|||
|
|
report_ip_status -name ip_status
|
|||
|
|
regenerate_bd_layout
|
|||
|
|
validate_bd_design
|
|||
|
|
CRITICAL WARNING: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_0: The device(s) attached to /S00_AXI do not share a common clock domain with this smartconnect instance. Modify the clock domain values of the attached device(s) or re-customize this AXI SmartConnect instance to add a new clock pin and connect it to the same clock source of the IP attached to /S00_AXI to prevent further clock DRC violations.
|
|||
|
|
CRITICAL WARNING: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_0: The device(s) attached to /S00_AXI do not share a common clock frequency with this smartconnect instance. Modify the clock frequency values of the attached device(s) or re-customize this AXI SmartConnect instance to add a new clock pin and connect it to the same clock source of the IP attached to /S00_AXI to prevent further clock DRC violations.
|
|||
|
|
CRITICAL WARNING: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_0: The device(s) attached to /S01_AXI do not share a common clock frequency with this smartconnect instance. Modify the clock frequency values of the attached device(s) or re-customize this AXI SmartConnect instance to add a new clock pin and connect it to the same clock source of the IP attached to /S01_AXI to prevent further clock DRC violations.
|
|||
|
|
INFO: [BD 5-943] Reserving offset range <0x44A0_0000 [ 64K ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|||
|
|
INFO: [BD 5-943] Reserving offset range <0x44A1_0000 [ 64K ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|||
|
|
INFO: [BD 5-943] Reserving offset range <0x44A0_0000 [ 64K ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|||
|
|
INFO: [BD 5-943] Reserving offset range <0x44A1_0000 [ 64K ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|||
|
|
INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_0: SmartConnect design_1_smartconnect_0_0 is in Low-Area Mode.
|
|||
|
|
INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_0 clk_wiz propagate
|
|||
|
|
ERROR: [BD 41-237] Bus Interface property FREQ_HZ does not match between /smartconnect_0/S00_AXI(50000000) and /can_init_0/m_axi(100000000)
|
|||
|
|
ERROR: [Common 17-39] 'validate_bd_design' failed due to earlier errors.
|
|||
|
|
report_ip_status -name ip_status
|
|||
|
|
update_ip_catalog -rebuild
|
|||
|
|
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
|||
|
|
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/proj/FPGA_DESIGN_IP'.
|
|||
|
|
update_ip_catalog -rebuild
|
|||
|
|
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
|||
|
|
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/proj/FPGA_DESIGN_IP'.
|
|||
|
|
report_ip_status -name ip_status
|
|||
|
|
upgrade_ip -vlnv xilinx.com:user:can_init:1.0 [get_ips design_1_can_init_0_0] -log ip_upgrade.log
|
|||
|
|
Upgrading 'C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd'
|
|||
|
|
INFO: [IP_Flow 19-3420] Updated design_1_can_init_0_0 to use current project options
|
|||
|
|
WARNING: [BD 41-2671] The dangling interface net <m00_aw_node_M_AXIS_ARB> will not be written out to the BD file.
|
|||
|
|
WARNING: [BD 41-2671] The dangling interface net <m01_aw_node_M_AXIS_ARB> will not be written out to the BD file.
|
|||
|
|
Wrote : <C:\proj\pro_finish\can_parse_ctrl\can_parse_ctrl.srcs\sources_1\bd\design_1\design_1.bd>
|
|||
|
|
Wrote : <C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
|
|||
|
|
INFO: [Coretcl 2-1525] Wrote upgrade log to 'C:/proj/pro_finish/can_parse_ctrl/ip_upgrade.log'.
|
|||
|
|
export_ip_user_files -of_objects [get_ips design_1_can_init_0_0] -no_script -sync -force -quiet
|
|||
|
|
generate_target all [get_files C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd]
|
|||
|
|
CRITICAL WARNING: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_0: The device(s) attached to /S00_AXI do not share a common clock domain with this smartconnect instance. Modify the clock domain values of the attached device(s) or re-customize this AXI SmartConnect instance to add a new clock pin and connect it to the same clock source of the IP attached to /S00_AXI to prevent further clock DRC violations.
|
|||
|
|
CRITICAL WARNING: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_0: The device(s) attached to /S01_AXI do not share a common clock frequency with this smartconnect instance. Modify the clock frequency values of the attached device(s) or re-customize this AXI SmartConnect instance to add a new clock pin and connect it to the same clock source of the IP attached to /S01_AXI to prevent further clock DRC violations.
|
|||
|
|
INFO: [BD 5-943] Reserving offset range <0x44A0_0000 [ 64K ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|||
|
|
INFO: [BD 5-943] Reserving offset range <0x44A1_0000 [ 64K ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|||
|
|
INFO: [BD 5-943] Reserving offset range <0x44A0_0000 [ 64K ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|||
|
|
INFO: [BD 5-943] Reserving offset range <0x44A1_0000 [ 64K ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|||
|
|
INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_0: SmartConnect design_1_smartconnect_0_0 is in Low-Area Mode.
|
|||
|
|
INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_0 clk_wiz propagate
|
|||
|
|
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
|
|||
|
|
Please check your design and connect them as needed:
|
|||
|
|
/can_rx_parse_axi_0/tlm_record_task_id
|
|||
|
|
/can_rx_parse_axi_0/tlm_downlink_task_id
|
|||
|
|
/can_rx_parse_axi_0/tlm_disk_status
|
|||
|
|
/can_rx_parse_axi_0/tlm_cam_dt_status
|
|||
|
|
/can_rx_parse_axi_0/tlm_lvds
|
|||
|
|
/can_rx_parse_axi_0/tlm_reconfig
|
|||
|
|
/can_rx_parse_axi_0/tlm_fpga_temp
|
|||
|
|
/can_rx_parse_axi_0/tlm_compress_flash
|
|||
|
|
|
|||
|
|
WARNING: [BD 41-2671] The dangling interface net <m00_aw_node_M_AXIS_ARB> will not be written out to the BD file.
|
|||
|
|
WARNING: [BD 41-2671] The dangling interface net <m01_aw_node_M_AXIS_ARB> will not be written out to the BD file.
|
|||
|
|
Wrote : <C:\proj\pro_finish\can_parse_ctrl\can_parse_ctrl.srcs\sources_1\bd\design_1\design_1.bd>
|
|||
|
|
Verilog Output written to : c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/synth/design_1.v
|
|||
|
|
Verilog Output written to : c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/sim/design_1.v
|
|||
|
|
Verilog Output written to : c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block can_init_0 .
|
|||
|
|
Exporting to file c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/hw_handoff/design_1_smartconnect_0_0.hwh
|
|||
|
|
Generated Hardware Definition File c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/synth/design_1_smartconnect_0_0.hwdef
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block smartconnect_0 .
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block ibufg_user_0 .
|
|||
|
|
Exporting to file c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh
|
|||
|
|
Generated Hardware Definition File c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/synth/design_1.hwdef
|
|||
|
|
generate_target: Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 3952.781 ; gain = 0.000
|
|||
|
|
catch { config_ip_cache -export [get_ips -all design_1_can_init_0_0] }
|
|||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_can_init_0_0
|
|||
|
|
catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_0] }
|
|||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_smartconnect_0_0
|
|||
|
|
catch { config_ip_cache -export [get_ips -all design_1_ibufg_user_0_0] }
|
|||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ibufg_user_0_0
|
|||
|
|
export_ip_user_files -of_objects [get_files C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
|||
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd]
|
|||
|
|
launch_runs design_1_can_init_0_0_synth_1 design_1_ibufg_user_0_0_synth_1 design_1_smartconnect_0_0_synth_1 -jobs 24
|
|||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_can_init_0_0
|
|||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ibufg_user_0_0
|
|||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_smartconnect_0_0
|
|||
|
|
[Wed May 27 13:03:22 2026] Launched design_1_can_init_0_0_synth_1, design_1_ibufg_user_0_0_synth_1, design_1_smartconnect_0_0_synth_1...
|
|||
|
|
Run output will be captured here:
|
|||
|
|
design_1_can_init_0_0_synth_1: C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.runs/design_1_can_init_0_0_synth_1/runme.log
|
|||
|
|
design_1_ibufg_user_0_0_synth_1: C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.runs/design_1_ibufg_user_0_0_synth_1/runme.log
|
|||
|
|
design_1_smartconnect_0_0_synth_1: C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.runs/design_1_smartconnect_0_0_synth_1/runme.log
|
|||
|
|
export_simulation -of_objects [get_files C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files -ipstatic_source_dir C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/modelsim} {questa=C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/questa} {riviera=C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/riviera} {activehdl=C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
|||
|
|
report_ip_status -name ip_status
|
|||
|
|
regenerate_bd_layout
|
|||
|
|
regenerate_bd_layout
|
|||
|
|
startgroup
|
|||
|
|
set_property CONFIG.MODE_MSR {0x00000002} [get_bd_cells can_init_0]
|
|||
|
|
endgroup
|
|||
|
|
save_bd_design
|
|||
|
|
Wrote : <C:\proj\pro_finish\can_parse_ctrl\can_parse_ctrl.srcs\sources_1\bd\design_1\design_1.bd>
|
|||
|
|
regenerate_bd_layout
|
|||
|
|
generate_target Simulation [get_files C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd]
|
|||
|
|
CRITICAL WARNING: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_0: The device(s) attached to /S00_AXI do not share a common clock domain with this smartconnect instance. Modify the clock domain values of the attached device(s) or re-customize this AXI SmartConnect instance to add a new clock pin and connect it to the same clock source of the IP attached to /S00_AXI to prevent further clock DRC violations.
|
|||
|
|
CRITICAL WARNING: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_0: The device(s) attached to /S01_AXI do not share a common clock frequency with this smartconnect instance. Modify the clock frequency values of the attached device(s) or re-customize this AXI SmartConnect instance to add a new clock pin and connect it to the same clock source of the IP attached to /S01_AXI to prevent further clock DRC violations.
|
|||
|
|
INFO: [BD 5-943] Reserving offset range <0x44A0_0000 [ 64K ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|||
|
|
INFO: [BD 5-943] Reserving offset range <0x44A1_0000 [ 64K ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|||
|
|
INFO: [BD 5-943] Reserving offset range <0x44A0_0000 [ 64K ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|||
|
|
INFO: [BD 5-943] Reserving offset range <0x44A1_0000 [ 64K ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|||
|
|
INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_0: SmartConnect design_1_smartconnect_0_0 is in Low-Area Mode.
|
|||
|
|
INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_0 clk_wiz propagate
|
|||
|
|
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
|
|||
|
|
Please check your design and connect them as needed:
|
|||
|
|
/can_rx_parse_axi_0/tlm_record_task_id
|
|||
|
|
/can_rx_parse_axi_0/tlm_downlink_task_id
|
|||
|
|
/can_rx_parse_axi_0/tlm_disk_status
|
|||
|
|
/can_rx_parse_axi_0/tlm_cam_dt_status
|
|||
|
|
/can_rx_parse_axi_0/tlm_lvds
|
|||
|
|
/can_rx_parse_axi_0/tlm_reconfig
|
|||
|
|
/can_rx_parse_axi_0/tlm_fpga_temp
|
|||
|
|
/can_rx_parse_axi_0/tlm_compress_flash
|
|||
|
|
|
|||
|
|
WARNING: [BD 41-2671] The dangling interface net <m00_aw_node_M_AXIS_ARB> will not be written out to the BD file.
|
|||
|
|
WARNING: [BD 41-2671] The dangling interface net <m01_aw_node_M_AXIS_ARB> will not be written out to the BD file.
|
|||
|
|
Wrote : <C:\proj\pro_finish\can_parse_ctrl\can_parse_ctrl.srcs\sources_1\bd\design_1\design_1.bd>
|
|||
|
|
Wrote : <C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
|
|||
|
|
Verilog Output written to : c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/synth/design_1.v
|
|||
|
|
Verilog Output written to : c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/sim/design_1.v
|
|||
|
|
Verilog Output written to : c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block can_init_0 .
|
|||
|
|
Exporting to file c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/hw_handoff/design_1_smartconnect_0_0.hwh
|
|||
|
|
Generated Hardware Definition File c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/synth/design_1_smartconnect_0_0.hwdef
|
|||
|
|
Exporting to file c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh
|
|||
|
|
Generated Hardware Definition File c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/synth/design_1.hwdef
|
|||
|
|
generate_target: Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 3952.781 ; gain = 0.000
|
|||
|
|
export_ip_user_files -of_objects [get_files C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
|||
|
|
export_simulation -of_objects [get_files C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files -ipstatic_source_dir C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/modelsim} {questa=C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/questa} {riviera=C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/riviera} {activehdl=C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
|||
|
|
launch_simulation
|
|||
|
|
Command: launch_simulation
|
|||
|
|
INFO: [Vivado 12-12493] Simulation top is 'tb_design_1_wrapper'
|
|||
|
|
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
|
|||
|
|
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
|
|||
|
|
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.sim/sim_1/behav/xsim'
|
|||
|
|
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
|
|||
|
|
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
|
|||
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|||
|
|
INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2023.2/tps/boost_1_72_0'
|
|||
|
|
INFO: [USF-XSim-7] Finding pre-compiled libraries...
|
|||
|
|
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2023.2/data/xsim/xsim.ini' copied to run dir:'C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.sim/sim_1/behav/xsim'
|
|||
|
|
INFO: [SIM-utils-54] Inspecting design source files for 'tb_design_1_wrapper' in fileset 'sim_1'...
|
|||
|
|
INFO: [SIM-utils-43] Exported 'C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.sim/sim_1/behav/xsim/sc_xtlm_design_1_smartconnect_0_0.mem'
|
|||
|
|
INFO: [USF-XSim-97] Finding global include files...
|
|||
|
|
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
|
|||
|
|
INFO: [USF-XSim-2] XSim::Compile design
|
|||
|
|
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.sim/sim_1/behav/xsim'
|
|||
|
|
"xvlog --incr --relax -L uvm -L axi_vip_v1_1_15 -L smartconnect_v1_0 -L xilinx_vip -prj tb_design_1_wrapper_vlog.prj"
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/46d7/src/wall_timer.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module wall_timer
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/46d7/src/can_init.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module can_init
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_can_init_0_0/sim/design_1_can_init_0_0.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module design_1_can_init_0_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/d5b1/src/can_rx_parse_axi.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module can_rx_parse_axi
|
|||
|
|
WARNING: [VRFC 10-3380] identifier 'tx_base' is used before its declaration [C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/d5b1/src/can_rx_parse_axi.v:174]
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_can_rx_parse_axi_0_0/sim/design_1_can_rx_parse_axi_0_0.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module design_1_can_rx_parse_axi_0_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_uart_parse_real_0_0/src/ila_0/sim/ila_0.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module ila_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_uart_parse_real_0_0/src/blk_mem_gen_0/sim/blk_mem_gen_0.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module blk_mem_gen_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/5b8a/src/uart.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module uart
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/5b8a/src/uart_data_parse.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module uart_data_parse
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/5b8a/src/uart_parse.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module uart_parse
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/5b8a/src/uart_rx.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module uart_rx
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/5b8a/src/uart_tx.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module uart_tx
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/5b8a/src/uart_parse_real.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module uart_parse_real
|
|||
|
|
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'async_serial' is not allowed [C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/5b8a/src/uart_parse_real.sv:55]
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_uart_parse_real_0_0/sim/design_1_uart_parse_real_0_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module design_1_uart_parse_real_0_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_clk_wiz.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module design_1_clk_wiz_0_0_clk_wiz
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module design_1_clk_wiz_0_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_util_vector_logic_0_0/sim/design_1_util_vector_logic_0_0.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module design_1_util_vector_logic_0_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_util_vector_logic_0_1/sim/design_1_util_vector_logic_0_1.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module design_1_util_vector_logic_0_1
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/sim/bd_48ac.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac
|
|||
|
|
INFO: [VRFC 10-311] analyzing module clk_map_imp_1NMB928
|
|||
|
|
INFO: [VRFC 10-311] analyzing module i_nodes_imp_6FNK9A
|
|||
|
|
INFO: [VRFC 10-311] analyzing module m00_exit_pipeline_imp_CVVFJV
|
|||
|
|
INFO: [VRFC 10-311] analyzing module m00_nodes_imp_Z1B1P3
|
|||
|
|
INFO: [VRFC 10-311] analyzing module m01_exit_pipeline_imp_FWTRCR
|
|||
|
|
INFO: [VRFC 10-311] analyzing module m01_nodes_imp_1R2BU3L
|
|||
|
|
INFO: [VRFC 10-311] analyzing module s00_entry_pipeline_imp_1C3JDRS
|
|||
|
|
INFO: [VRFC 10-311] analyzing module s00_nodes_imp_1FAO4F6
|
|||
|
|
INFO: [VRFC 10-311] analyzing module s01_entry_pipeline_imp_F11SX8
|
|||
|
|
INFO: [VRFC 10-311] analyzing module s01_nodes_imp_AIXRF8
|
|||
|
|
INFO: [VRFC 10-311] analyzing module switchboards_imp_1MKJLH2
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_0/sim/bd_48ac_one_0.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_one_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_2/sim/bd_48ac_arinsw_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_arinsw_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_3/sim/bd_48ac_rinsw_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_rinsw_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_4/sim/bd_48ac_awinsw_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_awinsw_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_5/sim/bd_48ac_winsw_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_winsw_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_6/sim/bd_48ac_binsw_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_binsw_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_7/sim/bd_48ac_aroutsw_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_aroutsw_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_8/sim/bd_48ac_routsw_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_routsw_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_9/sim/bd_48ac_awoutsw_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_awoutsw_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_10/sim/bd_48ac_woutsw_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_woutsw_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_11/sim/bd_48ac_boutsw_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_boutsw_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_12/sim/bd_48ac_arni_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_arni_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_13/sim/bd_48ac_rni_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_rni_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_14/sim/bd_48ac_awni_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_awni_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_15/sim/bd_48ac_wni_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_wni_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_16/sim/bd_48ac_bni_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_bni_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_17/sim/bd_48ac_s00mmu_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_s00mmu_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_18/sim/bd_48ac_s00tr_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_s00tr_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_19/sim/bd_48ac_s00sic_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_s00sic_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_20/sim/bd_48ac_s00a2s_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_s00a2s_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_21/sim/bd_48ac_sawn_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_sawn_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_22/sim/bd_48ac_swn_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_swn_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_23/sim/bd_48ac_sbn_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_sbn_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_24/sim/bd_48ac_s01mmu_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_s01mmu_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_25/sim/bd_48ac_s01tr_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_s01tr_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_26/sim/bd_48ac_s01sic_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_s01sic_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_27/sim/bd_48ac_s01a2s_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_s01a2s_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_28/sim/bd_48ac_sarn_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_sarn_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_29/sim/bd_48ac_srn_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_srn_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_30/sim/bd_48ac_sawn_1.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_sawn_1
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_31/sim/bd_48ac_swn_1.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_swn_1
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_32/sim/bd_48ac_sbn_1.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_sbn_1
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_33/sim/bd_48ac_m00s2a_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_m00s2a_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_34/sim/bd_48ac_m00arn_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_m00arn_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_35/sim/bd_48ac_m00rn_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_m00rn_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_36/sim/bd_48ac_m00awn_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_m00awn_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_37/sim/bd_48ac_m00wn_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_m00wn_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_38/sim/bd_48ac_m00bn_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_m00bn_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_39/sim/bd_48ac_m00e_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_m00e_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_40/sim/bd_48ac_m01s2a_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_m01s2a_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_41/sim/bd_48ac_m01arn_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_m01arn_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_42/sim/bd_48ac_m01rn_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_m01rn_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_43/sim/bd_48ac_m01awn_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_m01awn_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_44/sim/bd_48ac_m01wn_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_m01wn_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_45/sim/bd_48ac_m01bn_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_m01bn_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_46/sim/bd_48ac_m01e_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module bd_48ac_m01e_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/sim/design_1_smartconnect_0_0.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module design_1_smartconnect_0_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/1583/src/ibufg_user.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module ibufg_user
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_ibufg_user_0_0/sim/design_1_ibufg_user_0_0.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module design_1_ibufg_user_0_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/sim/design_1.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module design_1
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module design_1_wrapper
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/tb_design_1_wrapper.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module tb_design_1_wrapper
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.sim/sim_1/behav/xsim/glbl.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module glbl
|
|||
|
|
"xvhdl --incr --relax -prj tb_design_1_wrapper_vhdl.prj"
|
|||
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_can_0_2/sim/design_1_can_0_2.vhd" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-3107] analyzing entity 'design_1_can_0_2'
|
|||
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_can_0_3/sim/design_1_can_0_3.vhd" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-3107] analyzing entity 'design_1_can_0_3'
|
|||
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/ip/ip_1/sim/bd_48ac_psr_aclk_0.vhd" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-3107] analyzing entity 'bd_48ac_psr_aclk_0'
|
|||
|
|
run_program: Time (s): cpu = 00:00:02 ; elapsed = 00:00:11 . Memory (MB): peak = 3952.781 ; gain = 0.000
|
|||
|
|
INFO: [USF-XSim-69] 'compile' step finished in '12' seconds
|
|||
|
|
INFO: [USF-XSim-3] XSim::Elaborate design
|
|||
|
|
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.sim/sim_1/behav/xsim'
|
|||
|
|
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L blk_mem_gen_v8_4_7 -L util_vector_logic_v2_0_3 -L lib_cdc_v1_0_2 -L lib_bmg_v1_0_16 -L can_v5_1_1 -L xlconstant_v1_1_8 -L proc_sys_reset_v5_0_14 -L smartconnect_v1_0 -L axi_infrastructure_v1_1_0 -L axi_register_slice_v2_1_29 -L axi_vip_v1_1_15 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_design_1_wrapper_behav xil_defaultlib.tb_design_1_wrapper xil_defaultlib.glbl -log elaborate.log"
|
|||
|
|
Vivado Simulator v2023.2
|
|||
|
|
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
|||
|
|
Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
|||
|
|
Running: C:/Xilinx/Vivado/2023.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L blk_mem_gen_v8_4_7 -L util_vector_logic_v2_0_3 -L lib_cdc_v1_0_2 -L lib_bmg_v1_0_16 -L can_v5_1_1 -L xlconstant_v1_1_8 -L proc_sys_reset_v5_0_14 -L smartconnect_v1_0 -L axi_infrastructure_v1_1_0 -L axi_register_slice_v2_1_29 -L axi_vip_v1_1_15 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_design_1_wrapper_behav xil_defaultlib.tb_design_1_wrapper xil_defaultlib.glbl -log elaborate.log
|
|||
|
|
Using 2 slave threads.
|
|||
|
|
Starting static elaboration
|
|||
|
|
Pass Through NonSizing Optimizer
|
|||
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 16 for port 'cfg_div_i' [C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/5b8a/src/uart.sv:43]
|
|||
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 16 for port 'cfg_div_i' [C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/5b8a/src/uart.sv:63]
|
|||
|
|
WARNING: [VRFC 10-3091] actual bit length 166 differs from formal bit length 182 for port 'probe0' [C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/5b8a/src/uart_data_parse.sv:347]
|
|||
|
|
WARNING: [VRFC 10-5021] port 'ip2bus_intrevent' is not connected on this instance [C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/sim/design_1.v:111]
|
|||
|
|
WARNING: [VRFC 10-5021] port 'ip2bus_intrevent' is not connected on this instance [C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/sim/design_1.v:134]
|
|||
|
|
WARNING: [VRFC 10-5021] port 'mb_reset' is not connected on this instance [C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_0/bd_0/sim/bd_48ac.v:1431]
|
|||
|
|
Completed static elaboration
|
|||
|
|
Starting simulation data flow analysis
|
|||
|
|
WARNING: [XSIM 43-4099] "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/46d7/src/wall_timer.sv" Line 7. Module wall_timer(MODULE_FREQ_HZ=50000000,MS_WIDTH=10) doesn't have a timescale but at least one module in design has a timescale.
|
|||
|
|
WARNING: [XSIM 43-4099] "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/5b8a/src/uart.sv" Line 11. Module uart(CLOCK_FREQUENCY=50000000,BAUD_RATE=2000000) doesn't have a timescale but at least one module in design has a timescale.
|
|||
|
|
WARNING: [XSIM 43-4099] "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/46d7/src/wall_timer.sv" Line 7. Module wall_timer(MODULE_FREQ_HZ=50000000,MS_WIDTH=10) doesn't have a timescale but at least one module in design has a timescale.
|
|||
|
|
WARNING: [XSIM 43-4099] "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/5b8a/src/uart.sv" Line 11. Module uart(CLOCK_FREQUENCY=50000000,BAUD_RATE=2000000) doesn't have a timescale but at least one module in design has a timescale.
|
|||
|
|
Completed simulation data flow analysis
|
|||
|
|
Time Resolution for simulation is 1ps
|
|||
|
|
Compiling package std.standard
|
|||
|
|
Compiling package std.textio
|
|||
|
|
Compiling package ieee.std_logic_1164
|
|||
|
|
Compiling package ieee.numeric_std
|
|||
|
|
Compiling package ieee.std_logic_arith
|
|||
|
|
Compiling package ieee.std_logic_unsigned
|
|||
|
|
Compiling package synopsys.attributes
|
|||
|
|
Compiling package ieee.std_logic_misc
|
|||
|
|
Compiling package can_v5_1_1.proc_common_pkg
|
|||
|
|
Compiling package can_v5_1_1.ipif_pkg
|
|||
|
|
Compiling package can_v5_1_1.can_ip_pkg
|
|||
|
|
Compiling package xpm.vcomponents
|
|||
|
|
Compiling package unisim.vcomponents
|
|||
|
|
Compiling package ieee.vital_timing
|
|||
|
|
Compiling package ieee.vital_primitives
|
|||
|
|
Compiling package unisim.vpkg
|
|||
|
|
Compiling package xpm.$unit_xpm_cdc_sv_220102727
|
|||
|
|
Compiling package xpm.axi_xil_sb_pkg_xpm_nsu
|
|||
|
|
Compiling package xpm.axi_data_integrity_checker_xpm_n...
|
|||
|
|
Compiling package xpm.xpm_axi_data_integrity_checker_n...
|
|||
|
|
Compiling package xpm.xpm_axi_xil_sb_pkg_nmu
|
|||
|
|
Compiling package smartconnect_v1_0.sc_util_v1_0_4_pkg
|
|||
|
|
Compiling architecture imp of entity can_v5_1_1.address_decoder [\address_decoder(c_bus_awidth=8,...]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.slave_attachment [\slave_attachment(c_ard_addr_ran...]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.axi_lite_ipif [\axi_lite_ipif(c_s_axi_addr_widt...]
|
|||
|
|
Compiling architecture implementation of entity can_v5_1_1.can_sync_block [\can_sync_block(c_reset_state=1,...]
|
|||
|
|
Compiling architecture fdre_v of entity unisim.FDRE [fdre_default]
|
|||
|
|
Compiling architecture fdr_v of entity unisim.FDR [fdr_default]
|
|||
|
|
Compiling architecture implementation of entity lib_cdc_v1_0_2.cdc_sync [\cdc_sync(c_reset_state=1,c_flop...]
|
|||
|
|
Compiling architecture implementation of entity lib_cdc_v1_0_2.cdc_sync [\cdc_sync(c_reset_state=1,c_sing...]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.CAN_OL_SYNCH [can_ol_synch_default]
|
|||
|
|
Compiling module xpm.xpm_memory_base(MEMORY_SIZE=1638...
|
|||
|
|
Compiling module xpm.xpm_memory_tdpram(MEMORY_SIZE=16...
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.can_tl_arbchk [can_tl_arbchk_default]
|
|||
|
|
Compiling architecture fdce_v of entity unisim.FDCE [fdce_default]
|
|||
|
|
Compiling architecture fdc_v of entity unisim.FDC [fdc_default]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.can_ol_fifopriority [can_ol_fifopriority_default]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.CAN_TXFIFO_CNTL_GEN [\CAN_TXFIFO_CNTL_GEN(c_can_tx_aw...]
|
|||
|
|
Compiling module xpm.xpm_cdc_single(DEST_SYNC_FF=2,IN...
|
|||
|
|
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
|
|||
|
|
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=16...
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.CAN_RXFIFO_CNTL_GEN [\CAN_RXFIFO_CNTL_GEN(c_can_rx_aw...]
|
|||
|
|
Compiling module xpm.xpm_cdc_array_single(DEST_SYNC_F...
|
|||
|
|
Compiling module xpm.xpm_cdc_async_rst(DEST_SYNC_FF=4...
|
|||
|
|
Compiling architecture implementation of entity can_v5_1_1.can_sync_block [\can_sync_block(c_reset_state=1)...]
|
|||
|
|
Compiling architecture implementation of entity lib_cdc_v1_0_2.cdc_sync [\cdc_sync(c_reset_state=1)\]
|
|||
|
|
Compiling architecture implementation of entity lib_cdc_v1_0_2.cdc_sync [\cdc_sync(c_reset_state=1,c_sing...]
|
|||
|
|
Compiling architecture implementation of entity lib_cdc_v1_0_2.cdc_sync [\cdc_sync(c_reset_state=1,c_vect...]
|
|||
|
|
Compiling architecture implementation of entity lib_cdc_v1_0_2.cdc_sync [\cdc_sync(c_reset_state=1,c_flop...]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.CAN_IC_MAIN [can_ic_main_default]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.CAN_OL_TOP [\CAN_OL_TOP(c_can_rx_awidth=4,c_...]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.CAN_TL_ACF [can_tl_acf_default]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.CAN_TL_CLKDIV [can_tl_clkdiv_default]
|
|||
|
|
Compiling architecture implementation of entity lib_cdc_v1_0_2.cdc_sync [\cdc_sync(c_reset_state=1,c_sing...]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.CAN_TL_SYNCH [\CAN_TL_SYNCH(c_can_acf_defined=...]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.CAN_TL_BTL [can_tl_btl_default]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.CAN_TL_OM [can_tl_om_default]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.can_tl_arbit [can_tl_arbit_default]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.CAN_TL_BSP [\CAN_TL_BSP(c_can_acf_defined='1...]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.CAN_TL_TOP [\CAN_TL_TOP(c_can_acf_defined='1...]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.cantop [\cantop(c_can_rx_dpth=16,c_can_t...]
|
|||
|
|
Compiling architecture imp of entity can_v5_1_1.can_top [\can_top(c_can_rx_dpth=16,c_can_...]
|
|||
|
|
Compiling architecture amd of entity can_v5_1_1.can_v5_1_1 [\can_v5_1_1(c_can_rx_dpth=16,c_c...]
|
|||
|
|
Compiling architecture design_1_can_0_2_arch of entity xil_defaultlib.design_1_can_0_2 [design_1_can_0_2_default]
|
|||
|
|
Compiling architecture design_1_can_0_3_arch of entity xil_defaultlib.design_1_can_0_3 [design_1_can_0_3_default]
|
|||
|
|
Compiling module xil_defaultlib.wall_timer(MODULE_FREQ_HZ=500000...
|
|||
|
|
Compiling module xil_defaultlib.can_init(MODE_MSR=32'b010,DELAY_...
|
|||
|
|
Compiling module xil_defaultlib.design_1_can_init_0_0
|
|||
|
|
Compiling module xil_defaultlib.can_rx_parse_axi
|
|||
|
|
Compiling module xil_defaultlib.design_1_can_rx_parse_axi_0_0
|
|||
|
|
Compiling module unisims_ver.IBUF
|
|||
|
|
Compiling module unisims_ver.MMCME2_ADV(CLKFBOUT_MULT_F=20.0,...
|
|||
|
|
Compiling module unisims_ver.BUFG
|
|||
|
|
Compiling module xil_defaultlib.design_1_clk_wiz_0_0_clk_wiz
|
|||
|
|
Compiling module xil_defaultlib.design_1_clk_wiz_0_0
|
|||
|
|
Compiling module unisims_ver.IBUFG
|
|||
|
|
Compiling module xil_defaultlib.ibufg_user
|
|||
|
|
Compiling module xil_defaultlib.design_1_ibufg_user_0_0
|
|||
|
|
Compiling module xlconstant_v1_1_8.xlconstant_v1_1_8_xlconstant(CON...
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_one_0
|
|||
|
|
Compiling architecture fdre_v of entity unisim.FDRE [\FDRE(init='1')\]
|
|||
|
|
Compiling architecture implementation of entity lib_cdc_v1_0_2.cdc_sync [\cdc_sync(c_vector_width=2,c_mtb...]
|
|||
|
|
Compiling architecture srl16e_v of entity unisim.SRL16E [\SRL16E(init="1111111111111111")...]
|
|||
|
|
Compiling architecture srl16_v of entity unisim.SRL16 [\SRL16(init="1111111111111111")(...]
|
|||
|
|
Compiling architecture imp of entity proc_sys_reset_v5_0_14.lpf [\lpf(c_ext_rst_width=4,c_aux_rst...]
|
|||
|
|
Compiling architecture imp of entity proc_sys_reset_v5_0_14.upcnt_n [\upcnt_n(c_size=6)\]
|
|||
|
|
Compiling architecture imp of entity proc_sys_reset_v5_0_14.sequence_psr [sequence_psr_default]
|
|||
|
|
Compiling architecture imp of entity proc_sys_reset_v5_0_14.proc_sys_reset [\proc_sys_reset(c_aux_rst_width=...]
|
|||
|
|
Compiling architecture bd_48ac_psr_aclk_0_arch of entity xil_defaultlib.bd_48ac_psr_aclk_0 [bd_48ac_psr_aclk_0_default]
|
|||
|
|
Compiling module xil_defaultlib.clk_map_imp_1NMB928
|
|||
|
|
Compiling module xpm.xpm_cdc_async_rst(DEST_SYNC_FF=3...
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_m00e_0
|
|||
|
|
Compiling module xil_defaultlib.m00_exit_pipeline_imp_CVVFJV
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_m00arn_0
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_m00awn_0
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_m00bn_0
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_m00rn_0
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_m00wn_0
|
|||
|
|
Compiling module xil_defaultlib.m00_nodes_imp_Z1B1P3
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_m00s2a_0
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_m01e_0
|
|||
|
|
Compiling module xil_defaultlib.m01_exit_pipeline_imp_FWTRCR
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_m01arn_0
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_m01awn_0
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_m01bn_0
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_m01rn_0
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_m01wn_0
|
|||
|
|
Compiling module xil_defaultlib.m01_nodes_imp_1R2BU3L
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_m01s2a_0
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_s00a2s_0
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_s00mmu_0
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_s00sic_0
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_s00tr_0
|
|||
|
|
Compiling module xil_defaultlib.s00_entry_pipeline_imp_1C3JDRS
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_sawn_0
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_sbn_0
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_swn_0
|
|||
|
|
Compiling module xil_defaultlib.s00_nodes_imp_1FAO4F6
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_s01a2s_0
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_s01mmu_0
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_s01sic_0
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_s01tr_0
|
|||
|
|
Compiling module xil_defaultlib.s01_entry_pipeline_imp_F11SX8
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_sarn_0
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_sawn_1
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_sbn_1
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_srn_0
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_swn_1
|
|||
|
|
Compiling module xil_defaultlib.s01_nodes_imp_AIXRF8
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_arinsw_0
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_aroutsw_0
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_awinsw_0
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_awoutsw_0
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_binsw_0
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_boutsw_0
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_arni_0
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_awni_0
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_bni_0
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_rni_0
|
|||
|
|
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
|
|||
|
|
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=4,...
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_wni_0
|
|||
|
|
Compiling module xil_defaultlib.i_nodes_imp_6FNK9A
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_rinsw_0
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_routsw_0
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_winsw_0
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac_woutsw_0
|
|||
|
|
Compiling module xil_defaultlib.switchboards_imp_1MKJLH2
|
|||
|
|
Compiling module xil_defaultlib.bd_48ac
|
|||
|
|
Compiling module xil_defaultlib.design_1_smartconnect_0_0
|
|||
|
|
Compiling module xil_defaultlib.uart_rx
|
|||
|
|
Compiling module xil_defaultlib.uart_tx
|
|||
|
|
Compiling module xil_defaultlib.uart(CLOCK_FREQUENCY=50000000,BA...
|
|||
|
|
Compiling module blk_mem_gen_v8_4_7.blk_mem_gen_v8_4_7_output_stage(...
|
|||
|
|
Compiling module blk_mem_gen_v8_4_7.blk_mem_gen_v8_4_7_output_stage(...
|
|||
|
|
Compiling module blk_mem_gen_v8_4_7.blk_mem_gen_v8_4_7_softecc_outpu...
|
|||
|
|
Compiling module blk_mem_gen_v8_4_7.blk_mem_gen_v8_4_7_mem_module(C_...
|
|||
|
|
Compiling module blk_mem_gen_v8_4_7.blk_mem_axi_regs_fwd_v8_4(C_DATA...
|
|||
|
|
Compiling module blk_mem_gen_v8_4_7.blk_mem_gen_v8_4_7(C_ELABORATION...
|
|||
|
|
Compiling module xil_defaultlib.blk_mem_gen_0
|
|||
|
|
Compiling module xil_defaultlib.ila_0
|
|||
|
|
Compiling module xil_defaultlib.uart_data_parse_default
|
|||
|
|
Compiling module xil_defaultlib.uart_parse(CLOCK_FREQUENCY=50000...
|
|||
|
|
Compiling module xil_defaultlib.uart_parse_real
|
|||
|
|
Compiling module xil_defaultlib.design_1_uart_parse_real_0_0
|
|||
|
|
Compiling module util_vector_logic_v2_0_3.util_vector_logic_v2_0_3_util_ve...
|
|||
|
|
Compiling module xil_defaultlib.design_1_util_vector_logic_0_0
|
|||
|
|
Compiling module util_vector_logic_v2_0_3.util_vector_logic_v2_0_3_util_ve...
|
|||
|
|
Compiling module xil_defaultlib.design_1_util_vector_logic_0_1
|
|||
|
|
Compiling module xil_defaultlib.design_1
|
|||
|
|
Compiling module xil_defaultlib.design_1_wrapper
|
|||
|
|
Compiling module xil_defaultlib.tb_design_1_wrapper
|
|||
|
|
Compiling module xil_defaultlib.glbl
|
|||
|
|
Built simulation snapshot tb_design_1_wrapper_behav
|
|||
|
|
run_program: Time (s): cpu = 00:00:01 ; elapsed = 00:00:23 . Memory (MB): peak = 3952.781 ; gain = 0.000
|
|||
|
|
INFO: [USF-XSim-69] 'elaborate' step finished in '22' seconds
|
|||
|
|
INFO: [USF-XSim-4] XSim::Simulate design
|
|||
|
|
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.sim/sim_1/behav/xsim'
|
|||
|
|
INFO: [USF-XSim-98] *** Running xsim
|
|||
|
|
with args "tb_design_1_wrapper_behav -key {Behavioral:sim_1:Functional:tb_design_1_wrapper} -tclbatch {tb_design_1_wrapper.tcl} -protoinst "protoinst_files/bd_48ac.protoinst" -protoinst "protoinst_files/design_1.protoinst" -log {simulate.log}"
|
|||
|
|
INFO: [USF-XSim-8] Loading simulator feature
|
|||
|
|
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/bd_48ac.protoinst
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m00_exit_pipeline/m00_exit/M_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m00_exit_pipeline/m00_exit/S_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m00_exit_pipeline/m_axi
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m00_exit_pipeline/s_axi
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m00_sc2axi/M_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m01_exit_pipeline/m01_exit/M_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m01_exit_pipeline/m01_exit/S_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m01_exit_pipeline/m_axi
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m01_exit_pipeline/s_axi
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m01_sc2axi/M_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_axi2sc/S_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/m_axi
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/s00_mmu/M_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/s00_mmu/S_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/s00_si_converter/M_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/s00_si_converter/S_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/s00_transaction_regulator/M_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/s00_transaction_regulator/S_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/s_axi
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_axi2sc/S_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/m_axi
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/s01_mmu/M_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/s01_mmu/S_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/s01_si_converter/M_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/s01_si_converter/S_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/s01_transaction_regulator/M_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/s01_transaction_regulator/S_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/s_axi
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//switchboards/i_nodes/i_aw_node/M_AXIS_ARB
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//switchboards/i_nodes/i_w_node/S_AXIS_ARB
|
|||
|
|
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_1.protoinst
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//can_0/CAN_S_AXI_LITE
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//can_1/CAN_S_AXI_LITE
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//can_init_0/m_axi
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//can_rx_parse_axi_0/m_axi
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//smartconnect_0/M00_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//smartconnect_0/M01_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//smartconnect_0/S00_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//smartconnect_0/S01_AXI
|
|||
|
|
Time resolution is 1 ps
|
|||
|
|
source tb_design_1_wrapper.tcl
|
|||
|
|
# set curr_wave [current_wave_config]
|
|||
|
|
# if { [string length $curr_wave] == 0 } {
|
|||
|
|
# if { [llength [get_objects]] > 0} {
|
|||
|
|
# add_wave /
|
|||
|
|
# set_property needs_save false [current_wave_config]
|
|||
|
|
# } else {
|
|||
|
|
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
|||
|
|
# }
|
|||
|
|
# }
|
|||
|
|
# run 1000ns
|
|||
|
|
Block Memory Generator module tb_design_1_wrapper.u_dut.design_1_i.uart_parse_real_0.inst.u_dut.u_uart_data_parse.your_instance_name.inst.\native_mem_module.blk_mem_gen_v8_4_7_inst is using a behavioral model for simulation which will not precisely model memory collision behavior.
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_0/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/woecctx/memtx/xpm_memory_base_inst/Initial302_3 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_0/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/memrx/xpm_memory_base_inst/Initial302_35 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_1/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/woecctx/memtx/xpm_memory_base_inst/Initial302_3 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_1/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/memrx/xpm_memory_base_inst/Initial302_35 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_design_1_wrapper_behav' loaded.
|
|||
|
|
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
|
|||
|
|
launch_simulation: Time (s): cpu = 00:00:07 ; elapsed = 00:00:39 . Memory (MB): peak = 3952.781 ; gain = 0.000
|
|||
|
|
current_wave_config {Untitled 1}
|
|||
|
|
Untitled 1
|
|||
|
|
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/can_init_0/inst}}
|
|||
|
|
restart
|
|||
|
|
INFO: [Wavedata 42-604] Simulation restarted
|
|||
|
|
run 50 ms
|
|||
|
|
Block Memory Generator module tb_design_1_wrapper.u_dut.design_1_i.uart_parse_real_0.inst.u_dut.u_uart_data_parse.your_instance_name.inst.\native_mem_module.blk_mem_gen_v8_4_7_inst is using a behavioral model for simulation which will not precisely model memory collision behavior.
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_0/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/woecctx/memtx/xpm_memory_base_inst/Initial302_3 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_0/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/memrx/xpm_memory_base_inst/Initial302_35 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_1/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/woecctx/memtx/xpm_memory_base_inst/Initial302_3 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_1/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/memrx/xpm_memory_base_inst/Initial302_35 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
run: Time (s): cpu = 00:00:20 ; elapsed = 00:01:24 . Memory (MB): peak = 3952.781 ; gain = 0.000
|
|||
|
|
current_wave_config {Untitled 1}
|
|||
|
|
Untitled 1
|
|||
|
|
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/can_rx_parse_axi_0}}
|
|||
|
|
restart
|
|||
|
|
INFO: [Wavedata 42-604] Simulation restarted
|
|||
|
|
run 50 ms
|
|||
|
|
Block Memory Generator module tb_design_1_wrapper.u_dut.design_1_i.uart_parse_real_0.inst.u_dut.u_uart_data_parse.your_instance_name.inst.\native_mem_module.blk_mem_gen_v8_4_7_inst is using a behavioral model for simulation which will not precisely model memory collision behavior.
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_0/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/woecctx/memtx/xpm_memory_base_inst/Initial302_3 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_0/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/memrx/xpm_memory_base_inst/Initial302_35 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_1/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/woecctx/memtx/xpm_memory_base_inst/Initial302_3 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_1/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/memrx/xpm_memory_base_inst/Initial302_35 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
run: Time (s): cpu = 00:00:09 ; elapsed = 00:00:41 . Memory (MB): peak = 3952.781 ; gain = 0.000
|
|||
|
|
current_wave_config {Untitled 1}
|
|||
|
|
Untitled 1
|
|||
|
|
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/can_init_0/inst}}
|
|||
|
|
current_wave_config {Untitled 1}
|
|||
|
|
Untitled 1
|
|||
|
|
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst}}
|
|||
|
|
restart
|
|||
|
|
INFO: [Wavedata 42-604] Simulation restarted
|
|||
|
|
run 50 ms
|
|||
|
|
Block Memory Generator module tb_design_1_wrapper.u_dut.design_1_i.uart_parse_real_0.inst.u_dut.u_uart_data_parse.your_instance_name.inst.\native_mem_module.blk_mem_gen_v8_4_7_inst is using a behavioral model for simulation which will not precisely model memory collision behavior.
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_0/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/woecctx/memtx/xpm_memory_base_inst/Initial302_3 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_0/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/memrx/xpm_memory_base_inst/Initial302_35 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_1/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/woecctx/memtx/xpm_memory_base_inst/Initial302_3 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_1/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/memrx/xpm_memory_base_inst/Initial302_35 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
run: Time (s): cpu = 00:00:12 ; elapsed = 00:00:22 . Memory (MB): peak = 4132.000 ; gain = 84.480
|
|||
|
|
current_wave_config {Untitled 1}
|
|||
|
|
Untitled 1
|
|||
|
|
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0}}
|
|||
|
|
open_bd_design {C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd}
|
|||
|
|
close_bd_design [get_bd_designs design_1]
|
|||
|
|
Wrote : <C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
|
|||
|
|
open_bd_design {C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd}
|
|||
|
|
Reading block design file <C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd>...
|
|||
|
|
Adding component instance block -- xilinx.com:user:can_init:1.0 - can_init_0
|
|||
|
|
Adding component instance block -- xilinx.com:user:can_rx_parse_axi:1.0 - can_rx_parse_axi_0
|
|||
|
|
Adding component instance block -- xilinx.com:user:uart_parse_real:1.0 - uart_parse_real_0
|
|||
|
|
Adding component instance block -- xilinx.com:ip:clk_wiz:6.0 - clk_wiz_0
|
|||
|
|
Adding component instance block -- xilinx.com:ip:util_vector_logic:2.0 - util_vector_logic_0
|
|||
|
|
Adding component instance block -- xilinx.com:ip:util_vector_logic:2.0 - util_vector_logic_1
|
|||
|
|
Adding component instance block -- xilinx.com:ip:can:5.1 - can_0
|
|||
|
|
Adding component instance block -- xilinx.com:ip:can:5.1 - can_1
|
|||
|
|
Adding component instance block -- xilinx.com:ip:smartconnect:1.0 - smartconnect_0
|
|||
|
|
Adding component instance block -- xilinx.com:user:ibufg_user:1.0 - ibufg_user_0
|
|||
|
|
Successfully read diagram <design_1> from block design file <C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd>
|
|||
|
|
open_bd_design {C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd}
|
|||
|
|
close_bd_design [get_bd_designs design_1]
|
|||
|
|
Wrote : <C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
|
|||
|
|
open_bd_design {C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd}
|
|||
|
|
Reading block design file <C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd>...
|
|||
|
|
Adding component instance block -- xilinx.com:user:can_init:1.0 - can_init_0
|
|||
|
|
Adding component instance block -- xilinx.com:user:can_rx_parse_axi:1.0 - can_rx_parse_axi_0
|
|||
|
|
Adding component instance block -- xilinx.com:user:uart_parse_real:1.0 - uart_parse_real_0
|
|||
|
|
Adding component instance block -- xilinx.com:ip:clk_wiz:6.0 - clk_wiz_0
|
|||
|
|
Adding component instance block -- xilinx.com:ip:util_vector_logic:2.0 - util_vector_logic_0
|
|||
|
|
Adding component instance block -- xilinx.com:ip:util_vector_logic:2.0 - util_vector_logic_1
|
|||
|
|
Adding component instance block -- xilinx.com:ip:can:5.1 - can_0
|
|||
|
|
Adding component instance block -- xilinx.com:ip:can:5.1 - can_1
|
|||
|
|
Adding component instance block -- xilinx.com:ip:smartconnect:1.0 - smartconnect_0
|
|||
|
|
Adding component instance block -- xilinx.com:user:ibufg_user:1.0 - ibufg_user_0
|
|||
|
|
Successfully read diagram <design_1> from block design file <C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd>
|
|||
|
|
startgroup
|
|||
|
|
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0
|
|||
|
|
endgroup
|
|||
|
|
set_property -dict [list \
|
|||
|
|
CONFIG.NUM_MI {2} \
|
|||
|
|
CONFIG.NUM_SI {2} \
|
|||
|
|
] [get_bd_cells axi_interconnect_0]
|
|||
|
|
set_property location {7 1589 500} [get_bd_cells axi_interconnect_0]
|
|||
|
|
delete_bd_objs [get_bd_intf_nets can_init_0_m_axi] [get_bd_intf_nets can_rx_parse_axi_0_m_axi] [get_bd_intf_nets smartconnect_0_M00_AXI] [get_bd_intf_nets smartconnect_0_M01_AXI] [get_bd_cells smartconnect_0]
|
|||
|
|
set_property location {7 2096 334} [get_bd_cells can_1]
|
|||
|
|
connect_bd_intf_net [get_bd_intf_pins can_1/CAN_S_AXI_LITE] -boundary_type upper [get_bd_intf_pins axi_interconnect_0/M01_AXI]
|
|||
|
|
connect_bd_intf_net -boundary_type upper [get_bd_intf_pins axi_interconnect_0/M00_AXI] [get_bd_intf_pins can_0/CAN_S_AXI_LITE]
|
|||
|
|
connect_bd_intf_net -boundary_type upper [get_bd_intf_pins axi_interconnect_0/S00_AXI] [get_bd_intf_pins can_init_0/m_axi]
|
|||
|
|
connect_bd_intf_net -boundary_type upper [get_bd_intf_pins axi_interconnect_0/S01_AXI] [get_bd_intf_pins can_rx_parse_axi_0/m_axi]
|
|||
|
|
connect_bd_net [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] -boundary_type upper
|
|||
|
|
connect_bd_net [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] -boundary_type upper
|
|||
|
|
connect_bd_net [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] -boundary_type upper
|
|||
|
|
connect_bd_net [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/S01_ACLK] -boundary_type upper
|
|||
|
|
connect_bd_net [get_bd_pins axi_interconnect_0/S01_ACLK] [get_bd_pins ibufg_user_0/clk_out]
|
|||
|
|
connect_bd_net [get_bd_pins axi_interconnect_0/S01_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] -boundary_type upper
|
|||
|
|
connect_bd_net [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] -boundary_type upper
|
|||
|
|
connect_bd_net [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] -boundary_type upper
|
|||
|
|
connect_bd_net [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_0/ARESETN] -boundary_type upper
|
|||
|
|
connect_bd_net [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins util_vector_logic_1/Res]
|
|||
|
|
regenerate_bd_layout
|
|||
|
|
validate_bd_design
|
|||
|
|
INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_0 clk_wiz propagate
|
|||
|
|
ERROR: [BD 41-237] Bus Interface property FREQ_HZ does not match between /axi_interconnect_0/xbar/S00_AXI(10000000) and /can_init_0/m_axi(50000000)
|
|||
|
|
ERROR: [BD 41-237] Bus Interface property FREQ_HZ does not match between /can_0/CAN_S_AXI_LITE(50000000) and /axi_interconnect_0/xbar/M00_AXI(10000000)
|
|||
|
|
ERROR: [BD 41-237] Bus Interface property FREQ_HZ does not match between /can_1/CAN_S_AXI_LITE(50000000) and /axi_interconnect_0/xbar/M01_AXI(10000000)
|
|||
|
|
ERROR: [Common 17-39] 'validate_bd_design' failed due to earlier errors.
|
|||
|
|
startgroup
|
|||
|
|
set_property -dict [list \
|
|||
|
|
CONFIG.CLKOUT2_JITTER {192.113} \
|
|||
|
|
CONFIG.CLKOUT2_PHASE_ERROR {164.985} \
|
|||
|
|
CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {50.000} \
|
|||
|
|
CONFIG.CLKOUT2_USED {true} \
|
|||
|
|
CONFIG.MMCM_CLKOUT1_DIVIDE {20} \
|
|||
|
|
CONFIG.NUM_OUT_CLKS {2} \
|
|||
|
|
] [get_bd_cells clk_wiz_0]
|
|||
|
|
endgroup
|
|||
|
|
delete_bd_objs [get_bd_nets ibufg_user_0_clk_out]
|
|||
|
|
connect_bd_net [get_bd_pins ibufg_user_0/clk_out] [get_bd_pins clk_wiz_0/clk_in1]
|
|||
|
|
connect_bd_net [get_bd_pins clk_wiz_0/clk_out2] [get_bd_pins uart_parse_real_0/clk]
|
|||
|
|
connect_bd_net [get_bd_pins clk_wiz_0/clk_out2] [get_bd_pins can_rx_parse_axi_0/aclk]
|
|||
|
|
connect_bd_net [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] -boundary_type upper
|
|||
|
|
connect_bd_net [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] -boundary_type upper
|
|||
|
|
connect_bd_net [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] -boundary_type upper
|
|||
|
|
connect_bd_net [get_bd_pins axi_interconnect_0/S01_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] -boundary_type upper
|
|||
|
|
connect_bd_net [get_bd_pins can_init_0/clk] [get_bd_pins axi_interconnect_0/S01_ACLK]
|
|||
|
|
connect_bd_net [get_bd_pins can_init_0/clk] [get_bd_pins clk_wiz_0/clk_out2]
|
|||
|
|
connect_bd_net [get_bd_pins can_0/s_axi_aclk] [get_bd_pins can_1/s_axi_aclk]
|
|||
|
|
connect_bd_net [get_bd_pins can_1/s_axi_aclk] [get_bd_pins clk_wiz_0/clk_out2]
|
|||
|
|
regenerate_bd_layout
|
|||
|
|
validate_bd_design
|
|||
|
|
INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_0 clk_wiz propagate
|
|||
|
|
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
|
|||
|
|
Please check your design and connect them as needed:
|
|||
|
|
/can_rx_parse_axi_0/tlm_record_task_id
|
|||
|
|
/can_rx_parse_axi_0/tlm_downlink_task_id
|
|||
|
|
/can_rx_parse_axi_0/tlm_disk_status
|
|||
|
|
/can_rx_parse_axi_0/tlm_cam_dt_status
|
|||
|
|
/can_rx_parse_axi_0/tlm_lvds
|
|||
|
|
/can_rx_parse_axi_0/tlm_reconfig
|
|||
|
|
/can_rx_parse_axi_0/tlm_fpga_temp
|
|||
|
|
/can_rx_parse_axi_0/tlm_compress_flash
|
|||
|
|
|
|||
|
|
generate_target all [get_files C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd]
|
|||
|
|
INFO: [BD 41-1662] The design 'design_1.bd' is already validated. Therefore parameter propagation will not be re-run.
|
|||
|
|
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
|
|||
|
|
Please check your design and connect them as needed:
|
|||
|
|
/can_rx_parse_axi_0/tlm_record_task_id
|
|||
|
|
/can_rx_parse_axi_0/tlm_downlink_task_id
|
|||
|
|
/can_rx_parse_axi_0/tlm_disk_status
|
|||
|
|
/can_rx_parse_axi_0/tlm_cam_dt_status
|
|||
|
|
/can_rx_parse_axi_0/tlm_lvds
|
|||
|
|
/can_rx_parse_axi_0/tlm_reconfig
|
|||
|
|
/can_rx_parse_axi_0/tlm_fpga_temp
|
|||
|
|
/can_rx_parse_axi_0/tlm_compress_flash
|
|||
|
|
|
|||
|
|
Wrote : <C:\proj\pro_finish\can_parse_ctrl\can_parse_ctrl.srcs\sources_1\bd\design_1\design_1.bd>
|
|||
|
|
Wrote : <C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
|
|||
|
|
Verilog Output written to : c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/synth/design_1.v
|
|||
|
|
Verilog Output written to : c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/sim/design_1.v
|
|||
|
|
Verilog Output written to : c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block can_init_0 .
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_wiz_0 .
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_0/xbar .
|
|||
|
|
Exporting to file c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh
|
|||
|
|
Generated Hardware Definition File c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/synth/design_1.hwdef
|
|||
|
|
catch { config_ip_cache -export [get_ips -all design_1_can_init_0_0] }
|
|||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_can_init_0_0
|
|||
|
|
catch { config_ip_cache -export [get_ips -all design_1_clk_wiz_0_0] }
|
|||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_clk_wiz_0_0
|
|||
|
|
catch { config_ip_cache -export [get_ips -all design_1_xbar_0] }
|
|||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_xbar_0
|
|||
|
|
export_ip_user_files -of_objects [get_files C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
|||
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd]
|
|||
|
|
launch_runs design_1_can_init_0_0_synth_1 design_1_clk_wiz_0_0_synth_1 design_1_xbar_0_synth_1 -jobs 24
|
|||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_can_init_0_0
|
|||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_clk_wiz_0_0
|
|||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_xbar_0
|
|||
|
|
[Wed May 27 13:30:13 2026] Launched design_1_can_init_0_0_synth_1, design_1_clk_wiz_0_0_synth_1, design_1_xbar_0_synth_1...
|
|||
|
|
Run output will be captured here:
|
|||
|
|
design_1_can_init_0_0_synth_1: C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.runs/design_1_can_init_0_0_synth_1/runme.log
|
|||
|
|
design_1_clk_wiz_0_0_synth_1: C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.runs/design_1_clk_wiz_0_0_synth_1/runme.log
|
|||
|
|
design_1_xbar_0_synth_1: C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.runs/design_1_xbar_0_synth_1/runme.log
|
|||
|
|
export_simulation -of_objects [get_files C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files -ipstatic_source_dir C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/modelsim} {questa=C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/questa} {riviera=C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/riviera} {activehdl=C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
|||
|
|
close_sim
|
|||
|
|
INFO: xsimkernel Simulation Memory Usage: 32156 KB (Peak: 32156 KB), Simulation CPU Usage: 144139 ms
|
|||
|
|
INFO: [Simtcl 6-16] Simulation closed
|
|||
|
|
launch_simulation
|
|||
|
|
Command: launch_simulation
|
|||
|
|
INFO: [Vivado 12-12493] Simulation top is 'tb_design_1_wrapper'
|
|||
|
|
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
|
|||
|
|
INFO: [Vivado 12-12490] The selected simulation model for 'design_1_axi_interconnect_0_0' IP changed to 'rtl' from '', the simulation run directory will be deleted.
|
|||
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.sim/sim_1/behav/xsim/simulate.log
|
|||
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.sim/sim_1/behav/xsim/tb_design_1_wrapper_behav.wdb
|
|||
|
|
WARNING: [Vivado 12-3661] Failed to remove file:C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.sim/sim_1/behav/xsim/xelab.pb
|
|||
|
|
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
|
|||
|
|
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.sim/sim_1/behav/xsim'
|
|||
|
|
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
|
|||
|
|
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
|
|||
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|||
|
|
INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2023.2/tps/boost_1_72_0'
|
|||
|
|
INFO: [USF-XSim-7] Finding pre-compiled libraries...
|
|||
|
|
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2023.2/data/xsim/xsim.ini' copied to run dir:'C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.sim/sim_1/behav/xsim'
|
|||
|
|
INFO: [SIM-utils-54] Inspecting design source files for 'tb_design_1_wrapper' in fileset 'sim_1'...
|
|||
|
|
INFO: [USF-XSim-97] Finding global include files...
|
|||
|
|
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
|
|||
|
|
INFO: [USF-XSim-2] XSim::Compile design
|
|||
|
|
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.sim/sim_1/behav/xsim'
|
|||
|
|
"xvlog --incr --relax -L uvm -prj tb_design_1_wrapper_vlog.prj"
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/46d7/src/wall_timer.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module wall_timer
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/46d7/src/can_init.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module can_init
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_can_init_0_0/sim/design_1_can_init_0_0.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module design_1_can_init_0_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/d5b1/src/can_rx_parse_axi.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module can_rx_parse_axi
|
|||
|
|
WARNING: [VRFC 10-3380] identifier 'tx_base' is used before its declaration [C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/d5b1/src/can_rx_parse_axi.v:174]
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_can_rx_parse_axi_0_0/sim/design_1_can_rx_parse_axi_0_0.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module design_1_can_rx_parse_axi_0_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_uart_parse_real_0_0/src/ila_0/sim/ila_0.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module ila_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_uart_parse_real_0_0/src/blk_mem_gen_0/sim/blk_mem_gen_0.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module blk_mem_gen_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/5b8a/src/uart.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module uart
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/5b8a/src/uart_data_parse.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module uart_data_parse
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/5b8a/src/uart_parse.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module uart_parse
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/5b8a/src/uart_rx.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module uart_rx
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/5b8a/src/uart_tx.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module uart_tx
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/5b8a/src/uart_parse_real.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module uart_parse_real
|
|||
|
|
WARNING: [VRFC 10-9336] redeclaration of ANSI port 'async_serial' is not allowed [C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/5b8a/src/uart_parse_real.sv:55]
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_uart_parse_real_0_0/sim/design_1_uart_parse_real_0_0.sv" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module design_1_uart_parse_real_0_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_clk_wiz.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module design_1_clk_wiz_0_0_clk_wiz
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module design_1_clk_wiz_0_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_util_vector_logic_0_0/sim/design_1_util_vector_logic_0_0.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module design_1_util_vector_logic_0_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_util_vector_logic_0_1/sim/design_1_util_vector_logic_0_1.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module design_1_util_vector_logic_0_1
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/1583/src/ibufg_user.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module ibufg_user
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_ibufg_user_0_0/sim/design_1_ibufg_user_0_0.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module design_1_ibufg_user_0_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/sim/design_1.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module design_1
|
|||
|
|
INFO: [VRFC 10-311] analyzing module design_1_axi_interconnect_0_0
|
|||
|
|
INFO: [VRFC 10-311] analyzing module m00_couplers_imp_1CA5Z32
|
|||
|
|
INFO: [VRFC 10-311] analyzing module m01_couplers_imp_I4GRPB
|
|||
|
|
INFO: [VRFC 10-311] analyzing module s00_couplers_imp_O7FAN0
|
|||
|
|
INFO: [VRFC 10-311] analyzing module s01_couplers_imp_1F69D31
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_xbar_0/sim/design_1_xbar_0.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module design_1_xbar_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module design_1_wrapper
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/tb_design_1_wrapper.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module tb_design_1_wrapper
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.sim/sim_1/behav/xsim/glbl.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module glbl
|
|||
|
|
"xvhdl --incr --relax -prj tb_design_1_wrapper_vhdl.prj"
|
|||
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_can_0_2/sim/design_1_can_0_2.vhd" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-3107] analyzing entity 'design_1_can_0_2'
|
|||
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_can_0_3/sim/design_1_can_0_3.vhd" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-3107] analyzing entity 'design_1_can_0_3'
|
|||
|
|
INFO: [USF-XSim-69] 'compile' step finished in '4' seconds
|
|||
|
|
INFO: [USF-XSim-3] XSim::Elaborate design
|
|||
|
|
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.sim/sim_1/behav/xsim'
|
|||
|
|
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L blk_mem_gen_v8_4_7 -L util_vector_logic_v2_0_3 -L lib_cdc_v1_0_2 -L lib_bmg_v1_0_16 -L can_v5_1_1 -L generic_baseblocks_v2_1_1 -L axi_infrastructure_v1_1_0 -L axi_register_slice_v2_1_29 -L fifo_generator_v13_2_9 -L axi_data_fifo_v2_1_28 -L axi_crossbar_v2_1_30 -L uvm -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_design_1_wrapper_behav xil_defaultlib.tb_design_1_wrapper xil_defaultlib.glbl -log elaborate.log"
|
|||
|
|
Vivado Simulator v2023.2
|
|||
|
|
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
|||
|
|
Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
|||
|
|
Running: C:/Xilinx/Vivado/2023.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L blk_mem_gen_v8_4_7 -L util_vector_logic_v2_0_3 -L lib_cdc_v1_0_2 -L lib_bmg_v1_0_16 -L can_v5_1_1 -L generic_baseblocks_v2_1_1 -L axi_infrastructure_v1_1_0 -L axi_register_slice_v2_1_29 -L fifo_generator_v13_2_9 -L axi_data_fifo_v2_1_28 -L axi_crossbar_v2_1_30 -L uvm -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_design_1_wrapper_behav xil_defaultlib.tb_design_1_wrapper xil_defaultlib.glbl -log elaborate.log
|
|||
|
|
Using 2 slave threads.
|
|||
|
|
Starting static elaboration
|
|||
|
|
Pass Through NonSizing Optimizer
|
|||
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 16 for port 'cfg_div_i' [C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/5b8a/src/uart.sv:43]
|
|||
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 16 for port 'cfg_div_i' [C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/5b8a/src/uart.sv:63]
|
|||
|
|
WARNING: [VRFC 10-3091] actual bit length 166 differs from formal bit length 182 for port 'probe0' [C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/5b8a/src/uart_data_parse.sv:347]
|
|||
|
|
WARNING: [VRFC 10-5021] port 'ip2bus_intrevent' is not connected on this instance [C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/sim/design_1.v:183]
|
|||
|
|
WARNING: [VRFC 10-5021] port 'ip2bus_intrevent' is not connected on this instance [C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/sim/design_1.v:206]
|
|||
|
|
Completed static elaboration
|
|||
|
|
Starting simulation data flow analysis
|
|||
|
|
WARNING: [XSIM 43-4099] "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/46d7/src/wall_timer.sv" Line 7. Module wall_timer(MODULE_FREQ_HZ=50000000,MS_WIDTH=10) doesn't have a timescale but at least one module in design has a timescale.
|
|||
|
|
WARNING: [XSIM 43-4099] "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/5b8a/src/uart.sv" Line 11. Module uart(CLOCK_FREQUENCY=50000000,BAUD_RATE=2000000) doesn't have a timescale but at least one module in design has a timescale.
|
|||
|
|
WARNING: [XSIM 43-4099] "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/46d7/src/wall_timer.sv" Line 7. Module wall_timer(MODULE_FREQ_HZ=50000000,MS_WIDTH=10) doesn't have a timescale but at least one module in design has a timescale.
|
|||
|
|
WARNING: [XSIM 43-4099] "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/5b8a/src/uart.sv" Line 11. Module uart(CLOCK_FREQUENCY=50000000,BAUD_RATE=2000000) doesn't have a timescale but at least one module in design has a timescale.
|
|||
|
|
Completed simulation data flow analysis
|
|||
|
|
Time Resolution for simulation is 1ps
|
|||
|
|
Compiling package std.standard
|
|||
|
|
Compiling package std.textio
|
|||
|
|
Compiling package ieee.std_logic_1164
|
|||
|
|
Compiling package ieee.numeric_std
|
|||
|
|
Compiling package ieee.std_logic_arith
|
|||
|
|
Compiling package ieee.std_logic_unsigned
|
|||
|
|
Compiling package synopsys.attributes
|
|||
|
|
Compiling package ieee.std_logic_misc
|
|||
|
|
Compiling package can_v5_1_1.proc_common_pkg
|
|||
|
|
Compiling package can_v5_1_1.ipif_pkg
|
|||
|
|
Compiling package can_v5_1_1.can_ip_pkg
|
|||
|
|
Compiling package xpm.vcomponents
|
|||
|
|
Compiling package unisim.vcomponents
|
|||
|
|
Compiling package ieee.vital_timing
|
|||
|
|
Compiling package ieee.vital_primitives
|
|||
|
|
Compiling package unisim.vpkg
|
|||
|
|
Compiling package xpm.$unit_xpm_cdc_sv_220102727
|
|||
|
|
Compiling package xpm.axi_xil_sb_pkg_xpm_nsu
|
|||
|
|
Compiling package xpm.axi_data_integrity_checker_xpm_n...
|
|||
|
|
Compiling package xpm.xpm_axi_data_integrity_checker_n...
|
|||
|
|
Compiling package xpm.xpm_axi_xil_sb_pkg_nmu
|
|||
|
|
Compiling module xil_defaultlib.m00_couplers_imp_1CA5Z32
|
|||
|
|
Compiling module xil_defaultlib.m01_couplers_imp_I4GRPB
|
|||
|
|
Compiling module xil_defaultlib.s00_couplers_imp_O7FAN0
|
|||
|
|
Compiling module xil_defaultlib.s01_couplers_imp_1F69D31
|
|||
|
|
Compiling module generic_baseblocks_v2_1_1.generic_baseblocks_v2_1_1_mux_en...
|
|||
|
|
Compiling module axi_crossbar_v2_1_30.axi_crossbar_v2_1_30_addr_arbite...
|
|||
|
|
Compiling module generic_baseblocks_v2_1_1.generic_baseblocks_v2_1_1_carry_...
|
|||
|
|
Compiling module generic_baseblocks_v2_1_1.generic_baseblocks_v2_1_1_compar...
|
|||
|
|
Compiling module generic_baseblocks_v2_1_1.generic_baseblocks_v2_1_1_compar...
|
|||
|
|
Compiling module axi_crossbar_v2_1_30.axi_crossbar_v2_1_30_addr_decode...
|
|||
|
|
Compiling module axi_crossbar_v2_1_30.axi_crossbar_v2_1_30_splitter(C_...
|
|||
|
|
Compiling module axi_crossbar_v2_1_30.axi_crossbar_v2_1_30_splitter
|
|||
|
|
Compiling module generic_baseblocks_v2_1_1.generic_baseblocks_v2_1_1_mux_en...
|
|||
|
|
Compiling module generic_baseblocks_v2_1_1.generic_baseblocks_v2_1_1_mux_en...
|
|||
|
|
Compiling module generic_baseblocks_v2_1_1.generic_baseblocks_v2_1_1_mux_en...
|
|||
|
|
Compiling module generic_baseblocks_v2_1_1.generic_baseblocks_v2_1_1_mux_en...
|
|||
|
|
Compiling module axi_register_slice_v2_1_29.axi_register_slice_v2_1_29_axic_...
|
|||
|
|
Compiling module generic_baseblocks_v2_1_1.generic_baseblocks_v2_1_1_mux_en...
|
|||
|
|
Compiling module axi_crossbar_v2_1_30.axi_crossbar_v2_1_30_decerr_slav...
|
|||
|
|
Compiling module axi_crossbar_v2_1_30.axi_crossbar_v2_1_30_crossbar_sa...
|
|||
|
|
Compiling module axi_crossbar_v2_1_30.axi_crossbar_v2_1_30_axi_crossba...
|
|||
|
|
Compiling module xil_defaultlib.design_1_xbar_0
|
|||
|
|
Compiling module xil_defaultlib.design_1_axi_interconnect_0_0
|
|||
|
|
Compiling architecture imp of entity can_v5_1_1.address_decoder [\address_decoder(c_bus_awidth=8,...]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.slave_attachment [\slave_attachment(c_ard_addr_ran...]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.axi_lite_ipif [\axi_lite_ipif(c_s_axi_addr_widt...]
|
|||
|
|
Compiling architecture implementation of entity can_v5_1_1.can_sync_block [\can_sync_block(c_reset_state=1,...]
|
|||
|
|
Compiling architecture fdre_v of entity unisim.FDRE [fdre_default]
|
|||
|
|
Compiling architecture fdr_v of entity unisim.FDR [fdr_default]
|
|||
|
|
Compiling architecture implementation of entity lib_cdc_v1_0_2.cdc_sync [\cdc_sync(c_reset_state=1,c_flop...]
|
|||
|
|
Compiling architecture implementation of entity lib_cdc_v1_0_2.cdc_sync [\cdc_sync(c_reset_state=1,c_sing...]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.CAN_OL_SYNCH [can_ol_synch_default]
|
|||
|
|
Compiling module xpm.xpm_memory_base(MEMORY_SIZE=1638...
|
|||
|
|
Compiling module xpm.xpm_memory_tdpram(MEMORY_SIZE=16...
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.can_tl_arbchk [can_tl_arbchk_default]
|
|||
|
|
Compiling architecture fdce_v of entity unisim.FDCE [fdce_default]
|
|||
|
|
Compiling architecture fdc_v of entity unisim.FDC [fdc_default]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.can_ol_fifopriority [can_ol_fifopriority_default]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.CAN_TXFIFO_CNTL_GEN [\CAN_TXFIFO_CNTL_GEN(c_can_tx_aw...]
|
|||
|
|
Compiling module xpm.xpm_cdc_single(DEST_SYNC_FF=2,IN...
|
|||
|
|
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
|
|||
|
|
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=16...
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.CAN_RXFIFO_CNTL_GEN [\CAN_RXFIFO_CNTL_GEN(c_can_rx_aw...]
|
|||
|
|
Compiling module xpm.xpm_cdc_array_single(DEST_SYNC_F...
|
|||
|
|
Compiling module xpm.xpm_cdc_async_rst(DEST_SYNC_FF=4...
|
|||
|
|
Compiling architecture implementation of entity can_v5_1_1.can_sync_block [\can_sync_block(c_reset_state=1)...]
|
|||
|
|
Compiling architecture implementation of entity lib_cdc_v1_0_2.cdc_sync [\cdc_sync(c_reset_state=1)\]
|
|||
|
|
Compiling architecture implementation of entity lib_cdc_v1_0_2.cdc_sync [\cdc_sync(c_reset_state=1,c_sing...]
|
|||
|
|
Compiling architecture implementation of entity lib_cdc_v1_0_2.cdc_sync [\cdc_sync(c_reset_state=1,c_vect...]
|
|||
|
|
Compiling architecture implementation of entity lib_cdc_v1_0_2.cdc_sync [\cdc_sync(c_reset_state=1,c_flop...]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.CAN_IC_MAIN [can_ic_main_default]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.CAN_OL_TOP [\CAN_OL_TOP(c_can_rx_awidth=4,c_...]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.CAN_TL_ACF [can_tl_acf_default]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.CAN_TL_CLKDIV [can_tl_clkdiv_default]
|
|||
|
|
Compiling architecture implementation of entity lib_cdc_v1_0_2.cdc_sync [\cdc_sync(c_reset_state=1,c_sing...]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.CAN_TL_SYNCH [\CAN_TL_SYNCH(c_can_acf_defined=...]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.CAN_TL_BTL [can_tl_btl_default]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.CAN_TL_OM [can_tl_om_default]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.can_tl_arbit [can_tl_arbit_default]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.CAN_TL_BSP [\CAN_TL_BSP(c_can_acf_defined='1...]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.CAN_TL_TOP [\CAN_TL_TOP(c_can_acf_defined='1...]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.cantop [\cantop(c_can_rx_dpth=16,c_can_t...]
|
|||
|
|
Compiling architecture imp of entity can_v5_1_1.can_top [\can_top(c_can_rx_dpth=16,c_can_...]
|
|||
|
|
Compiling architecture amd of entity can_v5_1_1.can_v5_1_1 [\can_v5_1_1(c_can_rx_dpth=16,c_c...]
|
|||
|
|
Compiling architecture design_1_can_0_2_arch of entity xil_defaultlib.design_1_can_0_2 [design_1_can_0_2_default]
|
|||
|
|
Compiling architecture design_1_can_0_3_arch of entity xil_defaultlib.design_1_can_0_3 [design_1_can_0_3_default]
|
|||
|
|
Compiling module xil_defaultlib.wall_timer(MODULE_FREQ_HZ=500000...
|
|||
|
|
Compiling module xil_defaultlib.can_init(MODE_MSR=32'b010,DELAY_...
|
|||
|
|
Compiling module xil_defaultlib.design_1_can_init_0_0
|
|||
|
|
Compiling module xil_defaultlib.can_rx_parse_axi
|
|||
|
|
Compiling module xil_defaultlib.design_1_can_rx_parse_axi_0_0
|
|||
|
|
Compiling module unisims_ver.IBUF
|
|||
|
|
Compiling module unisims_ver.MMCME2_ADV(CLKFBOUT_MULT_F=20.0,...
|
|||
|
|
Compiling module unisims_ver.BUFG
|
|||
|
|
Compiling module xil_defaultlib.design_1_clk_wiz_0_0_clk_wiz
|
|||
|
|
Compiling module xil_defaultlib.design_1_clk_wiz_0_0
|
|||
|
|
Compiling module unisims_ver.IBUFG
|
|||
|
|
Compiling module xil_defaultlib.ibufg_user
|
|||
|
|
Compiling module xil_defaultlib.design_1_ibufg_user_0_0
|
|||
|
|
Compiling module xil_defaultlib.uart_rx
|
|||
|
|
Compiling module xil_defaultlib.uart_tx
|
|||
|
|
Compiling module xil_defaultlib.uart(CLOCK_FREQUENCY=50000000,BA...
|
|||
|
|
Compiling module blk_mem_gen_v8_4_7.blk_mem_gen_v8_4_7_output_stage(...
|
|||
|
|
Compiling module blk_mem_gen_v8_4_7.blk_mem_gen_v8_4_7_output_stage(...
|
|||
|
|
Compiling module blk_mem_gen_v8_4_7.blk_mem_gen_v8_4_7_softecc_outpu...
|
|||
|
|
Compiling module blk_mem_gen_v8_4_7.blk_mem_gen_v8_4_7_mem_module(C_...
|
|||
|
|
Compiling module blk_mem_gen_v8_4_7.blk_mem_axi_regs_fwd_v8_4(C_DATA...
|
|||
|
|
Compiling module blk_mem_gen_v8_4_7.blk_mem_gen_v8_4_7(C_ELABORATION...
|
|||
|
|
Compiling module xil_defaultlib.blk_mem_gen_0
|
|||
|
|
Compiling module xil_defaultlib.ila_0
|
|||
|
|
Compiling module xil_defaultlib.uart_data_parse_default
|
|||
|
|
Compiling module xil_defaultlib.uart_parse(CLOCK_FREQUENCY=50000...
|
|||
|
|
Compiling module xil_defaultlib.uart_parse_real
|
|||
|
|
Compiling module xil_defaultlib.design_1_uart_parse_real_0_0
|
|||
|
|
Compiling module util_vector_logic_v2_0_3.util_vector_logic_v2_0_3_util_ve...
|
|||
|
|
Compiling module xil_defaultlib.design_1_util_vector_logic_0_0
|
|||
|
|
Compiling module util_vector_logic_v2_0_3.util_vector_logic_v2_0_3_util_ve...
|
|||
|
|
Compiling module xil_defaultlib.design_1_util_vector_logic_0_1
|
|||
|
|
Compiling module xil_defaultlib.design_1
|
|||
|
|
Compiling module xil_defaultlib.design_1_wrapper
|
|||
|
|
Compiling module xil_defaultlib.tb_design_1_wrapper
|
|||
|
|
Compiling module xil_defaultlib.glbl
|
|||
|
|
Built simulation snapshot tb_design_1_wrapper_behav
|
|||
|
|
run_program: Time (s): cpu = 00:00:01 ; elapsed = 00:00:11 . Memory (MB): peak = 5821.062 ; gain = 0.000
|
|||
|
|
INFO: [USF-XSim-69] 'elaborate' step finished in '11' seconds
|
|||
|
|
INFO: [USF-XSim-4] XSim::Simulate design
|
|||
|
|
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.sim/sim_1/behav/xsim'
|
|||
|
|
INFO: [USF-XSim-98] *** Running xsim
|
|||
|
|
with args "tb_design_1_wrapper_behav -key {Behavioral:sim_1:Functional:tb_design_1_wrapper} -tclbatch {tb_design_1_wrapper.tcl} -protoinst "protoinst_files/design_1.protoinst" -log {simulate.log}"
|
|||
|
|
INFO: [USF-XSim-8] Loading simulator feature
|
|||
|
|
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_1.protoinst
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//axi_interconnect_0/M00_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//axi_interconnect_0/M01_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//axi_interconnect_0/S00_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//axi_interconnect_0/S01_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//axi_interconnect_0/m00_couplers/M_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//axi_interconnect_0/m00_couplers/S_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//axi_interconnect_0/m01_couplers/M_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//axi_interconnect_0/m01_couplers/S_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//axi_interconnect_0/s00_couplers/M_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//axi_interconnect_0/s00_couplers/S_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//axi_interconnect_0/s01_couplers/M_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//axi_interconnect_0/s01_couplers/S_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//axi_interconnect_0/xbar/M00_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//axi_interconnect_0/xbar/M01_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//axi_interconnect_0/xbar/S00_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//axi_interconnect_0/xbar/S01_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//can_0/CAN_S_AXI_LITE
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//can_1/CAN_S_AXI_LITE
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//can_init_0/m_axi
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//can_rx_parse_axi_0/m_axi
|
|||
|
|
Time resolution is 1 ps
|
|||
|
|
source tb_design_1_wrapper.tcl
|
|||
|
|
# set curr_wave [current_wave_config]
|
|||
|
|
# if { [string length $curr_wave] == 0 } {
|
|||
|
|
# if { [llength [get_objects]] > 0} {
|
|||
|
|
# add_wave /
|
|||
|
|
# set_property needs_save false [current_wave_config]
|
|||
|
|
# } else {
|
|||
|
|
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
|||
|
|
# }
|
|||
|
|
# }
|
|||
|
|
# run 1000ns
|
|||
|
|
Block Memory Generator module tb_design_1_wrapper.u_dut.design_1_i.uart_parse_real_0.inst.u_dut.u_uart_data_parse.your_instance_name.inst.\native_mem_module.blk_mem_gen_v8_4_7_inst is using a behavioral model for simulation which will not precisely model memory collision behavior.
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_0/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/woecctx/memtx/xpm_memory_base_inst/Initial302_26 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_0/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/memrx/xpm_memory_base_inst/Initial302_58 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_1/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/woecctx/memtx/xpm_memory_base_inst/Initial302_26 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_1/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/memrx/xpm_memory_base_inst/Initial302_58 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_design_1_wrapper_behav' loaded.
|
|||
|
|
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
|
|||
|
|
launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:17 . Memory (MB): peak = 5821.062 ; gain = 0.000
|
|||
|
|
current_wave_config {Untitled 2}
|
|||
|
|
Untitled 2
|
|||
|
|
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/can_rx_parse_axi_0}}
|
|||
|
|
restart
|
|||
|
|
INFO: [Wavedata 42-604] Simulation restarted
|
|||
|
|
run 50 ms
|
|||
|
|
Block Memory Generator module tb_design_1_wrapper.u_dut.design_1_i.uart_parse_real_0.inst.u_dut.u_uart_data_parse.your_instance_name.inst.\native_mem_module.blk_mem_gen_v8_4_7_inst is using a behavioral model for simulation which will not precisely model memory collision behavior.
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_0/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/woecctx/memtx/xpm_memory_base_inst/Initial302_26 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_0/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/memrx/xpm_memory_base_inst/Initial302_58 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_1/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/woecctx/memtx/xpm_memory_base_inst/Initial302_26 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_1/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/memrx/xpm_memory_base_inst/Initial302_58 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
run: Time (s): cpu = 00:00:10 ; elapsed = 00:00:15 . Memory (MB): peak = 5821.062 ; gain = 0.000
|
|||
|
|
current_wave_config {Untitled 2}
|
|||
|
|
Untitled 2
|
|||
|
|
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/axi_interconnect_0}}
|
|||
|
|
restart
|
|||
|
|
INFO: [Wavedata 42-604] Simulation restarted
|
|||
|
|
run 50 ms
|
|||
|
|
Block Memory Generator module tb_design_1_wrapper.u_dut.design_1_i.uart_parse_real_0.inst.u_dut.u_uart_data_parse.your_instance_name.inst.\native_mem_module.blk_mem_gen_v8_4_7_inst is using a behavioral model for simulation which will not precisely model memory collision behavior.
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_0/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/woecctx/memtx/xpm_memory_base_inst/Initial302_26 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_0/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/memrx/xpm_memory_base_inst/Initial302_58 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_1/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/woecctx/memtx/xpm_memory_base_inst/Initial302_26 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_1/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/memrx/xpm_memory_base_inst/Initial302_58 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
run: Time (s): cpu = 00:00:03 ; elapsed = 00:00:10 . Memory (MB): peak = 5821.062 ; gain = 0.000
|
|||
|
|
open_bd_design {C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd}
|
|||
|
|
current_wave_config {Untitled 2}
|
|||
|
|
Untitled 2
|
|||
|
|
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/can_0}}
|
|||
|
|
restart
|
|||
|
|
INFO: [Wavedata 42-604] Simulation restarted
|
|||
|
|
run 50 ms
|
|||
|
|
Block Memory Generator module tb_design_1_wrapper.u_dut.design_1_i.uart_parse_real_0.inst.u_dut.u_uart_data_parse.your_instance_name.inst.\native_mem_module.blk_mem_gen_v8_4_7_inst is using a behavioral model for simulation which will not precisely model memory collision behavior.
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_0/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/woecctx/memtx/xpm_memory_base_inst/Initial302_26 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_0/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/memrx/xpm_memory_base_inst/Initial302_58 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_1/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/woecctx/memtx/xpm_memory_base_inst/Initial302_26 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_1/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/memrx/xpm_memory_base_inst/Initial302_58 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
run: Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 5821.062 ; gain = 0.000
|
|||
|
|
current_wave_config {Untitled 2}
|
|||
|
|
Untitled 2
|
|||
|
|
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/can_init_0}}
|
|||
|
|
current_wave_config {Untitled 2}
|
|||
|
|
Untitled 2
|
|||
|
|
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/axi_interconnect_0}}
|
|||
|
|
current_wave_config {Untitled 2}
|
|||
|
|
Untitled 2
|
|||
|
|
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/can_init_0}}
|
|||
|
|
current_wave_config {Untitled 2}
|
|||
|
|
Untitled 2
|
|||
|
|
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/axi_interconnect_0/m00_couplers}}
|
|||
|
|
current_wave_config {Untitled 2}
|
|||
|
|
Untitled 2
|
|||
|
|
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/axi_interconnect_0/s00_couplers}}
|
|||
|
|
open_bd_design {C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd}
|
|||
|
|
restart
|
|||
|
|
INFO: [Wavedata 42-604] Simulation restarted
|
|||
|
|
run 50 ms
|
|||
|
|
Block Memory Generator module tb_design_1_wrapper.u_dut.design_1_i.uart_parse_real_0.inst.u_dut.u_uart_data_parse.your_instance_name.inst.\native_mem_module.blk_mem_gen_v8_4_7_inst is using a behavioral model for simulation which will not precisely model memory collision behavior.
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_0/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/woecctx/memtx/xpm_memory_base_inst/Initial302_26 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_0/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/memrx/xpm_memory_base_inst/Initial302_58 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_1/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/woecctx/memtx/xpm_memory_base_inst/Initial302_26 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_1/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/memrx/xpm_memory_base_inst/Initial302_58 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
run: Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 6811.980 ; gain = 0.000
|
|||
|
|
open_bd_design {C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd}
|
|||
|
|
open_bd_design {C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd}
|
|||
|
|
set_property range 128 [get_bd_addr_segs {can_init_0/m_axi/SEG_can_0_Reg}]
|
|||
|
|
set_property offset 0x00000000 [get_bd_addr_segs {can_init_0/m_axi/SEG_can_0_Reg}]
|
|||
|
|
set_property range 128 [get_bd_addr_segs {can_init_0/m_axi/SEG_can_1_Reg}]
|
|||
|
|
set_property offset 0x00000200 [get_bd_addr_segs {can_init_0/m_axi/SEG_can_1_Reg}]
|
|||
|
|
set_property range 512 [get_bd_addr_segs {can_init_0/m_axi/SEG_can_0_Reg}]
|
|||
|
|
set_property range 256 [get_bd_addr_segs {can_init_0/m_axi/SEG_can_0_Reg}]
|
|||
|
|
set_property range 256 [get_bd_addr_segs {can_init_0/m_axi/SEG_can_1_Reg}]
|
|||
|
|
set_property offset 0x0 [get_bd_addr_segs {can_rx_parse_axi_0/m_axi/SEG_can_0_Reg}]
|
|||
|
|
set_property range 256 [get_bd_addr_segs {can_rx_parse_axi_0/m_axi/SEG_can_0_Reg}]
|
|||
|
|
set_property range 256 [get_bd_addr_segs {can_rx_parse_axi_0/m_axi/SEG_can_1_Reg}]
|
|||
|
|
set_property offset 0x200 [get_bd_addr_segs {can_rx_parse_axi_0/m_axi/SEG_can_1_Reg}]
|
|||
|
|
save_bd_design
|
|||
|
|
Wrote : <C:\proj\pro_finish\can_parse_ctrl\can_parse_ctrl.srcs\sources_1\bd\design_1\design_1.bd>
|
|||
|
|
regenerate_bd_layout
|
|||
|
|
validate_bd_design
|
|||
|
|
INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_0 clk_wiz propagate
|
|||
|
|
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
|
|||
|
|
Please check your design and connect them as needed:
|
|||
|
|
/can_rx_parse_axi_0/tlm_record_task_id
|
|||
|
|
/can_rx_parse_axi_0/tlm_downlink_task_id
|
|||
|
|
/can_rx_parse_axi_0/tlm_disk_status
|
|||
|
|
/can_rx_parse_axi_0/tlm_cam_dt_status
|
|||
|
|
/can_rx_parse_axi_0/tlm_lvds
|
|||
|
|
/can_rx_parse_axi_0/tlm_reconfig
|
|||
|
|
/can_rx_parse_axi_0/tlm_fpga_temp
|
|||
|
|
/can_rx_parse_axi_0/tlm_compress_flash
|
|||
|
|
|
|||
|
|
generate_target all [get_files C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd]
|
|||
|
|
INFO: [BD 41-1662] The design 'design_1.bd' is already validated. Therefore parameter propagation will not be re-run.
|
|||
|
|
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
|
|||
|
|
Please check your design and connect them as needed:
|
|||
|
|
/can_rx_parse_axi_0/tlm_record_task_id
|
|||
|
|
/can_rx_parse_axi_0/tlm_downlink_task_id
|
|||
|
|
/can_rx_parse_axi_0/tlm_disk_status
|
|||
|
|
/can_rx_parse_axi_0/tlm_cam_dt_status
|
|||
|
|
/can_rx_parse_axi_0/tlm_lvds
|
|||
|
|
/can_rx_parse_axi_0/tlm_reconfig
|
|||
|
|
/can_rx_parse_axi_0/tlm_fpga_temp
|
|||
|
|
/can_rx_parse_axi_0/tlm_compress_flash
|
|||
|
|
|
|||
|
|
Wrote : <C:\proj\pro_finish\can_parse_ctrl\can_parse_ctrl.srcs\sources_1\bd\design_1\design_1.bd>
|
|||
|
|
Verilog Output written to : c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/synth/design_1.v
|
|||
|
|
Verilog Output written to : c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/sim/design_1.v
|
|||
|
|
Verilog Output written to : c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_0/xbar .
|
|||
|
|
Exporting to file c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh
|
|||
|
|
Generated Hardware Definition File c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/synth/design_1.hwdef
|
|||
|
|
catch { config_ip_cache -export [get_ips -all design_1_xbar_0] }
|
|||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_xbar_0
|
|||
|
|
export_ip_user_files -of_objects [get_files C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
|||
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd]
|
|||
|
|
launch_runs design_1_xbar_0_synth_1 -jobs 24
|
|||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_xbar_0
|
|||
|
|
[Wed May 27 14:14:04 2026] Launched design_1_xbar_0_synth_1...
|
|||
|
|
Run output will be captured here: C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.runs/design_1_xbar_0_synth_1/runme.log
|
|||
|
|
export_simulation -of_objects [get_files C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files -ipstatic_source_dir C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/modelsim} {questa=C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/questa} {riviera=C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/riviera} {activehdl=C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
|||
|
|
close_sim
|
|||
|
|
INFO: xsimkernel Simulation Memory Usage: 23880 KB (Peak: 23880 KB), Simulation CPU Usage: 37374 ms
|
|||
|
|
INFO: [Simtcl 6-16] Simulation closed
|
|||
|
|
launch_simulation
|
|||
|
|
Command: launch_simulation
|
|||
|
|
INFO: [Vivado 12-12493] Simulation top is 'tb_design_1_wrapper'
|
|||
|
|
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
|
|||
|
|
boost::filesystem::remove: <20><>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD>ô<EFBFBD><C3B4>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><DEB7><EFBFBD><EFBFBD>ʡ<EFBFBD>: "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.sim/sim_1/behav/xsim/simulate.log"
|
|||
|
|
launch_simulation
|
|||
|
|
Command: launch_simulation
|
|||
|
|
INFO: [Vivado 12-12493] Simulation top is 'tb_design_1_wrapper'
|
|||
|
|
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
|
|||
|
|
boost::filesystem::remove: <20><>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD>ô<EFBFBD><C3B4>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><DEB7><EFBFBD><EFBFBD>ʡ<EFBFBD>: "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.sim/sim_1/behav/xsim/simulate.log"
|
|||
|
|
launch_simulation
|
|||
|
|
Command: launch_simulation
|
|||
|
|
INFO: [Vivado 12-12493] Simulation top is 'tb_design_1_wrapper'
|
|||
|
|
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
|
|||
|
|
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
|
|||
|
|
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.sim/sim_1/behav/xsim'
|
|||
|
|
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
|
|||
|
|
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
|
|||
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|||
|
|
INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2023.2/tps/boost_1_72_0'
|
|||
|
|
INFO: [USF-XSim-7] Finding pre-compiled libraries...
|
|||
|
|
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2023.2/data/xsim/xsim.ini' copied to run dir:'C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.sim/sim_1/behav/xsim'
|
|||
|
|
INFO: [SIM-utils-54] Inspecting design source files for 'tb_design_1_wrapper' in fileset 'sim_1'...
|
|||
|
|
INFO: [USF-XSim-97] Finding global include files...
|
|||
|
|
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
|
|||
|
|
INFO: [USF-XSim-2] XSim::Compile design
|
|||
|
|
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.sim/sim_1/behav/xsim'
|
|||
|
|
"xvlog --incr --relax -L uvm -prj tb_design_1_wrapper_vlog.prj"
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_clk_wiz.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module design_1_clk_wiz_0_0_clk_wiz
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module design_1_clk_wiz_0_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_util_vector_logic_0_0/sim/design_1_util_vector_logic_0_0.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module design_1_util_vector_logic_0_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_util_vector_logic_0_1/sim/design_1_util_vector_logic_0_1.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module design_1_util_vector_logic_0_1
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/1583/src/ibufg_user.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module ibufg_user
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_ibufg_user_0_0/sim/design_1_ibufg_user_0_0.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module design_1_ibufg_user_0_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/sim/design_1.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module design_1
|
|||
|
|
INFO: [VRFC 10-311] analyzing module design_1_axi_interconnect_0_0
|
|||
|
|
INFO: [VRFC 10-311] analyzing module m00_couplers_imp_1CA5Z32
|
|||
|
|
INFO: [VRFC 10-311] analyzing module m01_couplers_imp_I4GRPB
|
|||
|
|
INFO: [VRFC 10-311] analyzing module s00_couplers_imp_O7FAN0
|
|||
|
|
INFO: [VRFC 10-311] analyzing module s01_couplers_imp_1F69D31
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ip/design_1_xbar_0/sim/design_1_xbar_0.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module design_1_xbar_0
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module design_1_wrapper
|
|||
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/tb_design_1_wrapper.v" into library xil_defaultlib
|
|||
|
|
INFO: [VRFC 10-311] analyzing module tb_design_1_wrapper
|
|||
|
|
"xvhdl --incr --relax -prj tb_design_1_wrapper_vhdl.prj"
|
|||
|
|
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
|
|||
|
|
INFO: [USF-XSim-3] XSim::Elaborate design
|
|||
|
|
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.sim/sim_1/behav/xsim'
|
|||
|
|
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L blk_mem_gen_v8_4_7 -L util_vector_logic_v2_0_3 -L lib_cdc_v1_0_2 -L lib_bmg_v1_0_16 -L can_v5_1_1 -L generic_baseblocks_v2_1_1 -L axi_infrastructure_v1_1_0 -L axi_register_slice_v2_1_29 -L fifo_generator_v13_2_9 -L axi_data_fifo_v2_1_28 -L axi_crossbar_v2_1_30 -L uvm -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_design_1_wrapper_behav xil_defaultlib.tb_design_1_wrapper xil_defaultlib.glbl -log elaborate.log"
|
|||
|
|
Vivado Simulator v2023.2
|
|||
|
|
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
|||
|
|
Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
|||
|
|
Running: C:/Xilinx/Vivado/2023.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L blk_mem_gen_v8_4_7 -L util_vector_logic_v2_0_3 -L lib_cdc_v1_0_2 -L lib_bmg_v1_0_16 -L can_v5_1_1 -L generic_baseblocks_v2_1_1 -L axi_infrastructure_v1_1_0 -L axi_register_slice_v2_1_29 -L fifo_generator_v13_2_9 -L axi_data_fifo_v2_1_28 -L axi_crossbar_v2_1_30 -L uvm -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_design_1_wrapper_behav xil_defaultlib.tb_design_1_wrapper xil_defaultlib.glbl -log elaborate.log
|
|||
|
|
Using 2 slave threads.
|
|||
|
|
Starting static elaboration
|
|||
|
|
Pass Through NonSizing Optimizer
|
|||
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 16 for port 'cfg_div_i' [C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/5b8a/src/uart.sv:43]
|
|||
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 16 for port 'cfg_div_i' [C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/5b8a/src/uart.sv:63]
|
|||
|
|
WARNING: [VRFC 10-3091] actual bit length 166 differs from formal bit length 182 for port 'probe0' [C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/5b8a/src/uart_data_parse.sv:347]
|
|||
|
|
WARNING: [VRFC 10-5021] port 'ip2bus_intrevent' is not connected on this instance [C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/sim/design_1.v:183]
|
|||
|
|
WARNING: [VRFC 10-5021] port 'ip2bus_intrevent' is not connected on this instance [C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/sim/design_1.v:206]
|
|||
|
|
Completed static elaboration
|
|||
|
|
Starting simulation data flow analysis
|
|||
|
|
WARNING: [XSIM 43-4099] "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/46d7/src/wall_timer.sv" Line 7. Module wall_timer(MODULE_FREQ_HZ=50000000,MS_WIDTH=10) doesn't have a timescale but at least one module in design has a timescale.
|
|||
|
|
WARNING: [XSIM 43-4099] "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/5b8a/src/uart.sv" Line 11. Module uart(CLOCK_FREQUENCY=50000000,BAUD_RATE=2000000) doesn't have a timescale but at least one module in design has a timescale.
|
|||
|
|
WARNING: [XSIM 43-4099] "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/46d7/src/wall_timer.sv" Line 7. Module wall_timer(MODULE_FREQ_HZ=50000000,MS_WIDTH=10) doesn't have a timescale but at least one module in design has a timescale.
|
|||
|
|
WARNING: [XSIM 43-4099] "C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/bd/design_1/ipshared/5b8a/src/uart.sv" Line 11. Module uart(CLOCK_FREQUENCY=50000000,BAUD_RATE=2000000) doesn't have a timescale but at least one module in design has a timescale.
|
|||
|
|
Completed simulation data flow analysis
|
|||
|
|
Time Resolution for simulation is 1ps
|
|||
|
|
Compiling package std.standard
|
|||
|
|
Compiling package std.textio
|
|||
|
|
Compiling package ieee.std_logic_1164
|
|||
|
|
Compiling package ieee.numeric_std
|
|||
|
|
Compiling package ieee.std_logic_arith
|
|||
|
|
Compiling package ieee.std_logic_unsigned
|
|||
|
|
Compiling package synopsys.attributes
|
|||
|
|
Compiling package ieee.std_logic_misc
|
|||
|
|
Compiling package can_v5_1_1.proc_common_pkg
|
|||
|
|
Compiling package can_v5_1_1.ipif_pkg
|
|||
|
|
Compiling package can_v5_1_1.can_ip_pkg
|
|||
|
|
Compiling package xpm.vcomponents
|
|||
|
|
Compiling package unisim.vcomponents
|
|||
|
|
Compiling package ieee.vital_timing
|
|||
|
|
Compiling package ieee.vital_primitives
|
|||
|
|
Compiling package unisim.vpkg
|
|||
|
|
Compiling package xpm.$unit_xpm_cdc_sv_220102727
|
|||
|
|
Compiling package xpm.axi_xil_sb_pkg_xpm_nsu
|
|||
|
|
Compiling package xpm.axi_data_integrity_checker_xpm_n...
|
|||
|
|
Compiling package xpm.xpm_axi_data_integrity_checker_n...
|
|||
|
|
Compiling package xpm.xpm_axi_xil_sb_pkg_nmu
|
|||
|
|
Compiling module xil_defaultlib.m00_couplers_imp_1CA5Z32
|
|||
|
|
Compiling module xil_defaultlib.m01_couplers_imp_I4GRPB
|
|||
|
|
Compiling module xil_defaultlib.s00_couplers_imp_O7FAN0
|
|||
|
|
Compiling module xil_defaultlib.s01_couplers_imp_1F69D31
|
|||
|
|
Compiling module generic_baseblocks_v2_1_1.generic_baseblocks_v2_1_1_mux_en...
|
|||
|
|
Compiling module axi_crossbar_v2_1_30.axi_crossbar_v2_1_30_addr_arbite...
|
|||
|
|
Compiling module generic_baseblocks_v2_1_1.generic_baseblocks_v2_1_1_carry_...
|
|||
|
|
Compiling module generic_baseblocks_v2_1_1.generic_baseblocks_v2_1_1_compar...
|
|||
|
|
Compiling module generic_baseblocks_v2_1_1.generic_baseblocks_v2_1_1_compar...
|
|||
|
|
Compiling module axi_crossbar_v2_1_30.axi_crossbar_v2_1_30_addr_decode...
|
|||
|
|
Compiling module axi_crossbar_v2_1_30.axi_crossbar_v2_1_30_splitter(C_...
|
|||
|
|
Compiling module axi_crossbar_v2_1_30.axi_crossbar_v2_1_30_splitter
|
|||
|
|
Compiling module generic_baseblocks_v2_1_1.generic_baseblocks_v2_1_1_mux_en...
|
|||
|
|
Compiling module generic_baseblocks_v2_1_1.generic_baseblocks_v2_1_1_mux_en...
|
|||
|
|
Compiling module generic_baseblocks_v2_1_1.generic_baseblocks_v2_1_1_mux_en...
|
|||
|
|
Compiling module generic_baseblocks_v2_1_1.generic_baseblocks_v2_1_1_mux_en...
|
|||
|
|
Compiling module axi_register_slice_v2_1_29.axi_register_slice_v2_1_29_axic_...
|
|||
|
|
Compiling module generic_baseblocks_v2_1_1.generic_baseblocks_v2_1_1_mux_en...
|
|||
|
|
Compiling module axi_crossbar_v2_1_30.axi_crossbar_v2_1_30_decerr_slav...
|
|||
|
|
Compiling module axi_crossbar_v2_1_30.axi_crossbar_v2_1_30_crossbar_sa...
|
|||
|
|
Compiling module axi_crossbar_v2_1_30.axi_crossbar_v2_1_30_axi_crossba...
|
|||
|
|
Compiling module xil_defaultlib.design_1_xbar_0
|
|||
|
|
Compiling module xil_defaultlib.design_1_axi_interconnect_0_0
|
|||
|
|
Compiling architecture imp of entity can_v5_1_1.address_decoder [\address_decoder(c_bus_awidth=8,...]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.slave_attachment [\slave_attachment(c_ard_addr_ran...]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.axi_lite_ipif [\axi_lite_ipif(c_s_axi_addr_widt...]
|
|||
|
|
Compiling architecture implementation of entity can_v5_1_1.can_sync_block [\can_sync_block(c_reset_state=1,...]
|
|||
|
|
Compiling architecture fdre_v of entity unisim.FDRE [fdre_default]
|
|||
|
|
Compiling architecture fdr_v of entity unisim.FDR [fdr_default]
|
|||
|
|
Compiling architecture implementation of entity lib_cdc_v1_0_2.cdc_sync [\cdc_sync(c_reset_state=1,c_flop...]
|
|||
|
|
Compiling architecture implementation of entity lib_cdc_v1_0_2.cdc_sync [\cdc_sync(c_reset_state=1,c_sing...]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.CAN_OL_SYNCH [can_ol_synch_default]
|
|||
|
|
Compiling module xpm.xpm_memory_base(MEMORY_SIZE=1638...
|
|||
|
|
Compiling module xpm.xpm_memory_tdpram(MEMORY_SIZE=16...
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.can_tl_arbchk [can_tl_arbchk_default]
|
|||
|
|
Compiling architecture fdce_v of entity unisim.FDCE [fdce_default]
|
|||
|
|
Compiling architecture fdc_v of entity unisim.FDC [fdc_default]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.can_ol_fifopriority [can_ol_fifopriority_default]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.CAN_TXFIFO_CNTL_GEN [\CAN_TXFIFO_CNTL_GEN(c_can_tx_aw...]
|
|||
|
|
Compiling module xpm.xpm_cdc_single(DEST_SYNC_FF=2,IN...
|
|||
|
|
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
|
|||
|
|
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=16...
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.CAN_RXFIFO_CNTL_GEN [\CAN_RXFIFO_CNTL_GEN(c_can_rx_aw...]
|
|||
|
|
Compiling module xpm.xpm_cdc_array_single(DEST_SYNC_F...
|
|||
|
|
Compiling module xpm.xpm_cdc_async_rst(DEST_SYNC_FF=4...
|
|||
|
|
Compiling architecture implementation of entity can_v5_1_1.can_sync_block [\can_sync_block(c_reset_state=1)...]
|
|||
|
|
Compiling architecture implementation of entity lib_cdc_v1_0_2.cdc_sync [\cdc_sync(c_reset_state=1)\]
|
|||
|
|
Compiling architecture implementation of entity lib_cdc_v1_0_2.cdc_sync [\cdc_sync(c_reset_state=1,c_sing...]
|
|||
|
|
Compiling architecture implementation of entity lib_cdc_v1_0_2.cdc_sync [\cdc_sync(c_reset_state=1,c_vect...]
|
|||
|
|
Compiling architecture implementation of entity lib_cdc_v1_0_2.cdc_sync [\cdc_sync(c_reset_state=1,c_flop...]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.CAN_IC_MAIN [can_ic_main_default]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.CAN_OL_TOP [\CAN_OL_TOP(c_can_rx_awidth=4,c_...]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.CAN_TL_ACF [can_tl_acf_default]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.CAN_TL_CLKDIV [can_tl_clkdiv_default]
|
|||
|
|
Compiling architecture implementation of entity lib_cdc_v1_0_2.cdc_sync [\cdc_sync(c_reset_state=1,c_sing...]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.CAN_TL_SYNCH [\CAN_TL_SYNCH(c_can_acf_defined=...]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.CAN_TL_BTL [can_tl_btl_default]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.CAN_TL_OM [can_tl_om_default]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.can_tl_arbit [can_tl_arbit_default]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.CAN_TL_BSP [\CAN_TL_BSP(c_can_acf_defined='1...]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.CAN_TL_TOP [\CAN_TL_TOP(c_can_acf_defined='1...]
|
|||
|
|
Compiling architecture rtl of entity can_v5_1_1.cantop [\cantop(c_can_rx_dpth=16,c_can_t...]
|
|||
|
|
Compiling architecture imp of entity can_v5_1_1.can_top [\can_top(c_can_rx_dpth=16,c_can_...]
|
|||
|
|
Compiling architecture amd of entity can_v5_1_1.can_v5_1_1 [\can_v5_1_1(c_can_rx_dpth=16,c_c...]
|
|||
|
|
Compiling architecture design_1_can_0_2_arch of entity xil_defaultlib.design_1_can_0_2 [design_1_can_0_2_default]
|
|||
|
|
Compiling architecture design_1_can_0_3_arch of entity xil_defaultlib.design_1_can_0_3 [design_1_can_0_3_default]
|
|||
|
|
Compiling module xil_defaultlib.wall_timer(MODULE_FREQ_HZ=500000...
|
|||
|
|
Compiling module xil_defaultlib.can_init(MODE_MSR=32'b010,DELAY_...
|
|||
|
|
Compiling module xil_defaultlib.design_1_can_init_0_0
|
|||
|
|
Compiling module xil_defaultlib.can_rx_parse_axi
|
|||
|
|
Compiling module xil_defaultlib.design_1_can_rx_parse_axi_0_0
|
|||
|
|
Compiling module unisims_ver.IBUF
|
|||
|
|
Compiling module unisims_ver.MMCME2_ADV(CLKFBOUT_MULT_F=20.0,...
|
|||
|
|
Compiling module unisims_ver.BUFG
|
|||
|
|
Compiling module xil_defaultlib.design_1_clk_wiz_0_0_clk_wiz
|
|||
|
|
Compiling module xil_defaultlib.design_1_clk_wiz_0_0
|
|||
|
|
Compiling module unisims_ver.IBUFG
|
|||
|
|
Compiling module xil_defaultlib.ibufg_user
|
|||
|
|
Compiling module xil_defaultlib.design_1_ibufg_user_0_0
|
|||
|
|
Compiling module xil_defaultlib.uart_rx
|
|||
|
|
Compiling module xil_defaultlib.uart_tx
|
|||
|
|
Compiling module xil_defaultlib.uart(CLOCK_FREQUENCY=50000000,BA...
|
|||
|
|
Compiling module blk_mem_gen_v8_4_7.blk_mem_gen_v8_4_7_output_stage(...
|
|||
|
|
Compiling module blk_mem_gen_v8_4_7.blk_mem_gen_v8_4_7_output_stage(...
|
|||
|
|
Compiling module blk_mem_gen_v8_4_7.blk_mem_gen_v8_4_7_softecc_outpu...
|
|||
|
|
Compiling module blk_mem_gen_v8_4_7.blk_mem_gen_v8_4_7_mem_module(C_...
|
|||
|
|
Compiling module blk_mem_gen_v8_4_7.blk_mem_axi_regs_fwd_v8_4(C_DATA...
|
|||
|
|
Compiling module blk_mem_gen_v8_4_7.blk_mem_gen_v8_4_7(C_ELABORATION...
|
|||
|
|
Compiling module xil_defaultlib.blk_mem_gen_0
|
|||
|
|
Compiling module xil_defaultlib.ila_0
|
|||
|
|
Compiling module xil_defaultlib.uart_data_parse_default
|
|||
|
|
Compiling module xil_defaultlib.uart_parse(CLOCK_FREQUENCY=50000...
|
|||
|
|
Compiling module xil_defaultlib.uart_parse_real
|
|||
|
|
Compiling module xil_defaultlib.design_1_uart_parse_real_0_0
|
|||
|
|
Compiling module util_vector_logic_v2_0_3.util_vector_logic_v2_0_3_util_ve...
|
|||
|
|
Compiling module xil_defaultlib.design_1_util_vector_logic_0_0
|
|||
|
|
Compiling module util_vector_logic_v2_0_3.util_vector_logic_v2_0_3_util_ve...
|
|||
|
|
Compiling module xil_defaultlib.design_1_util_vector_logic_0_1
|
|||
|
|
Compiling module xil_defaultlib.design_1
|
|||
|
|
Compiling module xil_defaultlib.design_1_wrapper
|
|||
|
|
Compiling module xil_defaultlib.tb_design_1_wrapper
|
|||
|
|
Compiling module xil_defaultlib.glbl
|
|||
|
|
Built simulation snapshot tb_design_1_wrapper_behav
|
|||
|
|
run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:11 . Memory (MB): peak = 6811.980 ; gain = 0.000
|
|||
|
|
INFO: [USF-XSim-69] 'elaborate' step finished in '11' seconds
|
|||
|
|
INFO: [USF-XSim-4] XSim::Simulate design
|
|||
|
|
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.sim/sim_1/behav/xsim'
|
|||
|
|
INFO: [USF-XSim-98] *** Running xsim
|
|||
|
|
with args "tb_design_1_wrapper_behav -key {Behavioral:sim_1:Functional:tb_design_1_wrapper} -tclbatch {tb_design_1_wrapper.tcl} -protoinst "protoinst_files/design_1.protoinst" -log {simulate.log}"
|
|||
|
|
INFO: [USF-XSim-8] Loading simulator feature
|
|||
|
|
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_1.protoinst
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//axi_interconnect_0/M00_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//axi_interconnect_0/M01_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//axi_interconnect_0/S00_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//axi_interconnect_0/S01_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//axi_interconnect_0/m00_couplers/M_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//axi_interconnect_0/m00_couplers/S_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//axi_interconnect_0/m01_couplers/M_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//axi_interconnect_0/m01_couplers/S_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//axi_interconnect_0/s00_couplers/M_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//axi_interconnect_0/s00_couplers/S_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//axi_interconnect_0/s01_couplers/M_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//axi_interconnect_0/s01_couplers/S_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//axi_interconnect_0/xbar/M00_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//axi_interconnect_0/xbar/M01_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//axi_interconnect_0/xbar/S00_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//axi_interconnect_0/xbar/S01_AXI
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//can_0/CAN_S_AXI_LITE
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//can_1/CAN_S_AXI_LITE
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//can_init_0/m_axi
|
|||
|
|
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//can_rx_parse_axi_0/m_axi
|
|||
|
|
Time resolution is 1 ps
|
|||
|
|
source tb_design_1_wrapper.tcl
|
|||
|
|
# set curr_wave [current_wave_config]
|
|||
|
|
# if { [string length $curr_wave] == 0 } {
|
|||
|
|
# if { [llength [get_objects]] > 0} {
|
|||
|
|
# add_wave /
|
|||
|
|
# set_property needs_save false [current_wave_config]
|
|||
|
|
# } else {
|
|||
|
|
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
|||
|
|
# }
|
|||
|
|
# }
|
|||
|
|
# run 1000ns
|
|||
|
|
Block Memory Generator module tb_design_1_wrapper.u_dut.design_1_i.uart_parse_real_0.inst.u_dut.u_uart_data_parse.your_instance_name.inst.\native_mem_module.blk_mem_gen_v8_4_7_inst is using a behavioral model for simulation which will not precisely model memory collision behavior.
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_0/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/woecctx/memtx/xpm_memory_base_inst/Initial302_26 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_0/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/memrx/xpm_memory_base_inst/Initial302_58 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_1/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/woecctx/memtx/xpm_memory_base_inst/Initial302_26 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_1/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/memrx/xpm_memory_base_inst/Initial302_58 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_design_1_wrapper_behav' loaded.
|
|||
|
|
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
|
|||
|
|
launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 6811.980 ; gain = 0.000
|
|||
|
|
current_wave_config {Untitled 3}
|
|||
|
|
Untitled 3
|
|||
|
|
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/can_0}}
|
|||
|
|
restart
|
|||
|
|
INFO: [Wavedata 42-604] Simulation restarted
|
|||
|
|
run 50 ms
|
|||
|
|
Block Memory Generator module tb_design_1_wrapper.u_dut.design_1_i.uart_parse_real_0.inst.u_dut.u_uart_data_parse.your_instance_name.inst.\native_mem_module.blk_mem_gen_v8_4_7_inst is using a behavioral model for simulation which will not precisely model memory collision behavior.
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_0/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/woecctx/memtx/xpm_memory_base_inst/Initial302_26 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_0/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/memrx/xpm_memory_base_inst/Initial302_58 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_1/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/woecctx/memtx/xpm_memory_base_inst/Initial302_26 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_1/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/memrx/xpm_memory_base_inst/Initial302_58 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
run: Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 6811.980 ; gain = 0.000
|
|||
|
|
current_wave_config {Untitled 3}
|
|||
|
|
Untitled 3
|
|||
|
|
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/can_rx_parse_axi_0}}
|
|||
|
|
restart
|
|||
|
|
INFO: [Wavedata 42-604] Simulation restarted
|
|||
|
|
restart
|
|||
|
|
INFO: [Wavedata 42-604] Simulation restarted
|
|||
|
|
run 50 ms
|
|||
|
|
Block Memory Generator module tb_design_1_wrapper.u_dut.design_1_i.uart_parse_real_0.inst.u_dut.u_uart_data_parse.your_instance_name.inst.\native_mem_module.blk_mem_gen_v8_4_7_inst is using a behavioral model for simulation which will not precisely model memory collision behavior.
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_0/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/woecctx/memtx/xpm_memory_base_inst/Initial302_26 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_0/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/memrx/xpm_memory_base_inst/Initial302_58 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_0.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_1/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/woecctx/memtx/xpm_memory_base_inst/Initial302_26 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.woecctx.memtx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc 0
|
|||
|
|
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/can_1/U0/core_options/cantop_i/CANCORE_LOGIC_I/ol/memrx/xpm_memory_base_inst/Initial302_58 Scope: tb_design_1_wrapper.u_dut.design_1_i.can_1.U0.core_options.cantop_i.CANCORE_LOGIC_I.ol.memrx.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508
|
|||
|
|
run: Time (s): cpu = 00:00:05 ; elapsed = 00:00:11 . Memory (MB): peak = 6811.980 ; gain = 0.000
|
|||
|
|
close_sim
|
|||
|
|
INFO: xsimkernel Simulation Memory Usage: 23796 KB (Peak: 23796 KB), Simulation CPU Usage: 20734 ms
|
|||
|
|
INFO: [Simtcl 6-16] Simulation closed
|
|||
|
|
startgroup
|
|||
|
|
set_property CONFIG.MODE_MSR {0x00000000} [get_bd_cells can_init_0]
|
|||
|
|
endgroup
|
|||
|
|
generate_target all [get_files C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd]
|
|||
|
|
INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_0 clk_wiz propagate
|
|||
|
|
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
|
|||
|
|
Please check your design and connect them as needed:
|
|||
|
|
/can_rx_parse_axi_0/tlm_record_task_id
|
|||
|
|
/can_rx_parse_axi_0/tlm_downlink_task_id
|
|||
|
|
/can_rx_parse_axi_0/tlm_disk_status
|
|||
|
|
/can_rx_parse_axi_0/tlm_cam_dt_status
|
|||
|
|
/can_rx_parse_axi_0/tlm_lvds
|
|||
|
|
/can_rx_parse_axi_0/tlm_reconfig
|
|||
|
|
/can_rx_parse_axi_0/tlm_fpga_temp
|
|||
|
|
/can_rx_parse_axi_0/tlm_compress_flash
|
|||
|
|
|
|||
|
|
Wrote : <C:\proj\pro_finish\can_parse_ctrl\can_parse_ctrl.srcs\sources_1\bd\design_1\design_1.bd>
|
|||
|
|
Verilog Output written to : c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/synth/design_1.v
|
|||
|
|
Verilog Output written to : c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/sim/design_1.v
|
|||
|
|
Verilog Output written to : c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
|
|||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block can_init_0 .
|
|||
|
|
Exporting to file c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh
|
|||
|
|
Generated Hardware Definition File c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/synth/design_1.hwdef
|
|||
|
|
catch { config_ip_cache -export [get_ips -all design_1_can_init_0_0] }
|
|||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_can_init_0_0
|
|||
|
|
INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry 658e51fb9cd9cc02 to dir: c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_init_0_0
|
|||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/ip/2023.2/6/5/658e51fb9cd9cc02/design_1_can_init_0_0.dcp to c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_init_0_0/design_1_can_init_0_0.dcp.
|
|||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_init_0_0/design_1_can_init_0_0.dcp
|
|||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/ip/2023.2/6/5/658e51fb9cd9cc02/design_1_can_init_0_0_sim_netlist.v to c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_init_0_0/design_1_can_init_0_0_sim_netlist.v.
|
|||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_init_0_0/design_1_can_init_0_0_sim_netlist.v
|
|||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/ip/2023.2/6/5/658e51fb9cd9cc02/design_1_can_init_0_0_sim_netlist.vhdl to c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_init_0_0/design_1_can_init_0_0_sim_netlist.vhdl.
|
|||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_init_0_0/design_1_can_init_0_0_sim_netlist.vhdl
|
|||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/ip/2023.2/6/5/658e51fb9cd9cc02/design_1_can_init_0_0_stub.v to c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_init_0_0/design_1_can_init_0_0_stub.v.
|
|||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_init_0_0/design_1_can_init_0_0_stub.v
|
|||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/ip/2023.2/6/5/658e51fb9cd9cc02/design_1_can_init_0_0_stub.vhdl to c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_init_0_0/design_1_can_init_0_0_stub.vhdl.
|
|||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.gen/sources_1/bd/design_1/ip/design_1_can_init_0_0/design_1_can_init_0_0_stub.vhdl
|
|||
|
|
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_can_init_0_0, cache-ID = 658e51fb9cd9cc02; cache size = 36.452 MB.
|
|||
|
|
catch { [ delete_ip_run [get_ips -all design_1_can_init_0_0] ] }
|
|||
|
|
export_ip_user_files -of_objects [get_files C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
|||
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd]
|
|||
|
|
export_simulation -of_objects [get_files C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files -ipstatic_source_dir C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/modelsim} {questa=C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/questa} {riviera=C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/riviera} {activehdl=C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
|||
|
|
reset_run synth_1
|
|||
|
|
INFO: [Project 1-1161] Replacing file C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.srcs/utils_1/imports/synth_1/design_1_wrapper.dcp with file C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.runs/synth_1/design_1_wrapper.dcp
|
|||
|
|
launch_runs impl_1 -to_step write_bitstream -jobs 24
|
|||
|
|
[Wed May 27 14:18:50 2026] Launched synth_1...
|
|||
|
|
Run output will be captured here: C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.runs/synth_1/runme.log
|
|||
|
|
[Wed May 27 14:18:50 2026] Launched impl_1...
|
|||
|
|
Run output will be captured here: C:/proj/pro_finish/can_parse_ctrl/can_parse_ctrl.runs/impl_1/runme.log
|