61 lines
4.8 KiB
Plaintext
61 lines
4.8 KiB
Plaintext
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#-----------------------------------------------------------
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# Vivado v2023.2 (64-bit)
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# SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023
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# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
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# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
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# Start of session at: Tue May 26 23:39:08 2026
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# Process ID: 21364
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# Current directory: E:/proj/proj_521/can_parse_ctrl
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# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent11772 E:\proj\proj_521\can_parse_ctrl\can_parse_ctrl.xpr
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# Log file: E:/proj/proj_521/can_parse_ctrl/vivado.log
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# Journal file: E:/proj/proj_521/can_parse_ctrl\vivado.jou
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# Running On: DESKTOP-UONVKRQ, OS: Windows, CPU Frequency: 2400 MHz, CPU Physical cores: 4, Host memory: 8434 MB
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#-----------------------------------------------------------
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start_gui
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open_project E:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.xpr
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update_compile_order -fileset sources_1
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open_bd_design {E:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd}
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regenerate_bd_layout
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validate_bd_design
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delete_bd_objs [get_bd_intf_nets S00_AXI_1] [get_bd_intf_nets axi_interconnect_0_M00_AXI] [get_bd_intf_nets axi_interconnect_0_M01_AXI] [get_bd_intf_nets S01_AXI_1] [get_bd_cells axi_interconnect_0]
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startgroup
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create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0
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endgroup
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set_property location {6 1239 241} [get_bd_cells smartconnect_0]
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set_property CONFIG.NUM_MI {2} [get_bd_cells smartconnect_0]
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connect_bd_intf_net [get_bd_intf_pins smartconnect_0/S00_AXI] [get_bd_intf_pins can_init_0/m_axi]
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connect_bd_intf_net [get_bd_intf_pins smartconnect_0/S01_AXI] [get_bd_intf_pins can_rx_parse_axi_0/m_axi]
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connect_bd_intf_net [get_bd_intf_pins smartconnect_0/M00_AXI] [get_bd_intf_pins can_0/CAN_S_AXI_LITE]
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connect_bd_intf_net [get_bd_intf_pins smartconnect_0/M01_AXI] [get_bd_intf_pins can_1/CAN_S_AXI_LITE]
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connect_bd_net [get_bd_pins smartconnect_0/aclk] [get_bd_pins ibufg_user_0/clk_out]
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connect_bd_net [get_bd_pins smartconnect_0/aresetn] [get_bd_pins util_vector_logic_1/Res]
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regenerate_bd_layout
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validate_bd_design
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regenerate_bd_layout
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validate_bd_design -force
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generate_target all [get_files E:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd]
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catch { config_ip_cache -export [get_ips -all design_1_can_init_0_0] }
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catch { config_ip_cache -export [get_ips -all design_1_can_rx_parse_axi_0_0] }
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catch { config_ip_cache -export [get_ips -all design_1_uart_parse_real_0_0] }
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catch { config_ip_cache -export [get_ips -all design_1_ibufg_user_0_0] }
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catch { config_ip_cache -export [get_ips -all design_1_clk_wiz_0_0] }
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catch { config_ip_cache -export [get_ips -all design_1_util_vector_logic_0_0] }
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catch { config_ip_cache -export [get_ips -all design_1_util_vector_logic_0_1] }
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catch { config_ip_cache -export [get_ips -all design_1_can_0_2] }
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catch { config_ip_cache -export [get_ips -all design_1_can_0_3] }
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catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_0] }
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export_ip_user_files -of_objects [get_files E:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
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create_ip_run [get_files -of_objects [get_fileset sources_1] E:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd]
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launch_runs design_1_can_0_2_synth_1 design_1_can_0_3_synth_1 design_1_can_init_0_0_synth_1 design_1_can_rx_parse_axi_0_0_synth_1 design_1_clk_wiz_0_0_synth_1 design_1_ibufg_user_0_0_synth_1 design_1_smartconnect_0_0_synth_1 design_1_uart_parse_real_0_0_synth_1 design_1_util_vector_logic_0_0_synth_1 design_1_util_vector_logic_0_1_synth_1 -jobs 8
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wait_on_run design_1_can_0_2_synth_1
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wait_on_run design_1_can_0_3_synth_1
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wait_on_run design_1_can_init_0_0_synth_1
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wait_on_run design_1_can_rx_parse_axi_0_0_synth_1
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wait_on_run design_1_clk_wiz_0_0_synth_1
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wait_on_run design_1_ibufg_user_0_0_synth_1
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wait_on_run design_1_smartconnect_0_0_synth_1
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wait_on_run design_1_uart_parse_real_0_0_synth_1
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wait_on_run design_1_util_vector_logic_0_0_synth_1
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wait_on_run design_1_util_vector_logic_0_1_synth_1
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export_simulation -of_objects [get_files E:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.srcs/sources_1/bd/design_1/design_1.bd] -directory E:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.ip_user_files/sim_scripts -ip_user_files_dir E:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.ip_user_files -ipstatic_source_dir E:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.ip_user_files/ipstatic -lib_map_path [list {modelsim=E:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/modelsim} {questa=E:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/questa} {riviera=E:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/riviera} {activehdl=E:/proj/proj_521/can_parse_ctrl/can_parse_ctrl.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
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