2161 lines
339 KiB
Plaintext
2161 lines
339 KiB
Plaintext
#-----------------------------------------------------------
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# Vivado v2023.2 (64-bit)
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# SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023
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# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
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# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
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# Start of session at: Sat Jul 4 10:43:58 2026
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# Process ID: 21724
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# Current directory: C:/proj/xc7v_ccsds122_datamover_uart
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# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent37844 C:\proj\xc7v_ccsds122_datamover_uart\ccsds122_storage.xpr
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# Log file: C:/proj/xc7v_ccsds122_datamover_uart/vivado.log
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# Journal file: C:/proj/xc7v_ccsds122_datamover_uart\vivado.jou
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# Running On: DESKTOP-EB3SDQ2, OS: Windows, CPU Frequency: 2112 MHz, CPU Physical cores: 16, Host memory: 16817 MB
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#-----------------------------------------------------------
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start_gui
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open_project C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.xpr
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.1 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.1/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.0 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.0/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.1 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.1/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.1 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.1/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
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INFO: [Project 1-313] Project file moved from 'C:/proj/vu440_ccsds122_datamover_uart' since last save.
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Scanning sources...
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Finished scanning sources
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CRITICAL WARNING: [Runs 36-271] Incremental checkpoint part, xcvu440-flga2892-1-c, does not match run part, xc7vx690tffg1761-2.
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INFO: [IP_Flow 19-234] Refreshing IP repositories
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INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/proj/FPGA_DESIGN_IP'.
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INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2023.2/data/ip'.
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WARNING: [filemgmt 56-443] The ECC Algorithm string is empty. Setting the Memory Map to default ECC value to ECC_NONE.
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WARNING: [filemgmt 56-443] The ECC Algorithm string is empty. Setting the Memory Map to default ECC value to ECC_NONE.
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WARNING: [BD 41-1661] One or more IPs have been locked in the design 'design_1.bd'. Please run report_ip_status for more details and recommendations on how to fix this issue.
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List of locked IPs:
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design_1_ccsds122_datamover_0_0
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design_1_ccsds122_axil_slave_0_0
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design_1_ddr3_0_0
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open_project: Time (s): cpu = 00:00:18 ; elapsed = 00:00:10 . Memory (MB): peak = 1800.344 ; gain = 288.750
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update_compile_order -fileset sources_1
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open_bd_design {C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd}
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Reading block design file <C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd>...
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Adding component instance block -- xilinx.com:user:ccsds122_datamover:1.0 - ccsds122_datamover_0
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Adding component instance block -- xilinx.com:ip:smartconnect:1.0 - smartconnect_0
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Adding component instance block -- xilinx.com:user:ccsds122_axil_slave:1.0 - ccsds122_axil_slave_0
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Adding component instance block -- xilinx.com:ip:ila:6.2 - ila_0
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INFO: [xilinx.com:ip:ila:6.2-6] /ila_0: AMD recommends using the System ILA IP in IP Integrator. The System ILA IP is functionally equivalent to an ILA and offers additional benefits in debugging interfaces both within IP Integrator and the Hardware Manager. Consult the Programming and Debug User Guide UG908 for further details.
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Adding component instance block -- xilinx.com:ip:system_ila:1.1 - system_ila_0
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Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - proc_sys_reset_0
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Adding component instance block -- xilinx.com:ip:ddr3:1.4 - ddr3_0
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Adding component instance block -- xilinx.com:ip:util_vector_logic:2.0 - util_vector_logic_0
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Adding component instance block -- xilinx.com:ip:axi_chip2chip:5.0 - axi_chip2chip_0
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Adding component instance block -- xilinx.com:ip:xlconstant:1.1 - xlconstant_0
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Adding component instance block -- xilinx.com:ip:clk_wiz:6.0 - clk_wiz_0
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INFO: [Device 21-403] Loading part xc7vx690tffg1761-2
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Successfully read diagram <design_1> from block design file <C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd>
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open_bd_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 2380.383 ; gain = 580.039
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report_ip_status -name ip_status
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upgrade_ip [get_ips {design_1_ccsds122_datamover_0_0 design_1_ccsds122_axil_slave_0_0}] -log ip_upgrade.log
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Upgrading 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd'
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INFO: [IP_Flow 19-3420] Updated design_1_ccsds122_axil_slave_0_0 to use current project options
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INFO: [IP_Flow 19-3422] Upgraded design_1_ccsds122_datamover_0_0 (ccsds122_datamover_v1_0 1.0) from revision 4 to revision 2
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Wrote : <C:\proj\xc7v_ccsds122_datamover_uart\ccsds122_storage.srcs\sources_1\bd\design_1\design_1.bd>
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INFO: [Coretcl 2-1525] Wrote upgrade log to 'C:/proj/xc7v_ccsds122_datamover_uart/ip_upgrade.log'.
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export_ip_user_files -of_objects [get_ips {design_1_ccsds122_datamover_0_0 design_1_ccsds122_axil_slave_0_0}] -no_script -sync -force -quiet
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report_ip_status -name ip_status
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startgroup
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create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:4.2 mig_7series_0
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endgroup
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set_property location {7 2336 1096} [get_bd_cells mig_7series_0]
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set_property location {5.5 2271 1107} [get_bd_cells mig_7series_0]
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set_property CONFIG.XML_INPUT_FILE {mig_a.prj} [get_bd_cells mig_7series_0]
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set_property CONFIG.RESET_BOARD_INTERFACE {Custom} [get_bd_cells mig_7series_0]
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set_property CONFIG.MIG_DONT_TOUCH_PARAM {Custom} [get_bd_cells mig_7series_0]
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set_property CONFIG.BOARD_MIG_PARAM {Custom} [get_bd_cells mig_7series_0]
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set_property location {5 2037 1123} [get_bd_cells mig_7series_0]
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delete_bd_objs [get_bd_intf_nets smartconnect_0_M00_AXI]
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connect_bd_intf_net [get_bd_intf_pins smartconnect_0/M00_AXI] [get_bd_intf_pins mig_7series_0/S_AXI]
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connect_bd_intf_net [get_bd_intf_pins system_ila_0/SLOT_2_AXI] [get_bd_intf_pins mig_7series_0/S_AXI]
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delete_bd_objs [get_bd_intf_nets aclk_0]
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connect_bd_intf_net [get_bd_intf_ports aclk_0] [get_bd_intf_pins mig_7series_0/SYS_CLK]
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undo
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INFO: [Common 17-17] undo 'connect_bd_intf_net [get_bd_intf_ports aclk_0] [get_bd_intf_pins mig_7series_0/SYS_CLK]'
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undo
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INFO: [Common 17-17] undo 'delete_bd_objs [get_bd_intf_nets aclk_0]'
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delete_bd_objs [get_bd_intf_nets aclk_0]
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connect_bd_intf_net [get_bd_intf_ports aclk_0] [get_bd_intf_pins mig_7series_0/SYS_CLK]
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delete_bd_objs [get_bd_nets util_vector_logic_0_Res]
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connect_bd_net [get_bd_pins util_vector_logic_0/Res] [get_bd_pins mig_7series_0/sys_rst]
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delete_bd_objs [get_bd_intf_nets c0_ddr3]
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set_property location {2362 1077} [get_bd_intf_ports c0_ddr3]
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set_property location {2406 1140} [get_bd_intf_ports c0_ddr3]
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connect_bd_intf_net [get_bd_intf_ports c0_ddr3] [get_bd_intf_pins mig_7series_0/DDR3]
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delete_bd_objs [get_bd_nets ddr3_0_c0_init_calib_complete]
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connect_bd_net [get_bd_pins mig_7series_0/init_calib_complete] [get_bd_pins ila_0/probe0]
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delete_bd_objs [get_bd_nets ddr3_0_c0_ddr3_ui_clk_sync_rst]
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connect_bd_net [get_bd_pins mig_7series_0/ui_clk_sync_rst] [get_bd_pins proc_sys_reset_0/ext_reset_in]
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delete_bd_objs [get_bd_cells ddr3_0]
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connect_bd_net [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins axi_chip2chip_0/m_aclk]
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connect_bd_net [get_bd_pins mig_7series_0/aresetn] [get_bd_pins proc_sys_reset_0/peripheral_aresetn]
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set_property CONFIG.XML_INPUT_FILE {c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/mig_b.prj} [get_bd_cells mig_7series_0]
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INFO: [IP_Flow 19-3484] Absolute path of file 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/mig_b.prj' provided. It will be converted relative to IP Instance files 'mig_b.prj'
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set_property CONFIG.RESET_BOARD_INTERFACE {Custom} [get_bd_cells mig_7series_0]
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set_property CONFIG.MIG_DONT_TOUCH_PARAM {Custom} [get_bd_cells mig_7series_0]
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set_property CONFIG.BOARD_MIG_PARAM {Custom} [get_bd_cells mig_7series_0]
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set_property CONFIG.XML_INPUT_FILE {c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/mig_a.prj} [get_bd_cells mig_7series_0]
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INFO: [IP_Flow 19-3484] Absolute path of file 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/mig_a.prj' provided. It will be converted relative to IP Instance files 'mig_a.prj'
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set_property CONFIG.RESET_BOARD_INTERFACE {Custom} [get_bd_cells mig_7series_0]
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set_property CONFIG.MIG_DONT_TOUCH_PARAM {Custom} [get_bd_cells mig_7series_0]
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set_property CONFIG.BOARD_MIG_PARAM {Custom} [get_bd_cells mig_7series_0]
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delete_bd_objs [get_bd_nets clk_wiz_0_clk_out1]
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connect_bd_net [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins mig_7series_0/clk_ref_i]
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startgroup
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create_bd_cell -type ip -vlnv xilinx.com:user:ccsds_uart_axi:1.0 ccsds_uart_axi_0
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endgroup
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set_property location {3.5 1128 1016} [get_bd_cells ccsds_uart_axi_0]
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delete_bd_objs [get_bd_intf_nets axi_chip2chip_0_m_axi]
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connect_bd_intf_net [get_bd_intf_pins ccsds_uart_axi_0/m_axi] [get_bd_intf_pins smartconnect_0/S02_AXI]
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startgroup
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set_property CONFIG.NUM_SI {4} [get_bd_cells smartconnect_0]
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endgroup
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connect_bd_intf_net [get_bd_intf_pins smartconnect_0/S03_AXI] [get_bd_intf_pins ccsds_uart_axi_0/m_axil]
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delete_bd_objs [get_bd_nets xlconstant_0_dout] [get_bd_nets axi_c2c_selio_tx_clk_out] [get_bd_nets axi_c2c_selio_tx_data_out] [get_bd_nets axi_c2c_selio_rx_clk_in] [get_bd_nets axi_c2c_selio_rx_data_in] [get_bd_nets axi_chip2chip_0_axi_c2c_link_status_out] [get_bd_nets axi_chip2chip_0_axi_c2c_multi_bit_error_out] [get_bd_cells axi_chip2chip_0]
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connect_bd_net [get_bd_pins ccsds_uart_axi_0/clk] [get_bd_pins mig_7series_0/ui_clk]
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connect_bd_net [get_bd_pins ccsds_uart_axi_0/rst_n] [get_bd_pins proc_sys_reset_0/peripheral_aresetn]
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startgroup
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make_bd_pins_external [get_bd_pins ccsds_uart_axi_0/uart_rx_i]
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endgroup
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set_property name uart_rx [get_bd_ports uart_rx_i_0]
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set_property name uart_rx [get_bd_nets uart_rx_i_0_1]
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startgroup
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make_bd_pins_external [get_bd_pins ccsds_uart_axi_0/uart_tx_o]
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endgroup
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set_property name uart_tx [get_bd_nets ccsds_uart_axi_0_uart_tx_o]
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set_property name uart_tx [get_bd_ports uart_tx_o_0]
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delete_bd_objs [get_bd_ports axi_c2c_selio_tx_clk_out] [get_bd_ports axi_c2c_selio_tx_data_out]
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delete_bd_objs [get_bd_ports axi_c2c_selio_rx_clk_in] [get_bd_ports axi_c2c_selio_rx_data_in]
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delete_bd_objs [get_bd_cells xlconstant_0]
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connect_bd_net [get_bd_ports uart_rx] [get_bd_pins ila_0/probe13]
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connect_bd_net [get_bd_pins ila_0/probe14] [get_bd_pins ccsds_uart_axi_0/uart_tx_o]
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startgroup
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set_property CONFIG.C_NUM_MONITOR_SLOTS {5} [get_bd_cells system_ila_0]
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endgroup
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connect_bd_intf_net [get_bd_intf_pins system_ila_0/SLOT_4_AXI] [get_bd_intf_pins ccsds_uart_axi_0/m_axil]
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report_ip_status -name ip_status
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regenerate_bd_layout
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assign_bd_address
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Slave segment '/ccsds122_axil_slave_0/s_axil/reg0' is being assigned into address space '/ccsds_uart_axi_0/m_axi' at <0x0000_0000 [ 2G ]>.
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Slave segment '/ccsds122_axil_slave_0/s_axil/reg0' is being assigned into address space '/ccsds_uart_axi_0/m_axil' at <0x0000_0000 [ 2G ]>.
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Slave segment '/mig_7series_0/memmap/memaddr' is being assigned into address space '/ccsds122_datamover_0/m_axi_mm2s' at <0x8000_0000 [ 1G ]>.
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Slave segment '/mig_7series_0/memmap/memaddr' is being assigned into address space '/ccsds122_datamover_0/m_axi_s2mm' at <0x8000_0000 [ 1G ]>.
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Slave segment '/mig_7series_0/memmap/memaddr' is being assigned into address space '/ccsds_uart_axi_0/m_axi' at <0x8000_0000 [ 1G ]>.
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Slave segment '/mig_7series_0/memmap/memaddr' is being assigned into address space '/ccsds_uart_axi_0/m_axil' at <0x8000_0000 [ 1G ]>.
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validate_bd_design
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INFO: [BD 5-943] Reserving offset range <0x8000_0000 [ 1G ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
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INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
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INFO: [BD 5-943] Reserving offset range <0x8000_0000 [ 1G ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
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INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
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INFO: [BD 5-943] Reserving offset range <0x8000_0000 [ 1G ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
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INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
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INFO: [BD 5-943] Reserving offset range <0x8000_0000 [ 1G ]> from slave interface '/smartconnect_0/S03_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
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INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S03_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
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INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_1: SmartConnect design_1_smartconnect_0_1 is in High-performance Mode.
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xit::source_ipfile: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 3123.492 ; gain = 80.547
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INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_0 clk_wiz propagate
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WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /mig_7series_0/S_AXI(0) and /smartconnect_0/M00_AXI(4)
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WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /mig_7series_0/S_AXI(0) and /smartconnect_0/M00_AXI(4)
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validate_bd_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 3253.957 ; gain = 211.012
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startgroup
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exclude_bd_addr_seg [get_bd_addr_segs ccsds122_datamover_0/m_axi_mm2s/SEG_mig_7series_0_memaddr]
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Excluding slave segment /mig_7series_0/memmap/memaddr from address space /ccsds122_datamover_0/m_axi_mm2s.
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exclude_bd_addr_seg [get_bd_addr_segs ccsds122_datamover_0/m_axi_s2mm/SEG_mig_7series_0_memaddr]
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Excluding slave segment /mig_7series_0/memmap/memaddr from address space /ccsds122_datamover_0/m_axi_s2mm.
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exclude_bd_addr_seg [get_bd_addr_segs ccsds_uart_axi_0/m_axi/SEG_mig_7series_0_memaddr]
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Excluding slave segment /mig_7series_0/memmap/memaddr from address space /ccsds_uart_axi_0/m_axi.
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exclude_bd_addr_seg [get_bd_addr_segs ccsds_uart_axi_0/m_axil/SEG_mig_7series_0_memaddr]
|
|
Excluding slave segment /mig_7series_0/memmap/memaddr from address space /ccsds_uart_axi_0/m_axil.
|
|
endgroup
|
|
startgroup
|
|
include_bd_addr_seg [get_bd_addr_segs -excluded ccsds122_datamover_0/m_axi_mm2s/SEG_mig_7series_0_memaddr]
|
|
Including slave segment </mig_7series_0/memmap/memaddr> into address space </ccsds122_datamover_0/m_axi_mm2s>.
|
|
endgroup
|
|
set_property offset 0x80000000 [get_bd_addr_segs {ccsds122_datamover_0/m_axi_mm2s/SEG_mig_7series_0_memaddr}]
|
|
set_property offset 0 [get_bd_addr_segs {ccsds122_datamover_0/m_axi_mm2s/SEG_mig_7series_0_memaddr}]
|
|
set_property range 2G [get_bd_addr_segs {ccsds122_datamover_0/m_axi_mm2s/SEG_mig_7series_0_memaddr}]
|
|
startgroup
|
|
include_bd_addr_seg [get_bd_addr_segs -excluded ccsds122_datamover_0/m_axi_s2mm/SEG_mig_7series_0_memaddr]
|
|
Including slave segment </mig_7series_0/memmap/memaddr> into address space </ccsds122_datamover_0/m_axi_s2mm>.
|
|
endgroup
|
|
set_property offset 0 [get_bd_addr_segs {ccsds122_datamover_0/m_axi_s2mm/SEG_mig_7series_0_memaddr}]
|
|
set_property range 2G [get_bd_addr_segs {ccsds122_datamover_0/m_axi_s2mm/SEG_mig_7series_0_memaddr}]
|
|
startgroup
|
|
include_bd_addr_seg [get_bd_addr_segs -excluded ccsds_uart_axi_0/m_axi/SEG_mig_7series_0_memaddr]
|
|
Including slave segment </mig_7series_0/memmap/memaddr> into address space </ccsds_uart_axi_0/m_axi>.
|
|
endgroup
|
|
set_property offset 0x80000000 [get_bd_addr_segs {ccsds_uart_axi_0/m_axi/SEG_mig_7series_0_memaddr}]
|
|
set_property range 64K [get_bd_addr_segs {ccsds_uart_axi_0/m_axi/SEG_ccsds122_axil_slave_0_reg0}]
|
|
set_property offset 0xFFFF0000 [get_bd_addr_segs {ccsds122_datamover_0/m_axi_mm2s/SEG_ccsds122_axil_slave_0_reg0}]
|
|
set_property offset 0xFFFF0000 [get_bd_addr_segs {ccsds_uart_axi_0/m_axi/SEG_ccsds122_axil_slave_0_reg0}]
|
|
set_property range 64K [get_bd_addr_segs {ccsds_uart_axi_0/m_axil/SEG_ccsds122_axil_slave_0_reg0}]
|
|
set_property offset 0xFFFF0000 [get_bd_addr_segs {ccsds_uart_axi_0/m_axil/SEG_ccsds122_axil_slave_0_reg0}]
|
|
startgroup
|
|
include_bd_addr_seg [get_bd_addr_segs -excluded ccsds_uart_axi_0/m_axil/SEG_mig_7series_0_memaddr]
|
|
Including slave segment </mig_7series_0/memmap/memaddr> into address space </ccsds_uart_axi_0/m_axil>.
|
|
endgroup
|
|
set_property offset 0 [get_bd_addr_segs {ccsds_uart_axi_0/m_axil/SEG_mig_7series_0_memaddr}]
|
|
set_property range 2G [get_bd_addr_segs {ccsds_uart_axi_0/m_axil/SEG_mig_7series_0_memaddr}]
|
|
report_ip_status -name ip_status
|
|
save_bd_design
|
|
Wrote : <C:\proj\xc7v_ccsds122_datamover_uart\ccsds122_storage.srcs\sources_1\bd\design_1\design_1.bd>
|
|
Wrote : <C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
|
|
set_property offset 0 [get_bd_addr_segs {ccsds_uart_axi_0/m_axi/SEG_mig_7series_0_memaddr}]
|
|
set_property range 2G [get_bd_addr_segs {ccsds_uart_axi_0/m_axi/SEG_mig_7series_0_memaddr}]
|
|
save_bd_design
|
|
Wrote : <C:\proj\xc7v_ccsds122_datamover_uart\ccsds122_storage.srcs\sources_1\bd\design_1\design_1.bd>
|
|
regenerate_bd_layout
|
|
validate_bd_design
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S03_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S03_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_1: SmartConnect design_1_smartconnect_0_1 is in High-performance Mode.
|
|
xit::source_ipfile: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 3363.309 ; gain = 0.074
|
|
INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_0 clk_wiz propagate
|
|
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /mig_7series_0/S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
|
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /mig_7series_0/S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
|
validate_bd_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 3363.367 ; gain = 15.164
|
|
report_ip_status -name ip_status
|
|
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
|
INFO: [BD 41-1662] The design 'design_1.bd' is already validated. Therefore parameter propagation will not be re-run.
|
|
Wrote : <C:\proj\xc7v_ccsds122_datamover_uart\ccsds122_storage.srcs\sources_1\bd\design_1\design_1.bd>
|
|
Wrote : <C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/sim/design_1.v
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
|
|
INFO: [IP_Flow 19-3420] Updated fifo_generator_0 to use current project options
|
|
INFO: [IP_Flow 19-3420] Updated ila_1 to use current project options
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block ccsds122_datamover_0 .
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/hw_handoff/design_1_smartconnect_0_1.hwh
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/synth/design_1_smartconnect_0_1.hwdef
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block smartconnect_0 .
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block ccsds122_axil_slave_0 .
|
|
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ila_0_0/design_1_ila_0_0_ooc.xdc'
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block ila_0 .
|
|
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_ooc.xdc'
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/hw_handoff/design_1_system_ila_0_0.hwh
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/synth/design_1_system_ila_0_0.hwdef
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block system_ila_0 .
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_0 .
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_vector_logic_0 .
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_wiz_0 .
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block mig_7series_0 .
|
|
INFO: [IP_Flow 19-3420] Updated ila_0 to use current project options
|
|
INFO: [IP_Flow 19-3420] Updated vio_0 to use current project options
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block ccsds_uart_axi_0 .
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.hwdef
|
|
generate_target: Time (s): cpu = 00:00:54 ; elapsed = 00:00:58 . Memory (MB): peak = 3763.094 ; gain = 397.738
|
|
catch { config_ip_cache -export [get_ips -all design_1_ccsds122_datamover_0_0] }
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds122_datamover_0_0
|
|
catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_smartconnect_0_1
|
|
catch { config_ip_cache -export [get_ips -all design_1_ccsds122_axil_slave_0_0] }
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds122_axil_slave_0_0
|
|
catch { config_ip_cache -export [get_ips -all design_1_ila_0_0] }
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ila_0_0
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_system_ila_0_0
|
|
catch { config_ip_cache -export [get_ips -all design_1_proc_sys_reset_0_0] }
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_proc_sys_reset_0_0
|
|
catch { config_ip_cache -export [get_ips -all design_1_util_vector_logic_0_3] }
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_util_vector_logic_0_3
|
|
catch { config_ip_cache -export [get_ips -all design_1_clk_wiz_0_0] }
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_clk_wiz_0_0
|
|
catch { config_ip_cache -export [get_ips -all design_1_ccsds_uart_axi_0_0] }
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds_uart_axi_0_0
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
|
launch_runs design_1_ccsds122_axil_slave_0_0_synth_1 design_1_ccsds122_datamover_0_0_synth_1 design_1_ccsds_uart_axi_0_0_synth_1 design_1_clk_wiz_0_0_synth_1 design_1_ila_0_0_synth_1 design_1_mig_7series_0_0_synth_1 design_1_proc_sys_reset_0_0_synth_1 design_1_smartconnect_0_1_synth_1 design_1_system_ila_0_0_synth_1 design_1_util_vector_logic_0_3_synth_1 -jobs 24
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds122_axil_slave_0_0
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds122_datamover_0_0
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds_uart_axi_0_0
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_clk_wiz_0_0
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ila_0_0
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_proc_sys_reset_0_0
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_smartconnect_0_1
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_system_ila_0_0
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_util_vector_logic_0_3
|
|
[Sat Jul 4 11:26:34 2026] Launched design_1_ccsds122_axil_slave_0_0_synth_1, design_1_ccsds122_datamover_0_0_synth_1, design_1_ccsds_uart_axi_0_0_synth_1, design_1_clk_wiz_0_0_synth_1, design_1_ila_0_0_synth_1, design_1_mig_7series_0_0_synth_1, design_1_proc_sys_reset_0_0_synth_1, design_1_smartconnect_0_1_synth_1, design_1_system_ila_0_0_synth_1, design_1_util_vector_logic_0_3_synth_1...
|
|
Run output will be captured here:
|
|
design_1_ccsds122_axil_slave_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ccsds122_axil_slave_0_0_synth_1/runme.log
|
|
design_1_ccsds122_datamover_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ccsds122_datamover_0_0_synth_1/runme.log
|
|
design_1_ccsds_uart_axi_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ccsds_uart_axi_0_0_synth_1/runme.log
|
|
design_1_clk_wiz_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_clk_wiz_0_0_synth_1/runme.log
|
|
design_1_ila_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ila_0_0_synth_1/runme.log
|
|
design_1_mig_7series_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_mig_7series_0_0_synth_1/runme.log
|
|
design_1_proc_sys_reset_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_proc_sys_reset_0_0_synth_1/runme.log
|
|
design_1_smartconnect_0_1_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_smartconnect_0_1_synth_1/runme.log
|
|
design_1_system_ila_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_system_ila_0_0_synth_1/runme.log
|
|
design_1_util_vector_logic_0_3_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_util_vector_logic_0_3_synth_1/runme.log
|
|
export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
|
report_ip_status -name ip_status
|
|
reset_run synth_1
|
|
INFO: [Project 1-1161] Replacing file C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/utils_1/imports/synth_1/design_1_wrapper.dcp with file C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/design_1_wrapper.dcp
|
|
WARNING: [Vivado 12-1017] Problems encountered:
|
|
1. Failed to delete one or more files in run directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1
|
|
|
|
launch_runs impl_1_copy_2 -to_step write_bitstream -jobs 24
|
|
INFO: [IP_Flow 19-6930] IPCACHE: runCacheChecks() number of threads = 8
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_ccsds122_axil_slave_0_0
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_ccsds122_datamover_0_0
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_ccsds_uart_axi_0_0
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_clk_wiz_0_0
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_ila_0_0
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_proc_sys_reset_0_0
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_smartconnect_0_1
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_system_ila_0_0
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_util_vector_logic_0_3
|
|
INFO: [IP_Flow 19-8020] IPCACHE: runCacheChecks() calling threadPool finishWork()
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds122_axil_slave_0_0
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds122_datamover_0_0
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds_uart_axi_0_0
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_clk_wiz_0_0
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ila_0_0
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_proc_sys_reset_0_0
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_smartconnect_0_1
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_system_ila_0_0
|
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INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_util_vector_logic_0_3
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[Sat Jul 4 11:27:56 2026] Launched design_1_ccsds122_datamover_0_0_synth_1, design_1_smartconnect_0_1_synth_1, design_1_ccsds122_axil_slave_0_0_synth_1, design_1_ila_0_0_synth_1, design_1_system_ila_0_0_synth_1, design_1_proc_sys_reset_0_0_synth_1, design_1_util_vector_logic_0_3_synth_1, design_1_clk_wiz_0_0_synth_1, design_1_mig_7series_0_0_synth_1, design_1_ccsds_uart_axi_0_0_synth_1, synth_1...
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Run output will be captured here:
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design_1_ccsds122_datamover_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ccsds122_datamover_0_0_synth_1/runme.log
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design_1_smartconnect_0_1_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_smartconnect_0_1_synth_1/runme.log
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design_1_ccsds122_axil_slave_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ccsds122_axil_slave_0_0_synth_1/runme.log
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design_1_ila_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ila_0_0_synth_1/runme.log
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design_1_system_ila_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_system_ila_0_0_synth_1/runme.log
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design_1_proc_sys_reset_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_proc_sys_reset_0_0_synth_1/runme.log
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design_1_util_vector_logic_0_3_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_util_vector_logic_0_3_synth_1/runme.log
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design_1_clk_wiz_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_clk_wiz_0_0_synth_1/runme.log
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design_1_mig_7series_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_mig_7series_0_0_synth_1/runme.log
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design_1_ccsds_uart_axi_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ccsds_uart_axi_0_0_synth_1/runme.log
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synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/runme.log
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[Sat Jul 4 11:27:56 2026] Launched impl_1_copy_2...
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Run output will be captured here: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/impl_1_copy_2/runme.log
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launch_runs: Time (s): cpu = 00:00:03 ; elapsed = 00:00:11 . Memory (MB): peak = 4127.094 ; gain = 17.211
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open_run impl_1_copy_2
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Netlist sorting complete. Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 4588.441 ; gain = 58.012
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INFO: [Netlist 29-17] Analyzing 12884 Unisim elements for replacement
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INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds
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INFO: [Project 1-479] Netlist was created with Vivado 2023.2
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INFO: [Project 1-570] Preparing netlist for logic optimization
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WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'design_1_i/clk_wiz_0/clk_in1' is not directly connected to top level port. 'IBUF_LOW_PWR' is ignored for synthesis but preserved for implementation.
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Read ShapeDB Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.720 . Memory (MB): peak = 5100.145 ; gain = 83.266
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INFO: [Timing 38-478] Restoring timing data from binary archive.
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INFO: [Timing 38-479] Binary timing data restore complete.
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INFO: [Project 1-856] Restoring constraints from binary archive.
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INFO: [Project 1-853] Binary constraint restore complete.
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INFO: [Designutils 20-5722] Start Reading Physical Databases.
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Reading placement.
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Read Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.226 . Memory (MB): peak = 6468.359 ; gain = 0.000
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Reading placer database...
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Read Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 6468.359 ; gain = 0.000
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Read PlaceDB: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 6660.230 ; gain = 191.871
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Read PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6660.230 ; gain = 0.000
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Reading routing.
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Read RouteStorage: Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 6735.691 ; gain = 75.461
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Read Physdb Files: Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 6735.691 ; gain = 267.332
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Restored from archive | CPU: 12.000000 secs | Memory: 0.000000 MB |
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Finished XDEF File Restore: Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 6735.691 ; gain = 267.332
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.062 . Memory (MB): peak = 6735.691 ; gain = 0.000
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INFO: [Project 1-111] Unisim Transformation Summary:
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A total of 3765 instances were transformed.
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CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 1904 instances
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IOBUFDS_DIFF_OUT_DCIEN => IOBUFDS_DIFF_OUT_DCIEN (IBUFDS_IBUFDISABLE_INT(x2), INV, OBUFTDS_DCIEN(x2)): 8 instances
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IOBUF_DCIEN => IOBUF_DCIEN (IBUF_IBUFDISABLE, OBUFT_DCIEN): 64 instances
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LUT6_2 => LUT6_2 (LUT5, LUT6): 19 instances
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OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance
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RAM16X1D => RAM32X1D (RAMD32(x2)): 12 instances
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RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 1719 instances
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RAM32X1D => RAM32X1D (RAMD32(x2)): 38 instances
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open_run: Time (s): cpu = 00:01:13 ; elapsed = 00:01:09 . Memory (MB): peak = 7649.504 ; gain = 3418.672
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open_report: Time (s): cpu = 00:00:17 ; elapsed = 00:00:08 . Memory (MB): peak = 7805.613 ; gain = 127.992
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CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
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WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
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open_bd_design {C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd}
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startgroup
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set_property -dict [list \
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CONFIG.CLKOUT1_JITTER {114.829} \
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CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {200.000} \
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CONFIG.MMCM_CLKOUT0_DIVIDE_F {5.000} \
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] [get_bd_cells clk_wiz_0]
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endgroup
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startgroup
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endgroup
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undo
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INFO: [Common 17-17] undo 'endgroup'
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INFO: [Common 17-17] undo 'startgroup'
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undo
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INFO: [Common 17-17] undo 'endgroup'
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INFO: [Common 17-17] undo 'set_property -dict [list \
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CONFIG.CLKOUT1_JITTER {114.829} \
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CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {200.000} \
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CONFIG.MMCM_CLKOUT0_DIVIDE_F {5.000} \
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] [get_bd_cells clk_wiz_0]'
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INFO: [Common 17-17] undo 'startgroup'
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startgroup
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set_property -dict [list \
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CONFIG.CLKOUT1_JITTER {114.829} \
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CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {200.000} \
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CONFIG.MMCM_CLKOUT0_DIVIDE_F {5.000} \
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] [get_bd_cells clk_wiz_0]
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endgroup
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regenerate_bd_layout
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validate_bd_design
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INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
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INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
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INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
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INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
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INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
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INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
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INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S03_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
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INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S03_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
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INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_1: SmartConnect design_1_smartconnect_0_1 is in High-performance Mode.
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xit::source_ipfile: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 8376.258 ; gain = 0.000
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INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_0 clk_wiz propagate
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WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /mig_7series_0/S_AXI(0) and /smartconnect_0/M00_AXI(4)
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WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /mig_7series_0/S_AXI(0) and /smartconnect_0/M00_AXI(4)
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validate_bd_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 8376.258 ; gain = 0.000
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generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
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INFO: [BD 41-1662] The design 'design_1.bd' is already validated. Therefore parameter propagation will not be re-run.
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Wrote : <C:\proj\xc7v_ccsds122_datamover_uart\ccsds122_storage.srcs\sources_1\bd\design_1\design_1.bd>
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Wrote : <C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
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Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
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Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/sim/design_1.v
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Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
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Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/hw_handoff/design_1_smartconnect_0_1.hwh
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Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/synth/design_1_smartconnect_0_1.hwdef
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INFO: [BD 41-1029] Generation completed for the IP Integrator block smartconnect_0 .
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WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_ooc.xdc'
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Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/hw_handoff/design_1_system_ila_0_0.hwh
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Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/synth/design_1_system_ila_0_0.hwdef
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INFO: [BD 41-1029] Generation completed for the IP Integrator block system_ila_0 .
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INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_wiz_0 .
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Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh
|
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Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.hwdef
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generate_target: Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 8376.258 ; gain = 0.000
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catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
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INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_smartconnect_0_1
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INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry 7f92233783f5e392 to dir: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1
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INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/f/7f92233783f5e392/design_1_smartconnect_0_1.dcp to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1.dcp.
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INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1.dcp
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INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/f/7f92233783f5e392/design_1_smartconnect_0_1_sim_netlist.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.v.
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INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.v
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INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/f/7f92233783f5e392/design_1_smartconnect_0_1_sim_netlist.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.vhdl.
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INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.vhdl
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INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/f/7f92233783f5e392/design_1_smartconnect_0_1_stub.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.v.
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INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.v
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INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/f/7f92233783f5e392/design_1_smartconnect_0_1_stub.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.vhdl.
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INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.vhdl
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INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_smartconnect_0_1, cache-ID = 7f92233783f5e392; cache size = 3280.062 MB.
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config_ip_cache: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 8404.277 ; gain = 28.020
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catch { [ delete_ip_run [get_ips -all design_1_smartconnect_0_1] ] }
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catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
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INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_system_ila_0_0
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INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry fcd979ae904f59e5 to dir: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0
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INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/f/c/fcd979ae904f59e5/design_1_system_ila_0_0.dcp to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0.dcp.
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INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0.dcp
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INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/f/c/fcd979ae904f59e5/design_1_system_ila_0_0_sim_netlist.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_sim_netlist.v.
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INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_sim_netlist.v
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INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/f/c/fcd979ae904f59e5/design_1_system_ila_0_0_sim_netlist.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_sim_netlist.vhdl.
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INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_sim_netlist.vhdl
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INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/f/c/fcd979ae904f59e5/design_1_system_ila_0_0_stub.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_stub.v.
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INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_stub.v
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INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/f/c/fcd979ae904f59e5/design_1_system_ila_0_0_stub.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_stub.vhdl.
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INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_stub.vhdl
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INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_system_ila_0_0, cache-ID = fcd979ae904f59e5; cache size = 3280.062 MB.
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config_ip_cache: Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 8404.277 ; gain = 0.000
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catch { [ delete_ip_run [get_ips -all design_1_system_ila_0_0] ] }
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catch { config_ip_cache -export [get_ips -all design_1_clk_wiz_0_0] }
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INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_clk_wiz_0_0
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export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
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create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
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launch_runs design_1_clk_wiz_0_0_synth_1 design_1_mig_7series_0_0_synth_1 -jobs 24
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INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_clk_wiz_0_0
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[Sat Jul 4 12:20:35 2026] Launched design_1_clk_wiz_0_0_synth_1, design_1_mig_7series_0_0_synth_1...
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Run output will be captured here:
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design_1_clk_wiz_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_clk_wiz_0_0_synth_1/runme.log
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design_1_mig_7series_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_mig_7series_0_0_synth_1/runme.log
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export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
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reset_run synth_1
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INFO: [Project 1-1161] Replacing file C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/utils_1/imports/synth_1/design_1_wrapper.dcp with file C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/design_1_wrapper.dcp
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WARNING: [Vivado 12-1017] Problems encountered:
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1. Failed to delete one or more files in run directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1
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launch_runs impl_1_copy_2 -to_step write_bitstream -jobs 24
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INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_clk_wiz_0_0
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[Sat Jul 4 12:21:03 2026] Launched design_1_clk_wiz_0_0_synth_1, design_1_mig_7series_0_0_synth_1, synth_1...
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Run output will be captured here:
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design_1_clk_wiz_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_clk_wiz_0_0_synth_1/runme.log
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design_1_mig_7series_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_mig_7series_0_0_synth_1/runme.log
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synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/runme.log
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[Sat Jul 4 12:21:03 2026] Launched impl_1_copy_2...
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Run output will be captured here: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/impl_1_copy_2/runme.log
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set_property CONFIG.XML_INPUT_FILE {c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/mig_b.prj} [get_bd_cells mig_7series_0]
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INFO: [IP_Flow 19-3484] Absolute path of file 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/mig_b.prj' provided. It will be converted relative to IP Instance files 'mig_b.prj'
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set_property CONFIG.RESET_BOARD_INTERFACE {Custom} [get_bd_cells mig_7series_0]
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set_property CONFIG.MIG_DONT_TOUCH_PARAM {Custom} [get_bd_cells mig_7series_0]
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set_property CONFIG.BOARD_MIG_PARAM {Custom} [get_bd_cells mig_7series_0]
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generate_target all [get_files c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0.xci]
|
|
ERROR: [Vivado 12-3563] The Nested sub-design 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0.xci' can only be generated by its parent sub-design.
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save_bd_design
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Wrote : <C:\proj\xc7v_ccsds122_datamover_uart\ccsds122_storage.srcs\sources_1\bd\design_1\design_1.bd>
|
|
Wrote : <C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
|
|
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
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INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S03_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S03_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_1: SmartConnect design_1_smartconnect_0_1 is in High-performance Mode.
|
|
xit::source_ipfile: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 8452.875 ; gain = 0.000
|
|
INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_0 clk_wiz propagate
|
|
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /mig_7series_0/S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
|
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /mig_7series_0/S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
|
Wrote : <C:\proj\xc7v_ccsds122_datamover_uart\ccsds122_storage.srcs\sources_1\bd\design_1\design_1.bd>
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/sim/design_1.v
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/hw_handoff/design_1_smartconnect_0_1.hwh
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/synth/design_1_smartconnect_0_1.hwdef
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block smartconnect_0 .
|
|
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_ooc.xdc'
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/hw_handoff/design_1_system_ila_0_0.hwh
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/synth/design_1_system_ila_0_0.hwdef
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block system_ila_0 .
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block mig_7series_0 .
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.hwdef
|
|
generate_target: Time (s): cpu = 00:00:55 ; elapsed = 00:00:58 . Memory (MB): peak = 8734.125 ; gain = 299.059
|
|
catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_smartconnect_0_1
|
|
INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry 7f92233783f5e392 to dir: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/f/7f92233783f5e392/design_1_smartconnect_0_1.dcp to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1.dcp.
|
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INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1.dcp
|
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INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/f/7f92233783f5e392/design_1_smartconnect_0_1_sim_netlist.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.v.
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INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.v
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/f/7f92233783f5e392/design_1_smartconnect_0_1_sim_netlist.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.vhdl.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.vhdl
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/f/7f92233783f5e392/design_1_smartconnect_0_1_stub.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.v.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.v
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/f/7f92233783f5e392/design_1_smartconnect_0_1_stub.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.vhdl.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.vhdl
|
|
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_smartconnect_0_1, cache-ID = 7f92233783f5e392; cache size = 3280.128 MB.
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_system_ila_0_0
|
|
INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry fcd979ae904f59e5 to dir: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/f/c/fcd979ae904f59e5/design_1_system_ila_0_0.dcp to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0.dcp.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0.dcp
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/f/c/fcd979ae904f59e5/design_1_system_ila_0_0_sim_netlist.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_sim_netlist.v.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_sim_netlist.v
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/f/c/fcd979ae904f59e5/design_1_system_ila_0_0_sim_netlist.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_sim_netlist.vhdl.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_sim_netlist.vhdl
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/f/c/fcd979ae904f59e5/design_1_system_ila_0_0_stub.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_stub.v.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_stub.v
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/f/c/fcd979ae904f59e5/design_1_system_ila_0_0_stub.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_stub.vhdl.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_stub.vhdl
|
|
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_system_ila_0_0, cache-ID = fcd979ae904f59e5; cache size = 3280.128 MB.
|
|
config_ip_cache: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 8806.906 ; gain = 0.000
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
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create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
|
launch_runs design_1_mig_7series_0_0_synth_1 -jobs 24
|
|
[Sat Jul 4 12:24:54 2026] Launched design_1_mig_7series_0_0_synth_1...
|
|
Run output will be captured here: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_mig_7series_0_0_synth_1/runme.log
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export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
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reset_run synth_1
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launch_runs impl_1_copy_2 -to_step write_bitstream -jobs 24
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[Sat Jul 4 12:25:21 2026] Launched design_1_mig_7series_0_0_synth_1, synth_1...
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Run output will be captured here:
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design_1_mig_7series_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_mig_7series_0_0_synth_1/runme.log
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synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/runme.log
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[Sat Jul 4 12:25:22 2026] Launched impl_1_copy_2...
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Run output will be captured here: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/impl_1_copy_2/runme.log
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open_run synth_1 -name synth_1
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Design is defaulting to impl run constrset: constrs_1
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Design is defaulting to synth run part: xc7vx690tffg1761-2
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INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_axil_slave_0_0/design_1_ccsds122_axil_slave_0_0.dcp' for cell 'design_1_i/ccsds122_axil_slave_0'
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INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/design_1_ccsds122_datamover_0_0.dcp' for cell 'design_1_i/ccsds122_datamover_0'
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INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/design_1_ccsds_uart_axi_0_0.dcp' for cell 'design_1_i/ccsds_uart_axi_0'
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INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.dcp' for cell 'design_1_i/clk_wiz_0'
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INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ila_0_0/design_1_ila_0_0.dcp' for cell 'design_1_i/ila_0'
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INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0.dcp' for cell 'design_1_i/mig_7series_0'
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INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0.dcp' for cell 'design_1_i/proc_sys_reset_0'
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INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1.dcp' for cell 'design_1_i/smartconnect_0'
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INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0.dcp' for cell 'design_1_i/system_ila_0'
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INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_3/design_1_util_vector_logic_0_3.dcp' for cell 'design_1_i/util_vector_logic_0'
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Netlist sorting complete. Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 9432.441 ; gain = 59.387
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INFO: [Netlist 29-17] Analyzing 12909 Unisim elements for replacement
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INFO: [Netlist 29-28] Unisim Transformation completed in 5 CPU seconds
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INFO: [Project 1-479] Netlist was created with Vivado 2023.2
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INFO: [Project 1-570] Preparing netlist for logic optimization
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WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. design_1_i/clk_wiz_0/inst/clkin1_ibufg
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Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
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WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'design_1_i/clk_wiz_0/clk_in1' is not directly connected to top level port. 'IBUF_LOW_PWR' is ignored for synthesis but preserved for implementation.
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INFO: [Chipscope 16-324] Core: design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl/u_ila_1 UUID: 9c1f4e79-feb5-532b-8648-e7237e71eda8
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INFO: [Chipscope 16-324] Core: design_1_i/ccsds_uart_axi_0/inst/u_core/u_ila UUID: 224cb1a1-1f43-5694-9b06-fc581d8cbbfe
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INFO: [Chipscope 16-324] Core: design_1_i/ccsds_uart_axi_0/inst/u_core/u_vio_soft_rst UUID: 62b2038d-2768-5030-a5ac-9430fcab7cee
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INFO: [Chipscope 16-324] Core: design_1_i/ila_0 UUID: be177176-557e-59fe-ace2-fe04795a2b22
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INFO: [Chipscope 16-324] Core: design_1_i/system_ila_0/inst/ila_lib UUID: cd4c83c8-23a6-596d-99ad-09be1335c6b0
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/axi_datamover_0/axi_datamover_0.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_datamover/U0'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/axi_datamover_0/axi_datamover_0.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_datamover/U0'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/fifo_generator_0/fifo_generator_0.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_bubble_removal/u_pack_fifo/U0'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/fifo_generator_0/fifo_generator_0.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_bubble_removal/u_pack_fifo/U0'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl/u_ila_1/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl/u_ila_1/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl/u_ila_1/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl/u_ila_1/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_1/bd_886d_psr_aclk_0_board.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_1/bd_886d_psr_aclk_0_board.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_1/bd_886d_psr_aclk_0.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_1/bd_886d_psr_aclk_0.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s00_nodes/s00_ar_node/inst'
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:49]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:52]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:55]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:59]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:63]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:66]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:70]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:73]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:76]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:79]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:85]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:88]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:91]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:94]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:97]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:100]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:104]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:107]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:110]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:113]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:116]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:119]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-13' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:122]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:125]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:128]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-13' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:131]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:134]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:137]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:140]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:143]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:146]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:149]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:152]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:155]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:161]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:164]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:167]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:171]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:174]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:178]
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s00_nodes/s00_ar_node/inst'
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|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst'
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:49]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:52]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:55]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:59]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:63]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:66]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:70]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:73]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:76]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:79]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:82]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:85]
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:88]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:91]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:94]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:97]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:100]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:104]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:107]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:110]
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:113]
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:116]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:119]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-13' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:122]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:125]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:128]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-13' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:131]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:134]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:137]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:140]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:143]
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:146]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:149]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:152]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:155]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:158]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:161]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:164]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:167]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:171]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:174]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:178]
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst'
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc:49]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc:52]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc:55]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc:59]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc:63]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc:66]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc:70]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc:73]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc:76]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc:79]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc:85]
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INFO: [Common 17-14] Message 'Vivado 12-180' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc:88]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc:88]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc:91]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc:94]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc:97]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc:100]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc:104]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc:107]
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INFO: [Common 17-14] Message 'Vivado_Tcl 4-921' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc:107]
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_18/bd_886d_swn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_18/bd_886d_swn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sbn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sbn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_24/bd_886d_sarn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_ar_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_24/bd_886d_sarn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_ar_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_25/bd_886d_srn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_r_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_25/bd_886d_srn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_r_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_26/bd_886d_sawn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_aw_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_26/bd_886d_sawn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_aw_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_27/bd_886d_swn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_w_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_27/bd_886d_swn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_w_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_28/bd_886d_sbn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_b_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_28/bd_886d_sbn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_b_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_33/bd_886d_sarn_2_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s03_nodes/s03_ar_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_33/bd_886d_sarn_2_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s03_nodes/s03_ar_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_34/bd_886d_srn_2_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s03_nodes/s03_r_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_34/bd_886d_srn_2_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s03_nodes/s03_r_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_35/bd_886d_sawn_2_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s03_nodes/s03_aw_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_35/bd_886d_sawn_2_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s03_nodes/s03_aw_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_36/bd_886d_swn_2_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s03_nodes/s03_w_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_36/bd_886d_swn_2_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s03_nodes/s03_w_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_37/bd_886d_sbn_2_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s03_nodes/s03_b_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_37/bd_886d_sbn_2_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s03_nodes/s03_b_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_39/bd_886d_m00arn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_39/bd_886d_m00arn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_40/bd_886d_m00rn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_40/bd_886d_m00rn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_41/bd_886d_m00awn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_41/bd_886d_m00awn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_42/bd_886d_m00wn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_42/bd_886d_m00wn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_43/bd_886d_m00bn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_43/bd_886d_m00bn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_46/bd_886d_m01arn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_ar_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_46/bd_886d_m01arn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_ar_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_47/bd_886d_m01rn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_r_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_47/bd_886d_m01rn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_r_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_48/bd_886d_m01awn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_aw_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_48/bd_886d_m01awn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_aw_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_49/bd_886d_m01wn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_w_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_49/bd_886d_m01wn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_w_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_50/bd_886d_m01bn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_b_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_50/bd_886d_m01bn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_b_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/smartconnect.xdc] for cell 'design_1_i/smartconnect_0/inst'
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WARNING: [Vivado_Tcl 4-919] Waiver ID 'CDC-1' -from list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/smartconnect.xdc:1]
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/smartconnect.xdc] for cell 'design_1_i/smartconnect_0/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ila_0_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/ila_0/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ila_0_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/ila_0/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ila_0_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/ila_0/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ila_0_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/ila_0/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/system_ila_0/inst/ila_lib/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/system_ila_0/inst/ila_lib/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/system_ila_0/inst/ila_lib/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/system_ila_0/inst/ila_lib/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0_board.xdc] for cell 'design_1_i/proc_sys_reset_0/U0'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0_board.xdc] for cell 'design_1_i/proc_sys_reset_0/U0'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0.xdc] for cell 'design_1_i/proc_sys_reset_0/U0'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0.xdc] for cell 'design_1_i/proc_sys_reset_0/U0'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_board.xdc] for cell 'design_1_i/clk_wiz_0/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_board.xdc] for cell 'design_1_i/clk_wiz_0/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xdc] for cell 'design_1_i/clk_wiz_0/inst'
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INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xdc:54]
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INFO: [Timing 38-2] Deriving generated clocks [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xdc:54]
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xdc] for cell 'design_1_i/clk_wiz_0/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/constraints/design_1_mig_7series_0_0.xdc] for cell 'design_1_i/mig_7series_0'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/constraints/design_1_mig_7series_0_0.xdc] for cell 'design_1_i/mig_7series_0'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/src/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/ccsds_uart_axi_0/inst/u_core/u_ila/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/src/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/ccsds_uart_axi_0/inst/u_core/u_ila/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/src/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/ccsds_uart_axi_0/inst/u_core/u_ila/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/src/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/ccsds_uart_axi_0/inst/u_core/u_ila/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/src/vio_0/vio_0.xdc] for cell 'design_1_i/ccsds_uart_axi_0/inst/u_core/u_vio_soft_rst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/src/vio_0/vio_0.xdc] for cell 'design_1_i/ccsds_uart_axi_0/inst/u_core/u_vio_soft_rst'
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Parsing XDC File [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/constrs_1/new/ccsds122_storage.xdc]
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CRITICAL WARNING: [Vivado 12-1411] Cannot set LOC property of ports, Terminal aclk_0_clk_p cannot be placed on E19 (IOB_X1Y426) because the pad is already occupied by terminal c0_ddr3_ck_p[0] possibly due to user constraint [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/constrs_1/new/ccsds122_storage.xdc:1]
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CRITICAL WARNING: [Vivado 12-1411] Cannot set LOC property of ports, Terminal aclk_0_clk_p cannot be placed on E19 (IOB_X1Y426) because the pad is already occupied by terminal c0_ddr3_ck_p[0] possibly due to user constraint [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/constrs_1/new/ccsds122_storage.xdc:2]
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CRITICAL WARNING: [Common 17-69] Command failed: Invalid I/O Standard 'DIFF_SSTL18' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/constrs_1/new/ccsds122_storage.xdc:3]
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Finished Parsing XDC File [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/constrs_1/new/ccsds122_storage.xdc]
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/axi_datamover_0/axi_datamover_0_clocks.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_datamover/U0'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/axi_datamover_0/axi_datamover_0_clocks.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_datamover/U0'
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INFO: [Project 1-1714] 329 XPM XDC files have been applied to the design.
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INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
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INFO: [Project 1-1687] 1077 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design.
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.072 . Memory (MB): peak = 10625.270 ; gain = 0.000
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INFO: [Project 1-111] Unisim Transformation Summary:
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A total of 3769 instances were transformed.
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CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 1904 instances
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IOBUFDS_DIFF_OUT_DCIEN => IOBUFDS_DIFF_OUT_DCIEN (IBUFDS_IBUFDISABLE_INT(x2), INV, OBUFTDS_DCIEN(x2)): 8 instances
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IOBUF_DCIEN => IOBUF_DCIEN (IBUF_IBUFDISABLE, OBUFT_DCIEN): 64 instances
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LUT6_2 => LUT6_2 (LUT5, LUT6): 28 instances
|
|
OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance
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RAM16X1D => RAM32X1D (RAMD32(x2)): 12 instances
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|
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 1714 instances
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RAM32X1D => RAM32X1D (RAMD32(x2)): 38 instances
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open_run: Time (s): cpu = 00:01:59 ; elapsed = 00:01:43 . Memory (MB): peak = 10625.270 ; gain = 1818.363
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open_bd_design {C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd}
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reset_run impl_1_copy_2
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delete_bd_objs [get_bd_intf_nets aclk_0_1] [get_bd_intf_ports aclk_0]
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startgroup
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make_bd_intf_pins_external [get_bd_intf_pins mig_7series_0/SYS_CLK]
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endgroup
|
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regenerate_bd_layout
|
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undo
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INFO: [Common 17-17] undo 'regenerate_bd_layout'
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undo
|
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INFO: [Common 17-17] undo 'endgroup'
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|
INFO: [Common 17-17] undo 'make_bd_intf_pins_external [get_bd_intf_pins mig_7series_0/SYS_CLK]'
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INFO: [Common 17-17] undo 'startgroup'
|
|
undo
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INFO: [Common 17-17] undo 'delete_bd_objs [get_bd_intf_nets aclk_0_1] [get_bd_intf_ports aclk_0]'
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regenerate_bd_layout
|
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regenerate_bd_layout
|
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validate_bd_design
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INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
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INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
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INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
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INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
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INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
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INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
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INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S03_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
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INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S03_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
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INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_1: SmartConnect design_1_smartconnect_0_1 is in High-performance Mode.
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xit::source_ipfile: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 10625.270 ; gain = 0.000
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|
INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_0 clk_wiz propagate
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|
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /mig_7series_0/S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
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WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /mig_7series_0/S_AXI(0) and /smartconnect_0/M00_AXI(4)
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validate_bd_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 10625.270 ; gain = 0.000
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|
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
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INFO: [BD 41-1662] The design 'design_1.bd' is already validated. Therefore parameter propagation will not be re-run.
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|
Wrote : <C:\proj\xc7v_ccsds122_datamover_uart\ccsds122_storage.srcs\sources_1\bd\design_1\design_1.bd>
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Wrote : <C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
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Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/sim/design_1.v
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Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
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Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/hw_handoff/design_1_smartconnect_0_1.hwh
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Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/synth/design_1_smartconnect_0_1.hwdef
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INFO: [BD 41-1029] Generation completed for the IP Integrator block smartconnect_0 .
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WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_ooc.xdc'
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Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/hw_handoff/design_1_system_ila_0_0.hwh
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Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/synth/design_1_system_ila_0_0.hwdef
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INFO: [BD 41-1029] Generation completed for the IP Integrator block system_ila_0 .
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Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh
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Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.hwdef
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generate_target: Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 10625.270 ; gain = 0.000
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catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
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INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_smartconnect_0_1
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INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry 7f92233783f5e392 to dir: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1
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INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/f/7f92233783f5e392/design_1_smartconnect_0_1.dcp to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1.dcp.
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INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1.dcp
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INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/f/7f92233783f5e392/design_1_smartconnect_0_1_sim_netlist.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.v.
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INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.v
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INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/f/7f92233783f5e392/design_1_smartconnect_0_1_sim_netlist.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.vhdl.
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INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.vhdl
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INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/f/7f92233783f5e392/design_1_smartconnect_0_1_stub.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.v.
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INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.v
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INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/f/7f92233783f5e392/design_1_smartconnect_0_1_stub.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.vhdl.
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INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.vhdl
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INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_smartconnect_0_1, cache-ID = 7f92233783f5e392; cache size = 3280.128 MB.
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|
config_ip_cache: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 10625.270 ; gain = 0.000
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catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
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|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_system_ila_0_0
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|
INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry fcd979ae904f59e5 to dir: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0
|
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INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/f/c/fcd979ae904f59e5/design_1_system_ila_0_0.dcp to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0.dcp.
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INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0.dcp
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INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/f/c/fcd979ae904f59e5/design_1_system_ila_0_0_sim_netlist.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_sim_netlist.v.
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INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_sim_netlist.v
|
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INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/f/c/fcd979ae904f59e5/design_1_system_ila_0_0_sim_netlist.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_sim_netlist.vhdl.
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INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_sim_netlist.vhdl
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INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/f/c/fcd979ae904f59e5/design_1_system_ila_0_0_stub.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_stub.v.
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INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_stub.v
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INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/f/c/fcd979ae904f59e5/design_1_system_ila_0_0_stub.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_stub.vhdl.
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|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_stub.vhdl
|
|
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_system_ila_0_0, cache-ID = fcd979ae904f59e5; cache size = 3280.128 MB.
|
|
config_ip_cache: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 10625.270 ; gain = 0.000
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export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
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|
export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
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generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
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INFO: [BD 41-1637] Generated targets are already up-to-date for block design 'design_1' - hence not re-generating.
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export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
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create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
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|
export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
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|
reset_run synth_1
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INFO: [Project 1-1161] Replacing file C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/utils_1/imports/synth_1/design_1_wrapper.dcp with file C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/design_1_wrapper.dcp
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launch_runs impl_1_copy_2 -to_step write_bitstream -jobs 24
|
|
WARNING: [Project 1-478] Design 'synth_1' is stale and will not be used when launching 'impl_1_copy_2'
|
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[Sat Jul 4 12:58:56 2026] Launched synth_1...
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Run output will be captured here: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/runme.log
|
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[Sat Jul 4 12:58:56 2026] Launched impl_1_copy_2...
|
|
Run output will be captured here: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/impl_1_copy_2/runme.log
|
|
report_ip_status -name ip_status
|
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set_property CONFIG.XML_INPUT_FILE {c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/mig_a.prj} [get_bd_cells mig_7series_0]
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INFO: [IP_Flow 19-3484] Absolute path of file 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/mig_a.prj' provided. It will be converted relative to IP Instance files 'mig_a.prj'
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WARNING: [BD 41-1684] Pin /mig_7series_0/clk_ref_i is now disabled. All connections to this pin have been removed.
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set_property CONFIG.RESET_BOARD_INTERFACE {Custom} [get_bd_cells mig_7series_0]
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set_property CONFIG.MIG_DONT_TOUCH_PARAM {Custom} [get_bd_cells mig_7series_0]
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set_property CONFIG.BOARD_MIG_PARAM {Custom} [get_bd_cells mig_7series_0]
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delete_bd_objs [get_bd_nets clk_wiz_0_clk_out1]
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generate_target all [get_files c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0.xci]
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|
ERROR: [Vivado 12-3563] The Nested sub-design 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0.xci' can only be generated by its parent sub-design.
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set_property CONFIG.XML_INPUT_FILE {c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/mig_b.prj} [get_bd_cells mig_7series_0]
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|
INFO: [IP_Flow 19-3484] Absolute path of file 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/mig_b.prj' provided. It will be converted relative to IP Instance files 'mig_b.prj'
|
|
set_property CONFIG.RESET_BOARD_INTERFACE {Custom} [get_bd_cells mig_7series_0]
|
|
set_property CONFIG.MIG_DONT_TOUCH_PARAM {Custom} [get_bd_cells mig_7series_0]
|
|
set_property CONFIG.BOARD_MIG_PARAM {Custom} [get_bd_cells mig_7series_0]
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generate_target all [get_files c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0.xci]
|
|
ERROR: [Vivado 12-3563] The Nested sub-design 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0.xci' can only be generated by its parent sub-design.
|
|
regenerate_bd_layout
|
|
validate_bd_design
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S03_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S03_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_1: SmartConnect design_1_smartconnect_0_1 is in High-performance Mode.
|
|
xit::source_ipfile: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 10883.359 ; gain = 9.219
|
|
INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_0 clk_wiz propagate
|
|
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /mig_7series_0/S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
|
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /mig_7series_0/S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
|
validate_bd_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 10894.340 ; gain = 42.914
|
|
regenerate_bd_layout
|
|
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
|
INFO: [BD 41-1662] The design 'design_1.bd' is already validated. Therefore parameter propagation will not be re-run.
|
|
Wrote : <C:\proj\xc7v_ccsds122_datamover_uart\ccsds122_storage.srcs\sources_1\bd\design_1\design_1.bd>
|
|
Wrote : <C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/sim/design_1.v
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/hw_handoff/design_1_smartconnect_0_1.hwh
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/synth/design_1_smartconnect_0_1.hwdef
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block smartconnect_0 .
|
|
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_ooc.xdc'
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/hw_handoff/design_1_system_ila_0_0.hwh
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/synth/design_1_system_ila_0_0.hwdef
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block system_ila_0 .
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block mig_7series_0 .
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.hwdef
|
|
generate_target: Time (s): cpu = 00:00:35 ; elapsed = 00:00:37 . Memory (MB): peak = 11208.910 ; gain = 314.570
|
|
catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_smartconnect_0_1
|
|
INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry 7f92233783f5e392 to dir: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/f/7f92233783f5e392/design_1_smartconnect_0_1.dcp to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1.dcp.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1.dcp
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/f/7f92233783f5e392/design_1_smartconnect_0_1_sim_netlist.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.v.
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|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.v
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/f/7f92233783f5e392/design_1_smartconnect_0_1_sim_netlist.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.vhdl.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.vhdl
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/f/7f92233783f5e392/design_1_smartconnect_0_1_stub.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.v.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.v
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/f/7f92233783f5e392/design_1_smartconnect_0_1_stub.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.vhdl.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.vhdl
|
|
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_smartconnect_0_1, cache-ID = 7f92233783f5e392; cache size = 3280.128 MB.
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_system_ila_0_0
|
|
INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry fcd979ae904f59e5 to dir: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/f/c/fcd979ae904f59e5/design_1_system_ila_0_0.dcp to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0.dcp.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0.dcp
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/f/c/fcd979ae904f59e5/design_1_system_ila_0_0_sim_netlist.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_sim_netlist.v.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_sim_netlist.v
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/f/c/fcd979ae904f59e5/design_1_system_ila_0_0_sim_netlist.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_sim_netlist.vhdl.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_sim_netlist.vhdl
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/f/c/fcd979ae904f59e5/design_1_system_ila_0_0_stub.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_stub.v.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_stub.v
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/f/c/fcd979ae904f59e5/design_1_system_ila_0_0_stub.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_stub.vhdl.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_stub.vhdl
|
|
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_system_ila_0_0, cache-ID = fcd979ae904f59e5; cache size = 3280.128 MB.
|
|
config_ip_cache: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 11281.555 ; gain = 0.000
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
|
launch_runs design_1_mig_7series_0_0_synth_1 -jobs 24
|
|
[Sat Jul 4 14:25:09 2026] Launched design_1_mig_7series_0_0_synth_1...
|
|
Run output will be captured here: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_mig_7series_0_0_synth_1/runme.log
|
|
export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
|
delete_bd_objs [get_bd_nets proc_sys_reset_0_peripheral_reset] [get_bd_cells clk_wiz_0]
|
|
undo
|
|
INFO: [Common 17-17] undo 'delete_bd_objs [get_bd_nets proc_sys_reset_0_peripheral_reset] [get_bd_cells clk_wiz_0]'
|
|
startgroup
|
|
create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_1
|
|
endgroup
|
|
set_property CONFIG.PRIM_SOURCE {Differential_clock_capable_pin} [get_bd_cells clk_wiz_1]
|
|
delete_bd_objs [get_bd_cells clk_wiz_1]
|
|
startgroup
|
|
create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 util_ds_buf_0
|
|
endgroup
|
|
delete_bd_objs [get_bd_intf_nets aclk_0_1]
|
|
connect_bd_intf_net [get_bd_intf_ports aclk_0] [get_bd_intf_pins util_ds_buf_0/CLK_IN_D]
|
|
set_property CONFIG.XML_INPUT_FILE {c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/mig_a.prj} [get_bd_cells mig_7series_0]
|
|
INFO: [IP_Flow 19-3484] Absolute path of file 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/mig_a.prj' provided. It will be converted relative to IP Instance files 'mig_a.prj'
|
|
set_property CONFIG.RESET_BOARD_INTERFACE {Custom} [get_bd_cells mig_7series_0]
|
|
set_property CONFIG.MIG_DONT_TOUCH_PARAM {Custom} [get_bd_cells mig_7series_0]
|
|
set_property CONFIG.BOARD_MIG_PARAM {Custom} [get_bd_cells mig_7series_0]
|
|
connect_bd_net [get_bd_pins util_ds_buf_0/IBUF_OUT] [get_bd_pins mig_7series_0/sys_clk_i]
|
|
startgroup
|
|
create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_1
|
|
endgroup
|
|
connect_bd_net [get_bd_pins clk_wiz_1/clk_in1] [get_bd_pins util_ds_buf_0/IBUF_OUT]
|
|
connect_bd_net [get_bd_ports sys_rst_n] [get_bd_pins clk_wiz_1/reset]
|
|
undo
|
|
INFO: [Common 17-17] undo 'connect_bd_net [get_bd_ports sys_rst_n] [get_bd_pins clk_wiz_1/reset]'
|
|
connect_bd_net [get_bd_pins clk_wiz_1/reset] [get_bd_pins util_vector_logic_0/Res]
|
|
delete_bd_objs [get_bd_nets proc_sys_reset_0_peripheral_reset] [get_bd_cells clk_wiz_0]
|
|
undo
|
|
INFO: [Common 17-17] undo 'delete_bd_objs [get_bd_nets proc_sys_reset_0_peripheral_reset] [get_bd_cells clk_wiz_0]'
|
|
delete_bd_objs [get_bd_nets proc_sys_reset_0_peripheral_reset] [get_bd_cells clk_wiz_0]
|
|
delete_bd_objs [get_bd_nets ddr3_0_c0_ddr3_ui_clk]
|
|
connect_bd_net [get_bd_pins ila_0/clk] [get_bd_pins clk_wiz_1/clk_out1]
|
|
connect_bd_net [get_bd_pins system_ila_0/clk] [get_bd_pins clk_wiz_1/clk_out1]
|
|
connect_bd_net [get_bd_pins ccsds_uart_axi_0/clk] [get_bd_pins mig_7series_0/ui_clk]
|
|
connect_bd_net [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins smartconnect_0/aclk]
|
|
connect_bd_net [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins ccsds122_axil_slave_0/clk]
|
|
connect_bd_net [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk]
|
|
connect_bd_net [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins ccsds122_datamover_0/clk]
|
|
regenerate_bd_layout
|
|
validate_bd_design
|
|
ERROR: [BD 41-758] The following clock pins are not connected to a valid clock source:
|
|
/ccsds122_datamover_0/m_axi_mm2s_aclk
|
|
/ccsds122_datamover_0/m_axis_mm2s_cmdsts_aclk
|
|
/ccsds122_datamover_0/m_axi_s2mm_aclk
|
|
|
|
ERROR: [Common 17-39] 'validate_bd_design' failed due to earlier errors.
|
|
connect_bd_net [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins ccsds122_datamover_0/m_axi_mm2s_aclk]
|
|
connect_bd_net [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins ccsds122_datamover_0/m_axis_mm2s_cmdsts_aclk]
|
|
connect_bd_net [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins ccsds122_datamover_0/m_axi_s2mm_aclk]
|
|
connect_bd_net [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins ccsds122_datamover_0/m_axis_s2mm_cmdsts_awclk]
|
|
regenerate_bd_layout
|
|
validate_bd_design
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S03_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S03_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_1: SmartConnect design_1_smartconnect_0_1 is in High-performance Mode.
|
|
xit::source_ipfile: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 11429.367 ; gain = 16.547
|
|
CRITICAL WARNING: [BD 41-1343] Reset pin /system_ila_0/resetn (associated clock /system_ila_0/clk) is connected to reset source /proc_sys_reset_0/peripheral_aresetn (synchronous to clock source /mig_7series_0/ui_clk).
|
|
This may prevent design from meeting timing. Please add Processor System Reset module to create a reset that is synchronous to the associated clock source /clk_wiz_1/clk_out1.
|
|
INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_1 clk_wiz propagate
|
|
ERROR: [BD 41-237] Bus Interface property CLK_DOMAIN does not match between /system_ila_0/SLOT_0_AXI(/clk_wiz_1_clk_out1) and /ccsds122_datamover_0/m_axi_mm2s(design_1_mig_7series_0_0_ui_clk)
|
|
ERROR: [BD 41-237] Bus Interface property CLK_DOMAIN does not match between /system_ila_0/SLOT_1_AXI(/clk_wiz_1_clk_out1) and /ccsds122_datamover_0/m_axi_s2mm(design_1_mig_7series_0_0_ui_clk)
|
|
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /mig_7series_0/S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
|
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /mig_7series_0/S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
|
ERROR: [BD 41-237] Bus Interface property CLK_DOMAIN does not match between /system_ila_0/SLOT_2_AXI(/clk_wiz_1_clk_out1) and /smartconnect_0/M00_AXI(design_1_mig_7series_0_0_ui_clk)
|
|
ERROR: [BD 41-237] Bus Interface property CLK_DOMAIN does not match between /system_ila_0/SLOT_3_AXI(/clk_wiz_1_clk_out1) and /smartconnect_0/M01_AXI(design_1_mig_7series_0_0_ui_clk)
|
|
ERROR: [BD 41-237] Bus Interface property CLK_DOMAIN does not match between /system_ila_0/SLOT_4_AXI(/clk_wiz_1_clk_out1) and /ccsds_uart_axi_0/m_axil(design_1_mig_7series_0_0_ui_clk)
|
|
validate_bd_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 11442.285 ; gain = 43.457
|
|
ERROR: [Common 17-39] 'validate_bd_design' failed due to earlier errors.
|
|
undo
|
|
INFO: [Common 17-17] undo 'regenerate_bd_layout'
|
|
undo
|
|
INFO: [Common 17-17] undo 'connect_bd_net [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins ccsds122_datamover_0/m_axis_s2mm_cmdsts_awclk]'
|
|
undo
|
|
INFO: [Common 17-17] undo 'connect_bd_net [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins ccsds122_datamover_0/m_axi_s2mm_aclk]'
|
|
undo
|
|
INFO: [Common 17-17] undo 'connect_bd_net [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins ccsds122_datamover_0/m_axis_mm2s_cmdsts_aclk]'
|
|
undo
|
|
INFO: [Common 17-17] undo 'connect_bd_net [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins ccsds122_datamover_0/m_axi_mm2s_aclk]'
|
|
undo
|
|
INFO: [Common 17-17] undo 'regenerate_bd_layout'
|
|
undo
|
|
INFO: [Common 17-17] undo 'connect_bd_net [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins ccsds122_datamover_0/clk]'
|
|
undo
|
|
INFO: [Common 17-17] undo 'connect_bd_net [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk]'
|
|
undo
|
|
INFO: [Common 17-17] undo 'connect_bd_net [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins ccsds122_axil_slave_0/clk]'
|
|
undo
|
|
INFO: [Common 17-17] undo 'connect_bd_net [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins smartconnect_0/aclk]'
|
|
undo
|
|
INFO: [Common 17-17] undo 'connect_bd_net [get_bd_pins ccsds_uart_axi_0/clk] [get_bd_pins mig_7series_0/ui_clk]'
|
|
undo
|
|
INFO: [Common 17-17] undo 'connect_bd_net [get_bd_pins system_ila_0/clk] [get_bd_pins clk_wiz_1/clk_out1]'
|
|
undo
|
|
INFO: [Common 17-17] undo 'connect_bd_net [get_bd_pins ila_0/clk] [get_bd_pins clk_wiz_1/clk_out1]'
|
|
undo
|
|
INFO: [Common 17-17] undo 'delete_bd_objs [get_bd_nets ddr3_0_c0_ddr3_ui_clk]'
|
|
delete_bd_objs [get_bd_nets mig_7series_0_init_calib_complete]
|
|
delete_bd_objs [get_bd_nets uart_tx]
|
|
undo
|
|
INFO: [Common 17-17] undo 'delete_bd_objs [get_bd_nets uart_tx]'
|
|
delete_bd_objs [get_bd_nets ccsds122_datamover_0_compress_done_valid]
|
|
connect_bd_net [get_bd_pins ccsds122_datamover_0/compress_done_valid] [get_bd_pins ila_0/probe0]
|
|
startgroup
|
|
create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.2 ila_1
|
|
INFO: [xilinx.com:ip:ila:6.2-6] /ila_1: AMD recommends using the System ILA IP in IP Integrator. The System ILA IP is functionally equivalent to an ILA and offers additional benefits in debugging interfaces both within IP Integrator and the Hardware Manager. Consult the Programming and Debug User Guide UG908 for further details.
|
|
endgroup
|
|
WARNING: [IP_Flow 19-4067] Ignoring invalid widget type specified checkbox.Providing a default widget
|
|
set_property -dict [list \
|
|
CONFIG.C_MONITOR_TYPE {Native} \
|
|
CONFIG.C_NUM_OF_PROBES {2} \
|
|
] [get_bd_cells ila_1]
|
|
set_property location {3 952 137} [get_bd_cells ccsds122_datamover_0]
|
|
connect_bd_net [get_bd_pins ila_1/clk] [get_bd_pins clk_wiz_1/clk_out1]
|
|
connect_bd_net [get_bd_pins ila_1/probe0] [get_bd_pins mig_7series_0/init_calib_complete]
|
|
connect_bd_net [get_bd_pins mig_7series_0/mmcm_locked] [get_bd_pins ila_1/probe1]
|
|
WARNING: [IP_Flow 19-4067] Ignoring invalid widget type specified checkbox.Providing a default widget
|
|
startgroup
|
|
set_property CONFIG.C_NUM_OF_PROBES {3} [get_bd_cells ila_1]
|
|
endgroup
|
|
connect_bd_net [get_bd_pins ila_1/probe2] [get_bd_pins mig_7series_0/ui_clk_sync_rst]
|
|
regenerate_bd_layout
|
|
validate_bd_design
|
|
ERROR: [Common 17-161] Invalid option value '' specified for 'object'.
|
|
ERROR: [BD 41-1273] Error running propagate TCL procedure: ERROR: [Common 17-161] Invalid option value '' specified for 'object'.
|
|
::xilinx.com_ip_ila_6.2::propagate Line 95
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S03_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S03_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_1: SmartConnect design_1_smartconnect_0_1 is in High-performance Mode.
|
|
xit::source_ipfile: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 11514.770 ; gain = 0.000
|
|
INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_1 clk_wiz propagate
|
|
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /mig_7series_0/S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
|
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /mig_7series_0/S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
|
validate_bd_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 11527.695 ; gain = 27.918
|
|
ERROR: [Common 17-39] 'validate_bd_design' failed due to earlier errors.
|
|
WARNING: [IP_Flow 19-4067] Ignoring invalid widget type specified checkbox.Providing a default widget
|
|
startgroup
|
|
set_property CONFIG.C_NUM_OF_PROBES {25} [get_bd_cells ila_0]
|
|
endgroup
|
|
regenerate_bd_layout
|
|
validate_bd_design
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S03_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S03_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_1: SmartConnect design_1_smartconnect_0_1 is in High-performance Mode.
|
|
xit::source_ipfile: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 11574.574 ; gain = 0.004
|
|
INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_1 clk_wiz propagate
|
|
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /mig_7series_0/S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
|
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /mig_7series_0/S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
|
validate_bd_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 11586.496 ; gain = 34.582
|
|
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
|
INFO: [BD 41-1662] The design 'design_1.bd' is already validated. Therefore parameter propagation will not be re-run.
|
|
Wrote : <C:\proj\xc7v_ccsds122_datamover_uart\ccsds122_storage.srcs\sources_1\bd\design_1\design_1.bd>
|
|
Wrote : <C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/sim/design_1.v
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/hw_handoff/design_1_smartconnect_0_1.hwh
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/synth/design_1_smartconnect_0_1.hwdef
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INFO: [BD 41-1029] Generation completed for the IP Integrator block smartconnect_0 .
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WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ila_0_0/design_1_ila_0_0_ooc.xdc'
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INFO: [BD 41-1029] Generation completed for the IP Integrator block ila_0 .
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WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_ooc.xdc'
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Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/hw_handoff/design_1_system_ila_0_0.hwh
|
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Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/synth/design_1_system_ila_0_0.hwdef
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INFO: [BD 41-1029] Generation completed for the IP Integrator block system_ila_0 .
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block mig_7series_0 .
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INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ds_buf_0 .
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INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_wiz_1 .
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WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ila_1_0/design_1_ila_1_0_ooc.xdc'
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INFO: [BD 41-1029] Generation completed for the IP Integrator block ila_1 .
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Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh
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Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.hwdef
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generate_target: Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 11891.848 ; gain = 305.352
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catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
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INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_smartconnect_0_1
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INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry 7f92233783f5e392 to dir: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1
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INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/f/7f92233783f5e392/design_1_smartconnect_0_1.dcp to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1.dcp.
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INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1.dcp
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INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/f/7f92233783f5e392/design_1_smartconnect_0_1_sim_netlist.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.v.
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INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.v
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INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/f/7f92233783f5e392/design_1_smartconnect_0_1_sim_netlist.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.vhdl.
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INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.vhdl
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INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/f/7f92233783f5e392/design_1_smartconnect_0_1_stub.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.v.
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INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.v
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/f/7f92233783f5e392/design_1_smartconnect_0_1_stub.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.vhdl.
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|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.vhdl
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INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_smartconnect_0_1, cache-ID = 7f92233783f5e392; cache size = 3280.128 MB.
|
|
catch { config_ip_cache -export [get_ips -all design_1_ila_0_0] }
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ila_0_0
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_system_ila_0_0
|
|
INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry fcd979ae904f59e5 to dir: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/f/c/fcd979ae904f59e5/design_1_system_ila_0_0.dcp to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0.dcp.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0.dcp
|
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INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/f/c/fcd979ae904f59e5/design_1_system_ila_0_0_sim_netlist.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_sim_netlist.v.
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INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_sim_netlist.v
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/f/c/fcd979ae904f59e5/design_1_system_ila_0_0_sim_netlist.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_sim_netlist.vhdl.
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|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_sim_netlist.vhdl
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|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/f/c/fcd979ae904f59e5/design_1_system_ila_0_0_stub.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_stub.v.
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|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_stub.v
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/f/c/fcd979ae904f59e5/design_1_system_ila_0_0_stub.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_stub.vhdl.
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|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_stub.vhdl
|
|
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_system_ila_0_0, cache-ID = fcd979ae904f59e5; cache size = 3280.128 MB.
|
|
config_ip_cache: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 11964.453 ; gain = 0.000
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|
catch { config_ip_cache -export [get_ips -all design_1_util_ds_buf_0_0] }
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_util_ds_buf_0_0
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|
catch { config_ip_cache -export [get_ips -all design_1_clk_wiz_1_1] }
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_clk_wiz_1_1
|
|
catch { config_ip_cache -export [get_ips -all design_1_ila_1_0] }
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ila_1_0
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|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
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create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
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|
launch_runs design_1_clk_wiz_1_1_synth_1 design_1_ila_0_0_synth_1 design_1_ila_1_0_synth_1 design_1_mig_7series_0_0_synth_1 design_1_util_ds_buf_0_0_synth_1 -jobs 24
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_clk_wiz_1_1
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ila_0_0
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ila_1_0
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INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_util_ds_buf_0_0
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[Sat Jul 4 14:55:15 2026] Launched design_1_clk_wiz_1_1_synth_1, design_1_ila_0_0_synth_1, design_1_ila_1_0_synth_1, design_1_mig_7series_0_0_synth_1, design_1_util_ds_buf_0_0_synth_1...
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Run output will be captured here:
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|
design_1_clk_wiz_1_1_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_clk_wiz_1_1_synth_1/runme.log
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design_1_ila_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ila_0_0_synth_1/runme.log
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design_1_ila_1_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ila_1_0_synth_1/runme.log
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design_1_mig_7series_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_mig_7series_0_0_synth_1/runme.log
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|
design_1_util_ds_buf_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_util_ds_buf_0_0_synth_1/runme.log
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export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
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|
reset_run synth_1
|
|
INFO: [Project 1-1161] Replacing file C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/utils_1/imports/synth_1/design_1_wrapper.dcp with file C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/design_1_wrapper.dcp
|
|
WARNING: [Vivado 12-1017] Problems encountered:
|
|
1. Failed to delete one or more files in run directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1
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launch_runs impl_1_copy_2 -to_step write_bitstream -jobs 24
|
|
INFO: [IP_Flow 19-6930] IPCACHE: runCacheChecks() number of threads = 8
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_clk_wiz_1_1
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_ila_0_0
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_ila_1_0
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_util_ds_buf_0_0
|
|
INFO: [IP_Flow 19-8020] IPCACHE: runCacheChecks() calling threadPool finishWork()
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_clk_wiz_1_1
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ila_1_0
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ila_0_0
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_util_ds_buf_0_0
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WARNING: [Project 1-478] Design 'synth_1' is stale and will not be used when launching 'impl_1_copy_2'
|
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[Sat Jul 4 14:55:51 2026] Launched design_1_ila_0_0_synth_1, design_1_mig_7series_0_0_synth_1, design_1_util_ds_buf_0_0_synth_1, design_1_clk_wiz_1_1_synth_1, design_1_ila_1_0_synth_1, synth_1...
|
|
Run output will be captured here:
|
|
design_1_ila_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ila_0_0_synth_1/runme.log
|
|
design_1_mig_7series_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_mig_7series_0_0_synth_1/runme.log
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|
design_1_util_ds_buf_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_util_ds_buf_0_0_synth_1/runme.log
|
|
design_1_clk_wiz_1_1_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_clk_wiz_1_1_synth_1/runme.log
|
|
design_1_ila_1_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ila_1_0_synth_1/runme.log
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|
synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/runme.log
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[Sat Jul 4 14:55:51 2026] Launched impl_1_copy_2...
|
|
Run output will be captured here: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/impl_1_copy_2/runme.log
|
|
launch_runs: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 11964.453 ; gain = 0.000
|
|
reset_run synth_1
|
|
reset_run design_1_ila_0_0_synth_1
|
|
WARNING: [Vivado 12-1017] Problems encountered:
|
|
1. Failed to delete one or more files in run directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ila_0_0_synth_1
|
|
|
|
reset_run design_1_mig_7series_0_0_synth_1
|
|
WARNING: [Vivado 12-1017] Problems encountered:
|
|
1. Failed to delete one or more files in run directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_mig_7series_0_0_synth_1
|
|
|
|
reset_run design_1_ila_1_0_synth_1
|
|
WARNING: [Vivado 12-1017] Problems encountered:
|
|
1. Failed to delete one or more files in run directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ila_1_0_synth_1
|
|
|
|
startgroup
|
|
create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 util_ds_buf_1
|
|
endgroup
|
|
set_property CONFIG.C_BUF_TYPE {BUFG} [get_bd_cells util_ds_buf_1]
|
|
delete_bd_objs [get_bd_nets util_ds_buf_0_IBUF_OUT]
|
|
connect_bd_net [get_bd_pins util_ds_buf_0/IBUF_OUT] [get_bd_pins clk_wiz_1/clk_in1]
|
|
connect_bd_net [get_bd_pins util_ds_buf_1/BUFG_I] [get_bd_pins util_ds_buf_0/IBUF_OUT]
|
|
connect_bd_net [get_bd_pins util_ds_buf_1/BUFG_O] [get_bd_pins mig_7series_0/sys_clk_i]
|
|
regenerate_bd_layout
|
|
validate_bd_design
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
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INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S03_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
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INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S03_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
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INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_1: SmartConnect design_1_smartconnect_0_1 is in High-performance Mode.
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|
xit::source_ipfile: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 11964.453 ; gain = 0.000
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INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_1 clk_wiz propagate
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WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /mig_7series_0/S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
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WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /mig_7series_0/S_AXI(0) and /smartconnect_0/M00_AXI(4)
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validate_bd_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 11964.453 ; gain = 0.000
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generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
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INFO: [BD 41-1662] The design 'design_1.bd' is already validated. Therefore parameter propagation will not be re-run.
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Wrote : <C:\proj\xc7v_ccsds122_datamover_uart\ccsds122_storage.srcs\sources_1\bd\design_1\design_1.bd>
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Wrote : <C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
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Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
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Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/sim/design_1.v
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Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
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Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/hw_handoff/design_1_smartconnect_0_1.hwh
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Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/synth/design_1_smartconnect_0_1.hwdef
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INFO: [BD 41-1029] Generation completed for the IP Integrator block smartconnect_0 .
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WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_ooc.xdc'
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Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/hw_handoff/design_1_system_ila_0_0.hwh
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Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/synth/design_1_system_ila_0_0.hwdef
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INFO: [BD 41-1029] Generation completed for the IP Integrator block system_ila_0 .
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INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ds_buf_1 .
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Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh
|
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Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.hwdef
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generate_target: Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 11996.551 ; gain = 32.098
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catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
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INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_smartconnect_0_1
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INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry 7f92233783f5e392 to dir: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1
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INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/f/7f92233783f5e392/design_1_smartconnect_0_1.dcp to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1.dcp.
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INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1.dcp
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/f/7f92233783f5e392/design_1_smartconnect_0_1_sim_netlist.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.v.
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INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.v
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|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/f/7f92233783f5e392/design_1_smartconnect_0_1_sim_netlist.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.vhdl.
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INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.vhdl
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INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/f/7f92233783f5e392/design_1_smartconnect_0_1_stub.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.v.
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INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.v
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INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/f/7f92233783f5e392/design_1_smartconnect_0_1_stub.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.vhdl.
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|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.vhdl
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|
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_smartconnect_0_1, cache-ID = 7f92233783f5e392; cache size = 3280.255 MB.
|
|
catch { config_ip_cache -export [get_ips -all design_1_ila_0_0] }
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|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ila_0_0
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_system_ila_0_0
|
|
INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry fcd979ae904f59e5 to dir: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/f/c/fcd979ae904f59e5/design_1_system_ila_0_0.dcp to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0.dcp.
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INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0.dcp
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/f/c/fcd979ae904f59e5/design_1_system_ila_0_0_sim_netlist.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_sim_netlist.v.
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INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_sim_netlist.v
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|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/f/c/fcd979ae904f59e5/design_1_system_ila_0_0_sim_netlist.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_sim_netlist.vhdl.
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INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_sim_netlist.vhdl
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|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/f/c/fcd979ae904f59e5/design_1_system_ila_0_0_stub.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_stub.v.
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|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_stub.v
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INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/f/c/fcd979ae904f59e5/design_1_system_ila_0_0_stub.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_stub.vhdl.
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|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_stub.vhdl
|
|
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_system_ila_0_0, cache-ID = fcd979ae904f59e5; cache size = 3280.255 MB.
|
|
config_ip_cache: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 12051.371 ; gain = 0.000
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|
catch { config_ip_cache -export [get_ips -all design_1_ila_1_0] }
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|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ila_1_0
|
|
catch { config_ip_cache -export [get_ips -all design_1_util_ds_buf_1_0] }
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INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_util_ds_buf_1_0
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|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
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create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
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launch_runs design_1_ila_0_0_synth_1 design_1_ila_1_0_synth_1 design_1_mig_7series_0_0_synth_1 design_1_util_ds_buf_1_0_synth_1 -jobs 24
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|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ila_0_0
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ila_1_0
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_util_ds_buf_1_0
|
|
[Sat Jul 4 14:59:02 2026] Launched design_1_ila_0_0_synth_1, design_1_ila_1_0_synth_1, design_1_mig_7series_0_0_synth_1, design_1_util_ds_buf_1_0_synth_1...
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Run output will be captured here:
|
|
design_1_ila_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ila_0_0_synth_1/runme.log
|
|
design_1_ila_1_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ila_1_0_synth_1/runme.log
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design_1_mig_7series_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_mig_7series_0_0_synth_1/runme.log
|
|
design_1_util_ds_buf_1_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_util_ds_buf_1_0_synth_1/runme.log
|
|
export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
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|
launch_runs impl_1_copy_2 -to_step write_bitstream -jobs 24
|
|
INFO: [IP_Flow 19-6930] IPCACHE: runCacheChecks() number of threads = 8
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_ila_0_0
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_ila_1_0
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_util_ds_buf_1_0
|
|
INFO: [IP_Flow 19-8020] IPCACHE: runCacheChecks() calling threadPool finishWork()
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ila_0_0
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ila_1_0
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_util_ds_buf_1_0
|
|
WARNING: [Project 1-478] Design 'synth_1' is stale and will not be used when launching 'impl_1_copy_2'
|
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[Sat Jul 4 14:59:35 2026] Launched design_1_ila_0_0_synth_1, design_1_mig_7series_0_0_synth_1, design_1_ila_1_0_synth_1, design_1_util_ds_buf_1_0_synth_1, synth_1...
|
|
Run output will be captured here:
|
|
design_1_ila_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ila_0_0_synth_1/runme.log
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|
design_1_mig_7series_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_mig_7series_0_0_synth_1/runme.log
|
|
design_1_ila_1_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ila_1_0_synth_1/runme.log
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design_1_util_ds_buf_1_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_util_ds_buf_1_0_synth_1/runme.log
|
|
synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/runme.log
|
|
[Sat Jul 4 14:59:35 2026] Launched impl_1_copy_2...
|
|
Run output will be captured here: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/impl_1_copy_2/runme.log
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create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
|
refresh_design
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_axil_slave_0_0/design_1_ccsds122_axil_slave_0_0.dcp' for cell 'design_1_i/ccsds122_axil_slave_0'
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/design_1_ccsds122_datamover_0_0.dcp' for cell 'design_1_i/ccsds122_datamover_0'
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/design_1_ccsds_uart_axi_0_0.dcp' for cell 'design_1_i/ccsds_uart_axi_0'
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_1_1/design_1_clk_wiz_1_1.dcp' for cell 'design_1_i/clk_wiz_1'
|
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INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ila_0_0/design_1_ila_0_0.dcp' for cell 'design_1_i/ila_0'
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ila_1_0/design_1_ila_1_0.dcp' for cell 'design_1_i/ila_1'
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0.dcp' for cell 'design_1_i/mig_7series_0'
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0.dcp' for cell 'design_1_i/proc_sys_reset_0'
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1.dcp' for cell 'design_1_i/smartconnect_0'
|
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INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0.dcp' for cell 'design_1_i/system_ila_0'
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INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_util_ds_buf_0_0/design_1_util_ds_buf_0_0.dcp' for cell 'design_1_i/util_ds_buf_0'
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INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_util_ds_buf_1_0/design_1_util_ds_buf_1_0.dcp' for cell 'design_1_i/util_ds_buf_1'
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INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_3/design_1_util_vector_logic_0_3.dcp' for cell 'design_1_i/util_vector_logic_0'
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Netlist sorting complete. Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 12636.672 ; gain = 0.000
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INFO: [Netlist 29-17] Analyzing 12966 Unisim elements for replacement
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INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
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WARNING: [Netlist 29-1115] Found multi-term driver net: design_1_i/util_ds_buf_0/U0/<const0>.
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INFO: [Project 1-479] Netlist was created with Vivado 2023.2
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INFO: [Project 1-570] Preparing netlist for logic optimization
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WARNING: [Opt 31-35] Removing redundant IBUF, design_1_i/clk_wiz_1/inst/clkin1_ibufg, from the path connected to top-level port: aclk_0_clk_p[0]
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Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
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WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'design_1_i/clk_wiz_1/clk_in1' is not directly connected to top level port. 'IBUF_LOW_PWR' is ignored for synthesis but preserved for implementation.
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WARNING: [Constraints 18-550] Could not create 'DIFF_TERM' constraint because net 'design_1_i/util_ds_buf_0/IBUF_OUT[0]' is not directly connected to top level port. 'DIFF_TERM' is ignored for synthesis but preserved for implementation.
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WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'design_1_i/util_ds_buf_0/IBUF_OUT[0]' is not directly connected to top level port. 'IBUF_LOW_PWR' is ignored for synthesis but preserved for implementation.
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INFO: [Chipscope 16-324] Core: design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl/u_ila_1 UUID: 9c1f4e79-feb5-532b-8648-e7237e71eda8
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INFO: [Chipscope 16-324] Core: design_1_i/ccsds_uart_axi_0/inst/u_core/u_ila UUID: 224cb1a1-1f43-5694-9b06-fc581d8cbbfe
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INFO: [Chipscope 16-324] Core: design_1_i/ccsds_uart_axi_0/inst/u_core/u_vio_soft_rst UUID: 62b2038d-2768-5030-a5ac-9430fcab7cee
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INFO: [Chipscope 16-324] Core: design_1_i/ila_0 UUID: be177176-557e-59fe-ace2-fe04795a2b22
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INFO: [Chipscope 16-324] Core: design_1_i/ila_1 UUID: b0ff74a9-f11a-54c5-b2aa-3d087c7ab7be
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INFO: [Chipscope 16-324] Core: design_1_i/system_ila_0/inst/ila_lib UUID: cd4c83c8-23a6-596d-99ad-09be1335c6b0
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/axi_datamover_0/axi_datamover_0.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_datamover/U0'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/axi_datamover_0/axi_datamover_0.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_datamover/U0'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/fifo_generator_0/fifo_generator_0.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_bubble_removal/u_pack_fifo/U0'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/fifo_generator_0/fifo_generator_0.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_bubble_removal/u_pack_fifo/U0'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl/u_ila_1/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl/u_ila_1/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl/u_ila_1/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl/u_ila_1/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_1/bd_886d_psr_aclk_0_board.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_1/bd_886d_psr_aclk_0_board.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_1/bd_886d_psr_aclk_0.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_1/bd_886d_psr_aclk_0.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s00_nodes/s00_ar_node/inst'
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:49]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:52]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:55]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:59]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:63]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:66]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:70]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:73]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:76]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:79]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:85]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:88]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:91]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:94]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:97]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:100]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:104]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:107]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:110]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:113]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:116]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:119]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-13' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:122]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:125]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:128]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-13' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:131]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:134]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:137]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:140]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:143]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:146]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:149]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:152]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:155]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:161]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:164]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:167]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:171]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:174]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc:178]
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s00_nodes/s00_ar_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst'
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:49]
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:52]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:55]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:59]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:63]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:66]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:70]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:73]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:76]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:79]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:82]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:85]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:88]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:91]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:94]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:97]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:100]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:104]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:107]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:110]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:113]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:116]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:119]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-13' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:122]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:125]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:128]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-13' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:131]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:134]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:137]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:140]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:143]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:146]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:149]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:152]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:155]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:158]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:161]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:164]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:167]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:171]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:174]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc:178]
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst'
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc:49]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc:52]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc:55]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc:59]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc:63]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc:66]
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc:70]
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc:73]
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc:76]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc:79]
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc:85]
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INFO: [Common 17-14] Message 'Vivado 12-180' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc:88]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc:88]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc:91]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc:94]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc:97]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc:100]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc:104]
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|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc:107]
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INFO: [Common 17-14] Message 'Vivado_Tcl 4-921' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc:107]
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst'
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|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_18/bd_886d_swn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_18/bd_886d_swn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst'
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|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sbn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst'
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|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sbn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst'
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|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_24/bd_886d_sarn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_ar_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_24/bd_886d_sarn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_ar_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_25/bd_886d_srn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_r_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_25/bd_886d_srn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_r_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_26/bd_886d_sawn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_aw_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_26/bd_886d_sawn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_aw_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_27/bd_886d_swn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_w_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_27/bd_886d_swn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_w_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_28/bd_886d_sbn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_b_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_28/bd_886d_sbn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_b_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_33/bd_886d_sarn_2_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s03_nodes/s03_ar_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_33/bd_886d_sarn_2_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s03_nodes/s03_ar_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_34/bd_886d_srn_2_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s03_nodes/s03_r_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_34/bd_886d_srn_2_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s03_nodes/s03_r_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_35/bd_886d_sawn_2_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s03_nodes/s03_aw_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_35/bd_886d_sawn_2_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s03_nodes/s03_aw_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_36/bd_886d_swn_2_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s03_nodes/s03_w_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_36/bd_886d_swn_2_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s03_nodes/s03_w_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_37/bd_886d_sbn_2_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s03_nodes/s03_b_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_37/bd_886d_sbn_2_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s03_nodes/s03_b_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_39/bd_886d_m00arn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_39/bd_886d_m00arn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_40/bd_886d_m00rn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_40/bd_886d_m00rn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_41/bd_886d_m00awn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_41/bd_886d_m00awn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_42/bd_886d_m00wn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_42/bd_886d_m00wn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_43/bd_886d_m00bn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_43/bd_886d_m00bn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_46/bd_886d_m01arn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_ar_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_46/bd_886d_m01arn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_ar_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_47/bd_886d_m01rn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_r_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_47/bd_886d_m01rn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_r_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_48/bd_886d_m01awn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_aw_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_48/bd_886d_m01awn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_aw_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_49/bd_886d_m01wn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_w_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_49/bd_886d_m01wn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_w_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_50/bd_886d_m01bn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_b_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_50/bd_886d_m01bn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_b_node/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/smartconnect.xdc] for cell 'design_1_i/smartconnect_0/inst'
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WARNING: [Vivado_Tcl 4-919] Waiver ID 'CDC-1' -from list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/smartconnect.xdc:1]
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/smartconnect.xdc] for cell 'design_1_i/smartconnect_0/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ila_0_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/ila_0/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ila_0_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/ila_0/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ila_0_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/ila_0/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ila_0_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/ila_0/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/system_ila_0/inst/ila_lib/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/system_ila_0/inst/ila_lib/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/system_ila_0/inst/ila_lib/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/system_ila_0/inst/ila_lib/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0_board.xdc] for cell 'design_1_i/proc_sys_reset_0/U0'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0_board.xdc] for cell 'design_1_i/proc_sys_reset_0/U0'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0.xdc] for cell 'design_1_i/proc_sys_reset_0/U0'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0.xdc] for cell 'design_1_i/proc_sys_reset_0/U0'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/constraints/design_1_mig_7series_0_0.xdc] for cell 'design_1_i/mig_7series_0'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/constraints/design_1_mig_7series_0_0.xdc] for cell 'design_1_i/mig_7series_0'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/src/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/ccsds_uart_axi_0/inst/u_core/u_ila/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/src/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/ccsds_uart_axi_0/inst/u_core/u_ila/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/src/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/ccsds_uart_axi_0/inst/u_core/u_ila/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/src/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/ccsds_uart_axi_0/inst/u_core/u_ila/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/src/vio_0/vio_0.xdc] for cell 'design_1_i/ccsds_uart_axi_0/inst/u_core/u_vio_soft_rst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/src/vio_0/vio_0.xdc] for cell 'design_1_i/ccsds_uart_axi_0/inst/u_core/u_vio_soft_rst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_util_ds_buf_0_0/design_1_util_ds_buf_0_0_board.xdc] for cell 'design_1_i/util_ds_buf_0/U0'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_util_ds_buf_0_0/design_1_util_ds_buf_0_0_board.xdc] for cell 'design_1_i/util_ds_buf_0/U0'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_1_1/design_1_clk_wiz_1_1_board.xdc] for cell 'design_1_i/clk_wiz_1/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_1_1/design_1_clk_wiz_1_1_board.xdc] for cell 'design_1_i/clk_wiz_1/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_1_1/design_1_clk_wiz_1_1.xdc] for cell 'design_1_i/clk_wiz_1/inst'
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INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_1_1/design_1_clk_wiz_1_1.xdc:54]
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INFO: [Timing 38-2] Deriving generated clocks [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_1_1/design_1_clk_wiz_1_1.xdc:54]
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_1_1/design_1_clk_wiz_1_1.xdc] for cell 'design_1_i/clk_wiz_1/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ila_1_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/ila_1/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ila_1_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/ila_1/inst'
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|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ila_1_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/ila_1/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ila_1_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/ila_1/inst'
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|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_util_ds_buf_1_0/design_1_util_ds_buf_1_0_board.xdc] for cell 'design_1_i/util_ds_buf_1/U0'
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_util_ds_buf_1_0/design_1_util_ds_buf_1_0_board.xdc] for cell 'design_1_i/util_ds_buf_1/U0'
|
|
Parsing XDC File [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/constrs_1/new/ccsds122_storage.xdc]
|
|
CRITICAL WARNING: [Common 17-69] Command failed: Invalid I/O Standard 'DIFF_SSTL18'. Default I/O Standard is used instead [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/constrs_1/new/ccsds122_storage.xdc:3]
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|
Finished Parsing XDC File [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/constrs_1/new/ccsds122_storage.xdc]
|
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/axi_datamover_0/axi_datamover_0_clocks.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_datamover/U0'
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|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/axi_datamover_0/axi_datamover_0_clocks.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_datamover/U0'
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|
INFO: [Project 1-1714] 329 XPM XDC files have been applied to the design.
|
|
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
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|
INFO: [Project 1-1687] 1077 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design.
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|
refresh_design: Time (s): cpu = 00:01:43 ; elapsed = 00:01:34 . Memory (MB): peak = 12856.379 ; gain = 805.008
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|
open_bd_design {C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd}
|
|
set_property CONFIG.XML_INPUT_FILE {c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/mig_b.prj} [get_bd_cells mig_7series_0]
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INFO: [IP_Flow 19-3484] Absolute path of file 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/mig_b.prj' provided. It will be converted relative to IP Instance files 'mig_b.prj'
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|
set_property CONFIG.RESET_BOARD_INTERFACE {Custom} [get_bd_cells mig_7series_0]
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set_property CONFIG.MIG_DONT_TOUCH_PARAM {Custom} [get_bd_cells mig_7series_0]
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|
set_property CONFIG.BOARD_MIG_PARAM {Custom} [get_bd_cells mig_7series_0]
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generate_target all [get_files c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0.xci]
|
|
ERROR: [Vivado 12-3563] The Nested sub-design 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0.xci' can only be generated by its parent sub-design.
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regenerate_bd_layout
|
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validate_bd_design
|
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INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
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INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S03_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S03_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_1: SmartConnect design_1_smartconnect_0_1 is in High-performance Mode.
|
|
xit::source_ipfile: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 12856.379 ; gain = 0.000
|
|
INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_1 clk_wiz propagate
|
|
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /mig_7series_0/S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
|
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /mig_7series_0/S_AXI(0) and /smartconnect_0/M00_AXI(4)
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|
validate_bd_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 12856.379 ; gain = 0.000
|
|
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
|
INFO: [BD 41-1662] The design 'design_1.bd' is already validated. Therefore parameter propagation will not be re-run.
|
|
Wrote : <C:\proj\xc7v_ccsds122_datamover_uart\ccsds122_storage.srcs\sources_1\bd\design_1\design_1.bd>
|
|
Wrote : <C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/sim/design_1.v
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/hw_handoff/design_1_smartconnect_0_1.hwh
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/synth/design_1_smartconnect_0_1.hwdef
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block smartconnect_0 .
|
|
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_ooc.xdc'
|
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Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/hw_handoff/design_1_system_ila_0_0.hwh
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/synth/design_1_system_ila_0_0.hwdef
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block system_ila_0 .
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block mig_7series_0 .
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.hwdef
|
|
generate_target: Time (s): cpu = 00:00:35 ; elapsed = 00:00:37 . Memory (MB): peak = 12856.379 ; gain = 0.000
|
|
catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_smartconnect_0_1
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|
INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry 7f92233783f5e392 to dir: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/f/7f92233783f5e392/design_1_smartconnect_0_1.dcp to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1.dcp.
|
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INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1.dcp
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/f/7f92233783f5e392/design_1_smartconnect_0_1_sim_netlist.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.v.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.v
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/f/7f92233783f5e392/design_1_smartconnect_0_1_sim_netlist.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.vhdl.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.vhdl
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/f/7f92233783f5e392/design_1_smartconnect_0_1_stub.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.v.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.v
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/f/7f92233783f5e392/design_1_smartconnect_0_1_stub.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.vhdl.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.vhdl
|
|
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_smartconnect_0_1, cache-ID = 7f92233783f5e392; cache size = 3302.756 MB.
|
|
config_ip_cache: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 12913.379 ; gain = 57.000
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_system_ila_0_0
|
|
INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry fcd979ae904f59e5 to dir: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/f/c/fcd979ae904f59e5/design_1_system_ila_0_0.dcp to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0.dcp.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0.dcp
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/f/c/fcd979ae904f59e5/design_1_system_ila_0_0_sim_netlist.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_sim_netlist.v.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_sim_netlist.v
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/f/c/fcd979ae904f59e5/design_1_system_ila_0_0_sim_netlist.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_sim_netlist.vhdl.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_sim_netlist.vhdl
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/f/c/fcd979ae904f59e5/design_1_system_ila_0_0_stub.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_stub.v.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_stub.v
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/f/c/fcd979ae904f59e5/design_1_system_ila_0_0_stub.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_stub.vhdl.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_stub.vhdl
|
|
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_system_ila_0_0, cache-ID = fcd979ae904f59e5; cache size = 3302.756 MB.
|
|
config_ip_cache: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 12913.379 ; gain = 0.000
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
|
launch_runs design_1_mig_7series_0_0_synth_1 -jobs 24
|
|
[Sat Jul 4 15:35:14 2026] Launched design_1_mig_7series_0_0_synth_1...
|
|
Run output will be captured here: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_mig_7series_0_0_synth_1/runme.log
|
|
export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
|
reset_run synth_1
|
|
INFO: [Project 1-1161] Replacing file C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/utils_1/imports/synth_1/design_1_wrapper.dcp with file C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/design_1_wrapper.dcp
|
|
WARNING: [Vivado 12-1017] Problems encountered:
|
|
1. Failed to delete one or more files in run directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1
|
|
|
|
launch_runs synth_1 -jobs 24
|
|
[Sat Jul 4 15:36:27 2026] Launched design_1_mig_7series_0_0_synth_1...
|
|
Run output will be captured here: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_mig_7series_0_0_synth_1/runme.log
|
|
[Sat Jul 4 15:36:27 2026] Launched synth_1...
|
|
Run output will be captured here: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/runme.log
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create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
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synth_design -rtl -rtl_skip_mlo -name rtl_1
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Command: synth_design -rtl -rtl_skip_mlo -name rtl_1
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Starting synth_design
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Using part: xc7vx690tffg1761-2
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Top: design_1_wrapper
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INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
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INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
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INFO: [Synth 8-7075] Helper process launched with PID 31536
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---------------------------------------------------------------------------------
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Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 13031.910 ; gain = 118.531
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---------------------------------------------------------------------------------
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INFO: [Synth 8-6157] synthesizing module 'design_1_wrapper' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v:13]
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INFO: [Synth 8-6157] synthesizing module 'design_1' [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v:13]
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INFO: [Synth 8-6157] synthesizing module 'design_1_ccsds122_axil_slave_0_0' [C:/proj/xc7v_ccsds122_datamover_uart/.Xil/Vivado-21724-DESKTOP-EB3SDQ2/realtime/design_1_ccsds122_axil_slave_0_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_1_ccsds122_axil_slave_0_0' (0#1) [C:/proj/xc7v_ccsds122_datamover_uart/.Xil/Vivado-21724-DESKTOP-EB3SDQ2/realtime/design_1_ccsds122_axil_slave_0_0_stub.v:6]
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INFO: [Synth 8-6157] synthesizing module 'design_1_ccsds122_datamover_0_0' [C:/proj/xc7v_ccsds122_datamover_uart/.Xil/Vivado-21724-DESKTOP-EB3SDQ2/realtime/design_1_ccsds122_datamover_0_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_1_ccsds122_datamover_0_0' (0#1) [C:/proj/xc7v_ccsds122_datamover_uart/.Xil/Vivado-21724-DESKTOP-EB3SDQ2/realtime/design_1_ccsds122_datamover_0_0_stub.v:6]
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INFO: [Synth 8-6157] synthesizing module 'design_1_ccsds_uart_axi_0_0' [C:/proj/xc7v_ccsds122_datamover_uart/.Xil/Vivado-21724-DESKTOP-EB3SDQ2/realtime/design_1_ccsds_uart_axi_0_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_1_ccsds_uart_axi_0_0' (0#1) [C:/proj/xc7v_ccsds122_datamover_uart/.Xil/Vivado-21724-DESKTOP-EB3SDQ2/realtime/design_1_ccsds_uart_axi_0_0_stub.v:6]
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INFO: [Synth 8-6157] synthesizing module 'design_1_clk_wiz_1_1' [C:/proj/xc7v_ccsds122_datamover_uart/.Xil/Vivado-21724-DESKTOP-EB3SDQ2/realtime/design_1_clk_wiz_1_1_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_1_clk_wiz_1_1' (0#1) [C:/proj/xc7v_ccsds122_datamover_uart/.Xil/Vivado-21724-DESKTOP-EB3SDQ2/realtime/design_1_clk_wiz_1_1_stub.v:6]
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WARNING: [Synth 8-7071] port 'locked' of module 'design_1_clk_wiz_1_1' is unconnected for instance 'clk_wiz_1' [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v:425]
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WARNING: [Synth 8-7023] instance 'clk_wiz_1' of module 'design_1_clk_wiz_1_1' has 4 connections declared, but only 3 given [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v:425]
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WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v:429]
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INFO: [Synth 8-6157] synthesizing module 'design_1_ila_0_0' [C:/proj/xc7v_ccsds122_datamover_uart/.Xil/Vivado-21724-DESKTOP-EB3SDQ2/realtime/design_1_ila_0_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_1_ila_0_0' (0#1) [C:/proj/xc7v_ccsds122_datamover_uart/.Xil/Vivado-21724-DESKTOP-EB3SDQ2/realtime/design_1_ila_0_0_stub.v:6]
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WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v:456]
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INFO: [Synth 8-6157] synthesizing module 'design_1_ila_1_0' [C:/proj/xc7v_ccsds122_datamover_uart/.Xil/Vivado-21724-DESKTOP-EB3SDQ2/realtime/design_1_ila_1_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_1_ila_1_0' (0#1) [C:/proj/xc7v_ccsds122_datamover_uart/.Xil/Vivado-21724-DESKTOP-EB3SDQ2/realtime/design_1_ila_1_0_stub.v:6]
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INFO: [Synth 8-6157] synthesizing module 'design_1_mig_7series_0_0' [C:/proj/xc7v_ccsds122_datamover_uart/.Xil/Vivado-21724-DESKTOP-EB3SDQ2/realtime/design_1_mig_7series_0_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_1_mig_7series_0_0' (0#1) [C:/proj/xc7v_ccsds122_datamover_uart/.Xil/Vivado-21724-DESKTOP-EB3SDQ2/realtime/design_1_mig_7series_0_0_stub.v:6]
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WARNING: [Synth 8-7071] port 'app_sr_active' of module 'design_1_mig_7series_0_0' is unconnected for instance 'mig_7series_0' [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v:461]
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WARNING: [Synth 8-7071] port 'app_ref_ack' of module 'design_1_mig_7series_0_0' is unconnected for instance 'mig_7series_0' [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v:461]
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WARNING: [Synth 8-7071] port 'app_zq_ack' of module 'design_1_mig_7series_0_0' is unconnected for instance 'mig_7series_0' [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v:461]
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WARNING: [Synth 8-7071] port 's_axi_bid' of module 'design_1_mig_7series_0_0' is unconnected for instance 'mig_7series_0' [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v:461]
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WARNING: [Synth 8-7071] port 's_axi_rid' of module 'design_1_mig_7series_0_0' is unconnected for instance 'mig_7series_0' [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v:461]
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WARNING: [Synth 8-7071] port 'device_temp' of module 'design_1_mig_7series_0_0' is unconnected for instance 'mig_7series_0' [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v:461]
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WARNING: [Synth 8-7023] instance 'mig_7series_0' of module 'design_1_mig_7series_0_0' has 63 connections declared, but only 57 given [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v:461]
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INFO: [Synth 8-6157] synthesizing module 'design_1_proc_sys_reset_0_0' [C:/proj/xc7v_ccsds122_datamover_uart/.Xil/Vivado-21724-DESKTOP-EB3SDQ2/realtime/design_1_proc_sys_reset_0_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_1_proc_sys_reset_0_0' (0#1) [C:/proj/xc7v_ccsds122_datamover_uart/.Xil/Vivado-21724-DESKTOP-EB3SDQ2/realtime/design_1_proc_sys_reset_0_0_stub.v:6]
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WARNING: [Synth 8-7071] port 'mb_reset' of module 'design_1_proc_sys_reset_0_0' is unconnected for instance 'proc_sys_reset_0' [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v:519]
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WARNING: [Synth 8-7071] port 'bus_struct_reset' of module 'design_1_proc_sys_reset_0_0' is unconnected for instance 'proc_sys_reset_0' [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v:519]
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WARNING: [Synth 8-7071] port 'peripheral_reset' of module 'design_1_proc_sys_reset_0_0' is unconnected for instance 'proc_sys_reset_0' [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v:519]
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WARNING: [Synth 8-7071] port 'interconnect_aresetn' of module 'design_1_proc_sys_reset_0_0' is unconnected for instance 'proc_sys_reset_0' [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v:519]
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WARNING: [Synth 8-7023] instance 'proc_sys_reset_0' of module 'design_1_proc_sys_reset_0_0' has 10 connections declared, but only 6 given [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v:519]
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INFO: [Synth 8-6157] synthesizing module 'design_1_smartconnect_0_1' [C:/proj/xc7v_ccsds122_datamover_uart/.Xil/Vivado-21724-DESKTOP-EB3SDQ2/realtime/design_1_smartconnect_0_1_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_1_smartconnect_0_1' (0#1) [C:/proj/xc7v_ccsds122_datamover_uart/.Xil/Vivado-21724-DESKTOP-EB3SDQ2/realtime/design_1_smartconnect_0_1_stub.v:6]
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WARNING: [Synth 8-7071] port 'S02_AXI_bid' of module 'design_1_smartconnect_0_1' is unconnected for instance 'smartconnect_0' [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v:526]
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WARNING: [Synth 8-7071] port 'S02_AXI_rid' of module 'design_1_smartconnect_0_1' is unconnected for instance 'smartconnect_0' [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v:526]
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WARNING: [Synth 8-7023] instance 'smartconnect_0' of module 'design_1_smartconnect_0_1' has 147 connections declared, but only 145 given [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v:526]
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WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v:672]
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INFO: [Synth 8-6157] synthesizing module 'design_1_system_ila_0_0' [C:/proj/xc7v_ccsds122_datamover_uart/.Xil/Vivado-21724-DESKTOP-EB3SDQ2/realtime/design_1_system_ila_0_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_1_system_ila_0_0' (0#1) [C:/proj/xc7v_ccsds122_datamover_uart/.Xil/Vivado-21724-DESKTOP-EB3SDQ2/realtime/design_1_system_ila_0_0_stub.v:6]
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INFO: [Synth 8-6157] synthesizing module 'design_1_util_ds_buf_0_0' [C:/proj/xc7v_ccsds122_datamover_uart/.Xil/Vivado-21724-DESKTOP-EB3SDQ2/realtime/design_1_util_ds_buf_0_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_1_util_ds_buf_0_0' (0#1) [C:/proj/xc7v_ccsds122_datamover_uart/.Xil/Vivado-21724-DESKTOP-EB3SDQ2/realtime/design_1_util_ds_buf_0_0_stub.v:6]
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INFO: [Synth 8-6157] synthesizing module 'design_1_util_ds_buf_1_0' [C:/proj/xc7v_ccsds122_datamover_uart/.Xil/Vivado-21724-DESKTOP-EB3SDQ2/realtime/design_1_util_ds_buf_1_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_1_util_ds_buf_1_0' (0#1) [C:/proj/xc7v_ccsds122_datamover_uart/.Xil/Vivado-21724-DESKTOP-EB3SDQ2/realtime/design_1_util_ds_buf_1_0_stub.v:6]
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INFO: [Synth 8-6157] synthesizing module 'design_1_util_vector_logic_0_3' [C:/proj/xc7v_ccsds122_datamover_uart/.Xil/Vivado-21724-DESKTOP-EB3SDQ2/realtime/design_1_util_vector_logic_0_3_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_1_util_vector_logic_0_3' (0#1) [C:/proj/xc7v_ccsds122_datamover_uart/.Xil/Vivado-21724-DESKTOP-EB3SDQ2/realtime/design_1_util_vector_logic_0_3_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_1' (0#1) [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v:13]
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INFO: [Synth 8-6155] done synthesizing module 'design_1_wrapper' (0#1) [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v:13]
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INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'ccsds122_datamover_0'. This will prevent further optimization [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v:300]
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INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'ila_0'. This will prevent further optimization [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v:429]
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INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'proc_sys_reset_0'. This will prevent further optimization [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v:519]
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INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'system_ila_0'. This will prevent further optimization [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v:672]
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INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'smartconnect_0'. This will prevent further optimization [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v:526]
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INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'mig_7series_0'. This will prevent further optimization [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v:461]
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INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'ccsds_uart_axi_0'. This will prevent further optimization [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v:370]
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INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'ccsds122_axil_slave_0'. This will prevent further optimization [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v:264]
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INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'design_1_i'. This will prevent further optimization [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v:76]
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INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'ila_1'. This will prevent further optimization [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v:456]
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---------------------------------------------------------------------------------
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Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 13130.598 ; gain = 217.219
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Handling Custom Attributes
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 13148.520 ; gain = 235.141
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 13148.520 ; gain = 235.141
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---------------------------------------------------------------------------------
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INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_axil_slave_0_0/design_1_ccsds122_axil_slave_0_0.dcp' for cell 'design_1_i/ccsds122_axil_slave_0'
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INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/design_1_ccsds122_datamover_0_0.dcp' for cell 'design_1_i/ccsds122_datamover_0'
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INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/design_1_ccsds_uart_axi_0_0.dcp' for cell 'design_1_i/ccsds_uart_axi_0'
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INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_1_1/design_1_clk_wiz_1_1.dcp' for cell 'design_1_i/clk_wiz_1'
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INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ila_0_0/design_1_ila_0_0.dcp' for cell 'design_1_i/ila_0'
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INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ila_1_0/design_1_ila_1_0.dcp' for cell 'design_1_i/ila_1'
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INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0.dcp' for cell 'design_1_i/mig_7series_0'
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INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0.dcp' for cell 'design_1_i/proc_sys_reset_0'
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INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1.dcp' for cell 'design_1_i/smartconnect_0'
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INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0.dcp' for cell 'design_1_i/system_ila_0'
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INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_util_ds_buf_0_0/design_1_util_ds_buf_0_0.dcp' for cell 'design_1_i/util_ds_buf_0'
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INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_util_ds_buf_1_0/design_1_util_ds_buf_1_0.dcp' for cell 'design_1_i/util_ds_buf_1'
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INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_3/design_1_util_vector_logic_0_3.dcp' for cell 'design_1_i/util_vector_logic_0'
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Netlist sorting complete. Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 13590.707 ; gain = 12.656
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INFO: [Netlist 29-17] Analyzing 12965 Unisim elements for replacement
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INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
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WARNING: [Netlist 29-1115] Found multi-term driver net: design_1_i/util_ds_buf_0/U0/<const0>.
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INFO: [Project 1-479] Netlist was created with Vivado 2023.2
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INFO: [Project 1-570] Preparing netlist for logic optimization
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WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'design_1_i/clk_wiz_1/clk_in1' is not directly connected to top level port. 'IBUF_LOW_PWR' is ignored for synthesis but preserved for implementation.
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WARNING: [Constraints 18-550] Could not create 'DIFF_TERM' constraint because net 'design_1_i/util_ds_buf_0/IBUF_OUT[0]' is not directly connected to top level port. 'DIFF_TERM' is ignored for synthesis but preserved for implementation.
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WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'design_1_i/util_ds_buf_0/IBUF_OUT[0]' is not directly connected to top level port. 'IBUF_LOW_PWR' is ignored for synthesis but preserved for implementation.
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Processing XDC Constraints
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Initializing timing engine
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/axi_datamover_0/axi_datamover_0.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_datamover/U0'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/axi_datamover_0/axi_datamover_0.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_datamover/U0'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/fifo_generator_0/fifo_generator_0.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_bubble_removal/u_pack_fifo/U0'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/fifo_generator_0/fifo_generator_0.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_bubble_removal/u_pack_fifo/U0'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl/u_ila_1/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl/u_ila_1/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_1/bd_886d_psr_aclk_0_board.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_1/bd_886d_psr_aclk_0_board.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_1/bd_886d_psr_aclk_0.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_1/bd_886d_psr_aclk_0.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_1/bd_886d_psr_aclk_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s00_nodes/s00_ar_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s00_nodes/s00_ar_node/inst'
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/bd_886d_sarn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst'
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/bd_886d_srn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst'
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/bd_886d_sawn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_18/bd_886d_swn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_18/bd_886d_swn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst'
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_18/bd_886d_swn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sbn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sbn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst'
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sbn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_24/bd_886d_sarn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_ar_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_24/bd_886d_sarn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_ar_node/inst'
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_24/bd_886d_sarn_1_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_25/bd_886d_srn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_r_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_25/bd_886d_srn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_r_node/inst'
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_25/bd_886d_srn_1_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_26/bd_886d_sawn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_aw_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_26/bd_886d_sawn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_aw_node/inst'
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_26/bd_886d_sawn_1_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_27/bd_886d_swn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_w_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_27/bd_886d_swn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_w_node/inst'
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_27/bd_886d_swn_1_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_28/bd_886d_sbn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_b_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_28/bd_886d_sbn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_b_node/inst'
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_28/bd_886d_sbn_1_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_33/bd_886d_sarn_2_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s03_nodes/s03_ar_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_33/bd_886d_sarn_2_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s03_nodes/s03_ar_node/inst'
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_33/bd_886d_sarn_2_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_34/bd_886d_srn_2_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s03_nodes/s03_r_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_34/bd_886d_srn_2_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s03_nodes/s03_r_node/inst'
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_34/bd_886d_srn_2_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_35/bd_886d_sawn_2_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s03_nodes/s03_aw_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_35/bd_886d_sawn_2_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s03_nodes/s03_aw_node/inst'
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_35/bd_886d_sawn_2_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_36/bd_886d_swn_2_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s03_nodes/s03_w_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_36/bd_886d_swn_2_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s03_nodes/s03_w_node/inst'
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_36/bd_886d_swn_2_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_37/bd_886d_sbn_2_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s03_nodes/s03_b_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_37/bd_886d_sbn_2_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s03_nodes/s03_b_node/inst'
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_37/bd_886d_sbn_2_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_39/bd_886d_m00arn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_39/bd_886d_m00arn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst'
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_39/bd_886d_m00arn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_40/bd_886d_m00rn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_40/bd_886d_m00rn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst'
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_40/bd_886d_m00rn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_41/bd_886d_m00awn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_41/bd_886d_m00awn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst'
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_41/bd_886d_m00awn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_42/bd_886d_m00wn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_42/bd_886d_m00wn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst'
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_42/bd_886d_m00wn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_43/bd_886d_m00bn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_43/bd_886d_m00bn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst'
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_43/bd_886d_m00bn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_46/bd_886d_m01arn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_ar_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_46/bd_886d_m01arn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_ar_node/inst'
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_46/bd_886d_m01arn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_47/bd_886d_m01rn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_r_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_47/bd_886d_m01rn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_r_node/inst'
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_47/bd_886d_m01rn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_48/bd_886d_m01awn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_aw_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_48/bd_886d_m01awn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_aw_node/inst'
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_48/bd_886d_m01awn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_49/bd_886d_m01wn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_w_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_49/bd_886d_m01wn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_w_node/inst'
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_49/bd_886d_m01wn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_50/bd_886d_m01bn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_b_node/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_50/bd_886d_m01bn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_b_node/inst'
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_50/bd_886d_m01bn_0_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/smartconnect.xdc] for cell 'design_1_i/smartconnect_0/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/smartconnect.xdc] for cell 'design_1_i/smartconnect_0/inst'
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/smartconnect.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ila_0_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/ila_0/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ila_0_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/ila_0/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/system_ila_0/inst/ila_lib/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/system_ila_0/inst/ila_lib/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0_board.xdc] for cell 'design_1_i/proc_sys_reset_0/U0'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0_board.xdc] for cell 'design_1_i/proc_sys_reset_0/U0'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0.xdc] for cell 'design_1_i/proc_sys_reset_0/U0'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0.xdc] for cell 'design_1_i/proc_sys_reset_0/U0'
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/constraints/design_1_mig_7series_0_0.xdc] for cell 'design_1_i/mig_7series_0'
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WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/constraints/design_1_mig_7series_0_0.xdc:816]
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WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/constraints/design_1_mig_7series_0_0.xdc:823]
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/constraints/design_1_mig_7series_0_0.xdc] for cell 'design_1_i/mig_7series_0'
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/constraints/design_1_mig_7series_0_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/src/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/ccsds_uart_axi_0/inst/u_core/u_ila/inst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/src/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/ccsds_uart_axi_0/inst/u_core/u_ila/inst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/src/vio_0/vio_0.xdc] for cell 'design_1_i/ccsds_uart_axi_0/inst/u_core/u_vio_soft_rst'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/src/vio_0/vio_0.xdc] for cell 'design_1_i/ccsds_uart_axi_0/inst/u_core/u_vio_soft_rst'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_util_ds_buf_0_0/design_1_util_ds_buf_0_0_board.xdc] for cell 'design_1_i/util_ds_buf_0/U0'
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Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_util_ds_buf_0_0/design_1_util_ds_buf_0_0_board.xdc] for cell 'design_1_i/util_ds_buf_0/U0'
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Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_1_1/design_1_clk_wiz_1_1_board.xdc] for cell 'design_1_i/clk_wiz_1/inst'
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_1_1/design_1_clk_wiz_1_1_board.xdc] for cell 'design_1_i/clk_wiz_1/inst'
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_1_1/design_1_clk_wiz_1_1.xdc] for cell 'design_1_i/clk_wiz_1/inst'
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_1_1/design_1_clk_wiz_1_1.xdc] for cell 'design_1_i/clk_wiz_1/inst'
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_1_1/design_1_clk_wiz_1_1.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ila_1_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/ila_1/inst'
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|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ila_1_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/ila_1/inst'
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|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_util_ds_buf_1_0/design_1_util_ds_buf_1_0_board.xdc] for cell 'design_1_i/util_ds_buf_1/U0'
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_util_ds_buf_1_0/design_1_util_ds_buf_1_0_board.xdc] for cell 'design_1_i/util_ds_buf_1/U0'
|
|
INFO: [Timing 38-2] Deriving generated clocks
|
|
Parsing XDC File [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/constrs_1/new/ccsds122_storage.xdc]
|
|
Finished Parsing XDC File [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/constrs_1/new/ccsds122_storage.xdc]
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/axi_datamover_0/axi_datamover_0_clocks.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_datamover/U0'
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/axi_datamover_0/axi_datamover_0_clocks.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_datamover/U0'
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|
INFO: [Project 1-1714] 329 XPM XDC files have been applied to the design.
|
|
Completed Processing XDC Constraints
|
|
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.067 . Memory (MB): peak = 14514.723 ; gain = 0.000
|
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
|
A total of 3805 instances were transformed.
|
|
CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 1940 instances
|
|
IOBUFDS_DIFF_OUT_DCIEN => IOBUFDS_DIFF_OUT_DCIEN (IBUFDS_IBUFDISABLE_INT(x2), INV, OBUFTDS_DCIEN(x2)): 8 instances
|
|
IOBUF_DCIEN => IOBUF_DCIEN (IBUF_IBUFDISABLE, OBUFT_DCIEN): 64 instances
|
|
LUT6_2 => LUT6_2 (LUT5, LUT6): 28 instances
|
|
OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance
|
|
RAM16X1D => RAM32X1D (RAMD32(x2)): 12 instances
|
|
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 1714 instances
|
|
RAM32X1D => RAM32X1D (RAMD32(x2)): 38 instances
|
|
|
|
RTL Elaboration Complete: : Time (s): cpu = 00:01:14 ; elapsed = 00:01:08 . Memory (MB): peak = 14727.926 ; gain = 1814.547
|
|
95 Infos, 26 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
|
synth_design completed successfully
|
|
synth_design: Time (s): cpu = 00:01:14 ; elapsed = 00:01:08 . Memory (MB): peak = 14727.926 ; gain = 1814.547
|
|
launch_runs impl_1_copy_2 -to_step write_bitstream -jobs 24
|
|
WARNING: [Project 1-478] Design 'synth_1' is stale and will not be used when launching 'impl_1_copy_2'
|
|
[Sat Jul 4 15:42:13 2026] Launched impl_1_copy_2...
|
|
Run output will be captured here: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/impl_1_copy_2/runme.log
|
|
current_design impl_1_copy_2
|
|
close_design
|
|
close_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:11 . Memory (MB): peak = 14902.969 ; gain = 48.324
|
|
close_design
|
|
close_design: Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 14902.969 ; gain = 0.000
|
|
show_objects -name find_1 [get_sites "*CMT_*" ]
|
|
WARNING: [Vivado 12-3731] No sites matched '*CMT_*'
|
|
WARNING: [Coretcl 2-1122] No objects found.
|
|
show_objects -name find_1 [get_sites "*CMT*" ]
|
|
WARNING: [Vivado 12-3731] No sites matched '*CMT*'
|
|
WARNING: [Coretcl 2-1122] No objects found.
|
|
get_sites -filter "NAME=~CMT"
|
|
WARNING: [Vivado 12-3731] No sites matched 'NAME=~CMT'
|
|
get_sites -of [get_clock_regions -of [get_banks 38]] -filter "NAME=~CMT"
|
|
invalid command name "get_banks"
|
|
get_sites -of [get_clock_regions -of [get_banks 38]] -filter "TYPE==MMCME2_ADV"
|
|
invalid command name "get_banks"
|
|
get_sites -filter "TYPE==MMCME2_ADV"
|
|
WARNING: [Vivado 12-3731] No sites matched 'TYPE==MMCME2_ADV'
|
|
get_sites -filter "TYPE==MMCME2_ADV"
|
|
WARNING: [Vivado 12-3731] No sites matched 'TYPE==MMCME2_ADV'
|
|
get_cells -hier *mmcm_adv*
|
|
design_1_i/clk_wiz_1/inst/mmcm_adv_inst
|
|
close_design
|
|
close_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 14958.355 ; gain = 0.000
|
|
reset_run synth_1
|
|
INFO: [Project 1-1161] Replacing file C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/utils_1/imports/synth_1/design_1_wrapper.dcp with file C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/design_1_wrapper.dcp
|
|
launch_runs synth_1 -jobs 24
|
|
[Sat Jul 4 16:23:28 2026] Launched synth_1...
|
|
Run output will be captured here: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/runme.log
|
|
update_ip_catalog -rebuild -scan_changes
|
|
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
|
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/proj/FPGA_DESIGN_IP'.
|
|
report_ip_status -name ip_status
|
|
upgrade_ip -vlnv xilinx.com:user:ccsds122_datamover:1.0 [get_ips design_1_ccsds122_datamover_0_0] -log ip_upgrade.log
|
|
Upgrading 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd'
|
|
INFO: [IP_Flow 19-3420] Updated design_1_ccsds122_datamover_0_0 to use current project options
|
|
Wrote : <C:\proj\xc7v_ccsds122_datamover_uart\ccsds122_storage.srcs\sources_1\bd\design_1\design_1.bd>
|
|
Wrote : <C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
|
|
INFO: [Coretcl 2-1525] Wrote upgrade log to 'C:/proj/xc7v_ccsds122_datamover_uart/ip_upgrade.log'.
|
|
export_ip_user_files -of_objects [get_ips design_1_ccsds122_datamover_0_0] -no_script -sync -force -quiet
|
|
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S03_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [BD 5-943] Reserving offset range <0xFFFF_0000 [ 64K ]> from slave interface '/smartconnect_0/S03_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
|
INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_1: SmartConnect design_1_smartconnect_0_1 is in High-performance Mode.
|
|
xit::source_ipfile: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 14958.355 ; gain = 0.000
|
|
INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_1 clk_wiz propagate
|
|
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /mig_7series_0/S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
|
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /mig_7series_0/S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
|
Wrote : <C:\proj\xc7v_ccsds122_datamover_uart\ccsds122_storage.srcs\sources_1\bd\design_1\design_1.bd>
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/sim/design_1.v
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
|
|
INFO: [IP_Flow 19-3420] Updated fifo_generator_0 to use current project options
|
|
INFO: [IP_Flow 19-3420] Updated ila_1 to use current project options
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block ccsds122_datamover_0 .
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/hw_handoff/design_1_smartconnect_0_1.hwh
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/synth/design_1_smartconnect_0_1.hwdef
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block smartconnect_0 .
|
|
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_ooc.xdc'
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/hw_handoff/design_1_system_ila_0_0.hwh
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/synth/design_1_system_ila_0_0.hwdef
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block system_ila_0 .
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.hwdef
|
|
generate_target: Time (s): cpu = 00:01:05 ; elapsed = 00:01:08 . Memory (MB): peak = 14958.355 ; gain = 0.000
|
|
catch { config_ip_cache -export [get_ips -all design_1_ccsds122_datamover_0_0] }
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds122_datamover_0_0
|
|
catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_smartconnect_0_1
|
|
INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry 7f92233783f5e392 to dir: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/f/7f92233783f5e392/design_1_smartconnect_0_1.dcp to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1.dcp.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1.dcp
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/f/7f92233783f5e392/design_1_smartconnect_0_1_sim_netlist.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.v.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.v
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/f/7f92233783f5e392/design_1_smartconnect_0_1_sim_netlist.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.vhdl.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.vhdl
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/f/7f92233783f5e392/design_1_smartconnect_0_1_stub.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.v.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.v
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/f/7f92233783f5e392/design_1_smartconnect_0_1_stub.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.vhdl.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.vhdl
|
|
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_smartconnect_0_1, cache-ID = 7f92233783f5e392; cache size = 3302.756 MB.
|
|
config_ip_cache: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 14958.355 ; gain = 0.000
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_system_ila_0_0
|
|
INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry fcd979ae904f59e5 to dir: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/f/c/fcd979ae904f59e5/design_1_system_ila_0_0.dcp to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0.dcp.
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0.dcp
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/f/c/fcd979ae904f59e5/design_1_system_ila_0_0_sim_netlist.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_sim_netlist.v.
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INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_sim_netlist.v
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INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/f/c/fcd979ae904f59e5/design_1_system_ila_0_0_sim_netlist.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_sim_netlist.vhdl.
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INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_sim_netlist.vhdl
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INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/f/c/fcd979ae904f59e5/design_1_system_ila_0_0_stub.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_stub.v.
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INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_stub.v
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INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/f/c/fcd979ae904f59e5/design_1_system_ila_0_0_stub.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_stub.vhdl.
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INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_stub.vhdl
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INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_system_ila_0_0, cache-ID = fcd979ae904f59e5; cache size = 3302.756 MB.
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config_ip_cache: Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 14958.355 ; gain = 0.000
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export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
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create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
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launch_runs design_1_ccsds122_datamover_0_0_synth_1 -jobs 24
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INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds122_datamover_0_0
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[Sat Jul 4 16:31:28 2026] Launched design_1_ccsds122_datamover_0_0_synth_1...
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Run output will be captured here: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ccsds122_datamover_0_0_synth_1/runme.log
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export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
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reset_run synth_1
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INFO: [Project 1-1161] Replacing file C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/utils_1/imports/synth_1/design_1_wrapper.dcp with file C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/design_1_wrapper.dcp
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WARNING: [Vivado 12-1017] Problems encountered:
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1. Failed to delete one or more files in run directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1
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launch_runs impl_1_copy_2 -to_step write_bitstream -jobs 24
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INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds122_datamover_0_0
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[Sat Jul 4 16:31:59 2026] Launched design_1_ccsds122_datamover_0_0_synth_1, synth_1...
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Run output will be captured here:
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design_1_ccsds122_datamover_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ccsds122_datamover_0_0_synth_1/runme.log
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synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/runme.log
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[Sat Jul 4 16:31:59 2026] Launched impl_1_copy_2...
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Run output will be captured here: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/impl_1_copy_2/runme.log
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close_bd_design [get_bd_designs design_1]
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report_ip_status -name ip_status
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reset_run synth_1
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reset_run design_1_ccsds122_datamover_0_0_synth_1
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WARNING: [Vivado 12-1017] Problems encountered:
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1. Failed to delete one or more files in run directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ccsds122_datamover_0_0_synth_1
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exit
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INFO: [Common 17-206] Exiting Vivado at Sat Jul 4 16:33:28 2026...
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