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#-----------------------------------------------------------
# Vivado v2023.2 (64-bit)
# SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
# Start of session at: Sun Jul 5 13:55:25 2026
# Process ID: 28992
# Current directory: C:/proj/xc7v_ccsds122_datamover_uart
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent22500 C:\proj\xc7v_ccsds122_datamover_uart\ccsds122_storage.xpr
# Log file: C:/proj/xc7v_ccsds122_datamover_uart/vivado.log
# Journal file: C:/proj/xc7v_ccsds122_datamover_uart\vivado.jou
# Running On: DESKTOP-EB3SDQ2, OS: Windows, CPU Frequency: 2112 MHz, CPU Physical cores: 16, Host memory: 16817 MB
#-----------------------------------------------------------
start_gui
open_project C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.xpr
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.1 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.1/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.0 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.0/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.1 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.1/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.1 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.1/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/proj/FPGA_DESIGN_IP'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2023.2/data/ip'.
WARNING: [filemgmt 56-443] The ECC Algorithm string is empty. Setting the Memory Map to default ECC value to ECC_NONE.
WARNING: [filemgmt 56-443] The ECC Algorithm string is empty. Setting the Memory Map to default ECC value to ECC_NONE.
open_project: Time (s): cpu = 00:00:23 ; elapsed = 00:00:15 . Memory (MB): peak = 1797.605 ; gain = 523.293
update_compile_order -fileset sources_1
set_property SOURCE_SET sources_1 [get_filesets sim_1]
add_files -fileset sim_1 -norecurse {C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/interface.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/arch_package.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_model.sv}
set_property SOURCE_SET sources_1 [get_filesets sim_1]
add_files -fileset sim_1 -norecurse {C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/interface.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/arch_package.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_model.sv}
WARNING: [filemgmt 56-12] File 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/interface.sv' cannot be added to the project because it already exists in the project, skipping this file
WARNING: [filemgmt 56-12] File 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/arch_package.sv' cannot be added to the project because it already exists in the project, skipping this file
WARNING: [filemgmt 56-12] File 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_model.sv' cannot be added to the project because it already exists in the project, skipping this file
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_model.sv] -no_script -reset -force -quiet
remove_files -fileset sim_1 C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_model.sv
set_property SOURCE_SET sources_1 [get_filesets sim_1]
add_files -fileset sim_1 -norecurse {C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/interface.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/arch_package.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_model.sv}
WARNING: [filemgmt 56-12] File 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/interface.sv' cannot be added to the project because it already exists in the project, skipping this file
WARNING: [filemgmt 56-12] File 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/arch_package.sv' cannot be added to the project because it already exists in the project, skipping this file
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-12493] Simulation top is 'tb_design_1_wrapper'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
Generating merged BMM file for the design top 'tb_design_1_wrapper'...
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2023.2/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2023.2/data/xsim/xsim.ini' copied to run dir:'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim'
INFO: [SIM-utils-50] Design contains embedded sources, generating MEM files for simulation...
Generating merged BMM file for the design top 'tb_design_1_wrapper'...
WARNING: [Memdata 28-361] Design is having concatenated BRAM controllers(heterogenous memory), this configuration is not supported by Updatemem for current device part. Only the first BRAM controller will be added to .MMI and used by Updatemem to update the bitstream with new data.
Generating merged BMM file for the design top 'tb_design_1_wrapper'...
INFO: [SIM-utils-54] Inspecting design source files for 'tb_design_1_wrapper' in fileset 'sim_1'...
INFO: [SIM-utils-43] Exported 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim/sc_xtlm_design_1_smartconnect_0_1.mem'
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim'
"xvlog --incr --relax -L uvm -L axi_vip_v1_1_15 -L smartconnect_v1_0 -L xilinx_vip -prj tb_design_1_wrapper_vlog.prj"
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/arch_package.sv" into library xil_defaultlib
ERROR: [VRFC 10-3195] cannot open include file 'arch_defines.v' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/arch_package.sv:52]
ERROR: [VRFC 10-8530] package 'arch_package' is ignored due to previous errors [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/arch_package.sv:49]
"xvhdl --incr --relax -prj tb_design_1_wrapper_vhdl.prj"
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-99] Step results log file:'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim/xvlog.log'
ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim/xvlog.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 1859.570 ; gain = 19.473
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
set_property SOURCE_SET sources_1 [get_filesets sim_1]
add_files -fileset sim_1 -norecurse {C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/arch_defines.v C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sdram_model_wrapper.sv}
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-12493] Simulation top is 'tb_design_1_wrapper'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
Generating merged BMM file for the design top 'tb_design_1_wrapper'...
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2023.2/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2023.2/data/xsim/xsim.ini' copied to run dir:'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim'
INFO: [SIM-utils-50] Design contains embedded sources, generating MEM files for simulation...
Generating merged BMM file for the design top 'tb_design_1_wrapper'...
WARNING: [Memdata 28-361] Design is having concatenated BRAM controllers(heterogenous memory), this configuration is not supported by Updatemem for current device part. Only the first BRAM controller will be added to .MMI and used by Updatemem to update the bitstream with new data.
Generating merged BMM file for the design top 'tb_design_1_wrapper'...
INFO: [SIM-utils-54] Inspecting design source files for 'tb_design_1_wrapper' in fileset 'sim_1'...
INFO: [SIM-utils-43] Exported 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim/sc_xtlm_design_1_smartconnect_0_1.mem'
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim'
"xvlog --incr --relax -L uvm -L axi_vip_v1_1_15 -L smartconnect_v1_0 -L xilinx_vip -prj tb_design_1_wrapper_vlog.prj"
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/arch_package.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_model.sv" into library xil_defaultlib
ERROR: [VRFC 10-3195] cannot open include file 'StateTable.sv' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_model.sv:83]
ERROR: [VRFC 10-3195] cannot open include file 'MemoryArray.sv' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_model.sv:84]
INFO: [VRFC 10-311] analyzing module ddr4_model
ERROR: [VRFC 10-2989] 'MemArray' is not declared [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_model.sv:141]
ERROR: [VRFC 10-3195] cannot open include file 'timing_tasks.sv' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_model.sv:148]
ERROR: [VRFC 10-2989] 'MemArray' is not declared [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_model.sv:219]
ERROR: [VRFC 10-2989] 'MemArray' is not declared [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_model.sv:221]
ERROR: [VRFC 10-2989] 'proj_package' is not declared [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_model.sv:309]
ERROR: [VRFC 10-2989] 'proj_package' is not declared [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_model.sv:2320]
ERROR: [VRFC 10-2989] 'proj_package' is not declared [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_model.sv:2321]
ERROR: [VRFC 10-2989] 'proj_package' is not declared [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_model.sv:2326]
ERROR: [VRFC 10-2989] 'proj_package' is not declared [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_model.sv:2327]
ERROR: [VRFC 10-2989] 'proj_package' is not declared [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_model.sv:2341]
ERROR: [VRFC 10-2989] 'proj_package' is not declared [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_model.sv:2342]
ERROR: [VRFC 10-2989] 'MemArray' is not declared [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_model.sv:2424]
ERROR: [VRFC 10-2989] 'MemArray' is not declared [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_model.sv:2449]
ERROR: [VRFC 10-2989] '_4G' is not declared [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_model.sv:86]
ERROR: [VRFC 10-2989] 'memKey_type' is not declared [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_model.sv:222]
ERROR: [VRFC 10-2989] 'tCK' is not declared [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_model.sv:249]
ERROR: [VRFC 10-2989] 'tCK' is not declared [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_model.sv:251]
INFO: [#UNDEF] Sorry, too many errors..
"xvhdl --incr --relax -prj tb_design_1_wrapper_vhdl.prj"
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-99] Step results log file:'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim/xvlog.log'
ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim/xvlog.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 1904.141 ; gain = 42.547
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
INFO: [BD 41-1637] Generated targets are already up-to-date for block design 'design_1' - hence not re-generating.
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
update_compile_order -fileset sim_1
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_model.sv] -no_script -reset -force -quiet
remove_files -fileset sim_1 C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_model.sv
reset_simulation -simset sim_1 -mode behavioral
INFO: [Vivado 12-2266] Removing simulation data...
INFO: [Vivado 12-2267] Reset complete
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-12493] Simulation top is 'tb_design_1_wrapper'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
Generating merged BMM file for the design top 'tb_design_1_wrapper'...
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2023.2/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2023.2/data/xsim/xsim.ini' copied to run dir:'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim'
INFO: [SIM-utils-50] Design contains embedded sources, generating MEM files for simulation...
Generating merged BMM file for the design top 'tb_design_1_wrapper'...
WARNING: [Memdata 28-361] Design is having concatenated BRAM controllers(heterogenous memory), this configuration is not supported by Updatemem for current device part. Only the first BRAM controller will be added to .MMI and used by Updatemem to update the bitstream with new data.
Generating merged BMM file for the design top 'tb_design_1_wrapper'...
INFO: [SIM-utils-54] Inspecting design source files for 'tb_design_1_wrapper' in fileset 'sim_1'...
INFO: [SIM-utils-43] Exported 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim/sc_xtlm_design_1_smartconnect_0_1.mem'
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim'
"xvlog --incr --relax -L uvm -L axi_vip_v1_1_15 -L smartconnect_v1_0 -L xilinx_vip -prj tb_design_1_wrapper_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/fifo_generator_0/sim/fifo_generator_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fifo_generator_0
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/ila_1/sim/ila_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ila_1
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122_addr_calc.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122_addr_calc
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122_bubble_removal_ctrl.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122_bubble_removal_ctrl
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_pkg.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122_compression_top.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122_compression_top
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122_stream_ctrl.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122_stream_ctrl
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_ac_bitplane_cached_commit.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_ac_bitplane_cached_commit
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_ac_bitplane_gaggle_encoder.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_ac_bitplane_gaggle_encoder
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_ac_depth_encoder.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_ac_depth_option_select
INFO: [VRFC 10-311] analyzing module ccsds122p_ac_depth_code_emitter
INFO: [VRFC 10-311] analyzing module ccsds122p_ac_depth_encoder
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_ac_stage0_dc_emit.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_ac_stage0_dc_emit
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_backend_farm.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_backend_farm
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_backend_lane.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_backend_lane
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_bit_length24.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_bit_length24
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_bitstream_packer.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_bitstream_packer
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_block_state_pack.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_block_state_pack
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_block_state_ram.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_block_state_ram
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_dc_code_emitter.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_dc_code_emitter
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_dc_entropy_encoder.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_dc_entropy_encoder
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_dc_option_select.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_dc_option_select
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_dc_seed.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_dc_seed
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_dwt_h_stage.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_dwt_h_stage
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_dwt_l0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_dwt_l0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_dwt_l1.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_dwt_l1
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_dwt_l2.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_dwt_l2
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_dwt_ll_row_order.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_dwt_ll_row_order
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_dwt_m97_lift_core.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_dwt_m97_lift_core
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_dwt_merge.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_dwt_merge
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_dwt_split_stage.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_dwt_split_stage
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_dwt_v_stage.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_dwt_v_stage
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_encoded_segment_reorder.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_encoded_segment_reorder
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_header_writer.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_header_writer
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_ingress_frontend.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_ingress_frontend
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_segment_bank.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_segment_bank
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_segment_bitdepth.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_segment_bitdepth
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_segment_block_reader.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_segment_block_reader
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_segment_encoder_core.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_segment_encoder_core
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_segment_fill.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_segment_fill
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_segment_first_pass.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_segment_first_pass
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_segment_reorder.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_segment_reorder
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_segment_state_bank.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_segment_state_bank
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_segment_stats.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_segment_stats
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_stage_block_scan.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_stage_block_scan
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_stage_option_select.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_stage_pattern_map
INFO: [VRFC 10-311] analyzing module ccsds122p_stage_option_select
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_stage_refine_emit.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_stage_refine_emit
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_stage_rice_emitter.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_stage_rice_emitter
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_stage_symbol_emit.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_stage_symbol_emit
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_subband_router.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_subband_router
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_xpm_sdpram.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_xpm_sdpram
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122p_xpm_sdpram_masked.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122p_xpm_sdpram_masked
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/top_bpe_encoder.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module top_bpe_encoder
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/54b1/src/ccsds122_datamover.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122_datamover
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ccsds122_datamover_0_0/sim/design_1_ccsds122_datamover_0_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_1_ccsds122_datamover_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_0/sim/bd_886d_one_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_one_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_4/sim/bd_886d_arsw_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_arsw_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_5/sim/bd_886d_rsw_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_rsw_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_6/sim/bd_886d_awsw_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_awsw_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_7/sim/bd_886d_wsw_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_wsw_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_8/sim/bd_886d_bsw_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_bsw_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_9/sim/bd_886d_s00mmu_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_s00mmu_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_10/sim/bd_886d_s00tr_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_s00tr_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_11/sim/bd_886d_s00sic_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_s00sic_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_12/sim/bd_886d_s00a2s_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_s00a2s_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/sim/bd_886d_sarn_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_sarn_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/sim/bd_886d_srn_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_srn_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_15/sim/bd_886d_s01mmu_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_s01mmu_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_16/sim/bd_886d_s01tr_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_s01tr_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_17/sim/bd_886d_s01sic_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_s01sic_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_18/sim/bd_886d_s01a2s_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_s01a2s_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/sim/bd_886d_sawn_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_sawn_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_20/sim/bd_886d_swn_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_swn_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_21/sim/bd_886d_sbn_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_sbn_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_22/sim/bd_886d_s02mmu_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_s02mmu_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_23/sim/bd_886d_s02tr_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_s02tr_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_24/sim/bd_886d_s02sic_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_s02sic_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_25/sim/bd_886d_s02a2s_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_s02a2s_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_26/sim/bd_886d_sarn_1.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_sarn_1
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_27/sim/bd_886d_srn_1.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_srn_1
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_28/sim/bd_886d_sawn_1.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_sawn_1
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_29/sim/bd_886d_swn_1.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_swn_1
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_30/sim/bd_886d_sbn_1.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_sbn_1
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_31/sim/bd_886d_s03mmu_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_s03mmu_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_32/sim/bd_886d_s03tr_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_s03tr_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_33/sim/bd_886d_s03sic_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_s03sic_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_34/sim/bd_886d_s03a2s_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_s03a2s_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_35/sim/bd_886d_sarn_2.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_sarn_2
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_36/sim/bd_886d_srn_2.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_srn_2
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_37/sim/bd_886d_sawn_2.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_sawn_2
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_38/sim/bd_886d_swn_2.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_swn_2
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_39/sim/bd_886d_sbn_2.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_sbn_2
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_40/sim/bd_886d_m00s2a_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_m00s2a_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_41/sim/bd_886d_m00arn_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_m00arn_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_42/sim/bd_886d_m00rn_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_m00rn_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_43/sim/bd_886d_m00awn_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_m00awn_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_44/sim/bd_886d_m00wn_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_m00wn_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_45/sim/bd_886d_m00bn_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_m00bn_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_46/sim/bd_886d_m00e_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_m00e_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_47/sim/bd_886d_m01s2a_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_m01s2a_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_48/sim/bd_886d_m01arn_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_m01arn_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_49/sim/bd_886d_m01rn_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_m01rn_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_50/sim/bd_886d_m01awn_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_m01awn_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_51/sim/bd_886d_m01wn_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_m01wn_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_52/sim/bd_886d_m01bn_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_m01bn_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_53/sim/bd_886d_m01e_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d_m01e_0
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/sim/bd_886d.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_886d
INFO: [VRFC 10-311] analyzing module clk_map_imp_1WP46Y0
INFO: [VRFC 10-311] analyzing module m00_exit_pipeline_imp_4816GJ
INFO: [VRFC 10-311] analyzing module m00_nodes_imp_QDFR33
INFO: [VRFC 10-311] analyzing module m01_exit_pipeline_imp_6OCSAB
INFO: [VRFC 10-311] analyzing module m01_nodes_imp_1HTXBQH
INFO: [VRFC 10-311] analyzing module s00_entry_pipeline_imp_12V3TGW
INFO: [VRFC 10-311] analyzing module s00_nodes_imp_16MUXNU
INFO: [VRFC 10-311] analyzing module s01_entry_pipeline_imp_6HKV8K
INFO: [VRFC 10-311] analyzing module s01_nodes_imp_1AH57G
INFO: [VRFC 10-311] analyzing module s02_entry_pipeline_imp_R26R6H
INFO: [VRFC 10-311] analyzing module s02_nodes_imp_XIDFT3
INFO: [VRFC 10-311] analyzing module s03_entry_pipeline_imp_1XMQ8JX
INFO: [VRFC 10-311] analyzing module s03_nodes_imp_1RRAM9D
INFO: [VRFC 10-311] analyzing module switchboards_imp_1V8ZM66
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/sim/design_1_smartconnect_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_1_smartconnect_0_1
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/fe4d/src/ccsds122_axil_slave.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds122_axil_slave
WARNING: [VRFC 10-3380] identifier 'enable_reg_d1' is used before its declaration [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/fe4d/src/ccsds122_axil_slave.sv:140]
WARNING: [VRFC 10-3380] identifier 'enable_reg_d1' is used before its declaration [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/fe4d/src/ccsds122_axil_slave.sv:178]
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ccsds122_axil_slave_0_0/sim/design_1_ccsds122_axil_slave_0_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_1_ccsds122_axil_slave_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ila_0_0/sim/design_1_ila_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_1_ila_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/src/vio_0/sim/vio_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module vio_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/08a1/src/axi_uart_upload.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axi_uart_upload
WARNING: [VRFC 10-3380] identifier 'awst_q' is used before its declaration [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/08a1/src/axi_uart_upload.sv:286]
WARNING: [VRFC 10-3380] identifier 'arst_q' is used before its declaration [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/08a1/src/axi_uart_upload.sv:288]
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/08a1/src/uart_rx.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module uart_rx
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/08a1/src/uart_tx.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module uart_tx
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/08a1/src/ccsds_uart_axi.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ccsds_uart_axi
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/sim/design_1_ccsds_uart_axi_0_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_1_ccsds_uart_axi_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_6/sim/bd_45eb_lmb_bram_I_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_45eb_lmb_bram_I_0
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_9/sim/bd_45eb_second_lmb_bram_I_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_45eb_second_lmb_bram_I_0
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/bd_0/sim/bd_45eb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_45eb
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/ip_0/sim/design_1_ddr4_0_0_microblaze_mcs.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_1_ddr4_0_0_microblaze_mcs
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/ip_1/rtl/phy/design_1_ddr4_0_0_phy_ddr4.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_1_ddr4_0_0_phy_ddr4
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy_behav.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_phy_v2_2_1_xiphy_behav
INFO: [VRFC 10-311] analyzing module ddr4_phy_v2_2_1_bitslice_behav
INFO: [VRFC 10-311] analyzing module ddr4_phy_v2_2_1_fifo_sv
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/ip_1/rtl/phy/ddr4_phy_v2_2_xiphy.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_phy_v2_2_1_xiphy
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/ip_1/rtl/iob/ddr4_phy_v2_2_iob_byte.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_phy_v2_2_1_iob_byte
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/ip_1/rtl/iob/ddr4_phy_v2_2_iob.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_phy_v2_2_1_iob
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/ip_1/rtl/clocking/ddr4_phy_v2_2_pll.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_phy_v2_2_1_pll
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_tristate_wrapper.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_phy_v2_2_1_xiphy_tristate_wrapper
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_riuor_wrapper.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_phy_v2_2_1_xiphy_riuor_wrapper
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_control_wrapper.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_phy_v2_2_1_xiphy_control_wrapper
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_byte_wrapper.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_phy_v2_2_1_xiphy_byte_wrapper
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/ip_1/rtl/xiphy_files/ddr4_phy_v2_2_xiphy_bitslice_wrapper.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_phy_v2_2_1_xiphy_bitslice_wrapper
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/ip_1/rtl/ip_top/design_1_ddr4_0_0_phy.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_1_ddr4_0_0_phy
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/controller/ddr4_v2_2_mc_wtr.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_mc_wtr
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/controller/ddr4_v2_2_mc_ref.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_mc_ref
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/controller/ddr4_v2_2_mc_rd_wr.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_mc_rd_wr
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/controller/ddr4_v2_2_mc_periodic.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_mc_periodic
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/controller/ddr4_v2_2_mc_group.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_mc_group
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/controller/ddr4_v2_2_mc_ecc_merge_enc.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_mc_ecc_merge_enc
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/controller/ddr4_v2_2_mc_ecc_gen.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_mc_ecc_gen
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/controller/ddr4_v2_2_mc_ecc_fi_xor.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_mc_ecc_fi_xor
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/controller/ddr4_v2_2_mc_ecc_dec_fix.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_mc_ecc_dec_fix
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/controller/ddr4_v2_2_mc_ecc_buf.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_mc_ecc_buf
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/controller/ddr4_v2_2_mc_ecc.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_mc_ecc
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/controller/ddr4_v2_2_mc_ctl.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_mc_ctl
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/controller/ddr4_v2_2_mc_cmd_mux_c.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_mc_cmd_mux_c
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/controller/ddr4_v2_2_mc_cmd_mux_ap.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_mc_cmd_mux_ap
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/controller/ddr4_v2_2_mc_arb_p.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_mc_arb_p
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/controller/ddr4_v2_2_mc_arb_mux_p.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_mc_arb_mux_p
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/controller/ddr4_v2_2_mc_arb_c.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_mc_arb_c
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/controller/ddr4_v2_2_mc_arb_a.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_mc_arb_a
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/controller/ddr4_v2_2_mc_act_timer.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_mc_act_timer
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/controller/ddr4_v2_2_mc_act_rank.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_mc_act_rank
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/controller/ddr4_v2_2_mc.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_mc
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/ui/ddr4_v2_2_ui_wr_data.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_ui_wr_data
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/ui/ddr4_v2_2_ui_rd_data.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_ui_rd_data
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/ui/ddr4_v2_2_ui_cmd.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_ui_cmd
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/ui/ddr4_v2_2_ui.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_ui
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/axi/ddr4_v2_2_axi_ar_channel.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_axi_ar_channel
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/axi/ddr4_v2_2_axi_aw_channel.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_axi_aw_channel
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/axi/ddr4_v2_2_axi_b_channel.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_axi_b_channel
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/axi/ddr4_v2_2_axi_cmd_arbiter.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_axi_cmd_arbiter
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/axi/ddr4_v2_2_axi_cmd_fsm.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_axi_cmd_fsm
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/axi/ddr4_v2_2_axi_cmd_translator.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_axi_cmd_translator
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/axi/ddr4_v2_2_axi_fifo.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_axi_fifo
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/axi/ddr4_v2_2_axi_incr_cmd.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_axi_incr_cmd
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/axi/ddr4_v2_2_axi_r_channel.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_axi_r_channel
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/axi/ddr4_v2_2_axi_w_channel.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_axi_w_channel
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/axi/ddr4_v2_2_axi_wr_cmd_fsm.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_axi_wr_cmd_fsm
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/axi/ddr4_v2_2_axi_wrap_cmd.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_axi_wrap_cmd
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/axi/ddr4_v2_2_a_upsizer.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_a_upsizer
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/axi/ddr4_v2_2_axi.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_axi
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/axi/ddr4_v2_2_axi_register_slice.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_axi_register_slice
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/axi/ddr4_v2_2_axi_upsizer.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_axi_upsizer
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/axi/ddr4_v2_2_axic_register_slice.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_axic_register_slice
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/axi/ddr4_v2_2_carry_and.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_carry_and
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/axi/ddr4_v2_2_carry_latch_and.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_carry_latch_and
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/axi/ddr4_v2_2_carry_latch_or.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_carry_latch_or
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/axi/ddr4_v2_2_carry_or.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_carry_or
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/axi/ddr4_v2_2_command_fifo.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_command_fifo
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/axi/ddr4_v2_2_comparator.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_comparator
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/axi/ddr4_v2_2_comparator_sel.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_comparator_sel
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/axi/ddr4_v2_2_comparator_sel_static.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_comparator_sel_static
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/axi/ddr4_v2_2_r_upsizer.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_r_upsizer
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/axi/ddr4_v2_2_w_upsizer.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_w_upsizer
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/axi_ctrl/ddr4_v2_2_axi_ctrl_addr_decode.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_axi_ctrl_addr_decode
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/axi_ctrl/ddr4_v2_2_axi_ctrl_read.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_axi_ctrl_read
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/axi_ctrl/ddr4_v2_2_axi_ctrl_reg_bank.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_axi_ctrl_reg_bank
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/axi_ctrl/ddr4_v2_2_axi_ctrl_reg.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_axi_ctrl_reg
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/axi_ctrl/ddr4_v2_2_axi_ctrl_top.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_axi_ctrl_top
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/axi_ctrl/ddr4_v2_2_axi_ctrl_write.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_axi_ctrl_write
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/clocking/ddr4_v2_2_infrastructure.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_infrastructure
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_cal_xsdb_bram
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_cal_write.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_cal_write
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_cal_wr_byte.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_cal_wr_byte
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_cal_wr_bit.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_cal_wr_bit
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_cal_sync.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_cal_sync
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_cal_read.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_cal_read
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_cal_rd_en.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_cal_rd_en
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_cal_pi.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_cal_pi
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_cal_mc_odt.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_cal_mc_odt
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_cal_debug_microblaze.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_cal_debug_microblaze
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_cal_cplx_data.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_cal_cplx_data
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_cal_cplx.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_cal_cplx
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_cal_config_rom.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_cal_config_rom
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_cal_addr_decode.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_cal_addr_decode
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_cal_top.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_cal_top
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_cal_xsdb_arbiter.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_cal_xsdb_arbiter
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_cal.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_cal
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_chipscope_xsdb_slave.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_chipscope_xsdb_slave
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_dp_AB9.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_cfg_mem_mod
INFO: [VRFC 10-311] analyzing module ddr4_v2_2_20_bram_tdp
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/ip_top/design_1_ddr4_0_0_ddr4.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_1_ddr4_0_0_ddr4
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/ip_top/design_1_ddr4_0_0_ddr4_mem_intfc.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_1_ddr4_0_0_ddr4_mem_intfc
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/design_1_ddr4_0_0_ddr4_cal_riu.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_1_ddr4_0_0_ddr4_cal_riu
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/ip_top/design_1_ddr4_0_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_1_ddr4_0_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/tb/design_1_ddr4_0_0_microblaze_mcs_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_1_ddr4_0_0_microblaze_mcs
WARNING: [VRFC 10-3609] overwriting previous definition of module 'design_1_ddr4_0_0_microblaze_mcs' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/tb/design_1_ddr4_0_0_microblaze_mcs_0.sv:79]
INFO: [VRFC 10-311] analyzing module microblaze_mcs
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_util_vector_logic_0_4/sim/design_1_util_vector_logic_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_1_util_vector_logic_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/sim/bd_f60c_ila_lib_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_f60c_ila_lib_0
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/bd_f60c_g_inst_0_gigantic_mux.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_f60c_g_inst_0_gigantic_mux
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_f60c_g_inst_0
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_2/sim/bd_f60c_slot_0_aw_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_f60c_slot_0_aw_0
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_3/sim/bd_f60c_slot_0_w_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_f60c_slot_0_w_0
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_4/sim/bd_f60c_slot_0_b_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_f60c_slot_0_b_0
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_5/sim/bd_f60c_slot_0_ar_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_f60c_slot_0_ar_0
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_6/sim/bd_f60c_slot_0_r_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_f60c_slot_0_r_0
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_7/sim/bd_f60c_slot_1_aw_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_f60c_slot_1_aw_0
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_8/sim/bd_f60c_slot_1_w_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_f60c_slot_1_w_0
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_9/sim/bd_f60c_slot_1_b_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_f60c_slot_1_b_0
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_10/sim/bd_f60c_slot_1_ar_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_f60c_slot_1_ar_0
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_11/sim/bd_f60c_slot_1_r_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_f60c_slot_1_r_0
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_12/sim/bd_f60c_slot_2_aw_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_f60c_slot_2_aw_0
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_13/sim/bd_f60c_slot_2_w_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_f60c_slot_2_w_0
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_14/sim/bd_f60c_slot_2_b_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_f60c_slot_2_b_0
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_15/sim/bd_f60c_slot_2_ar_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_f60c_slot_2_ar_0
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_16/sim/bd_f60c_slot_2_r_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_f60c_slot_2_r_0
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_17/sim/bd_f60c_slot_3_aw_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_f60c_slot_3_aw_0
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_18/sim/bd_f60c_slot_3_w_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_f60c_slot_3_w_0
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_19/sim/bd_f60c_slot_3_b_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_f60c_slot_3_b_0
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_20/sim/bd_f60c_slot_3_ar_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_f60c_slot_3_ar_0
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_21/sim/bd_f60c_slot_3_r_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_f60c_slot_3_r_0
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/sim/bd_f60c.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_f60c
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/sim/design_1_system_ila_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_1_system_ila_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/sim/design_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_1
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_1_wrapper
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/tb_design_1_wrapper.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module tb_design_1_wrapper
WARNING: [VRFC 10-8884] decimal constant 5000000000 should be smaller than 2147483648; using 705032704 instead [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/tb_design_1_wrapper.sv:99]
WARNING: [VRFC 10-8884] decimal constant 10000000000 should be smaller than 2147483648; using 1410065408 instead [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/tb_design_1_wrapper.sv:132]
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim/glbl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module glbl
"xvhdl --incr --relax -prj tb_design_1_wrapper_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/axi_datamover_0/sim/axi_datamover_0.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'axi_datamover_0'
INFO: [VRFC 10-163] Analyzing VHDL file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_1/sim/bd_886d_psr0_0.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'bd_886d_psr0_0'
INFO: [VRFC 10-163] Analyzing VHDL file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_2/sim/bd_886d_psr_aclk_0.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'bd_886d_psr_aclk_0'
INFO: [VRFC 10-163] Analyzing VHDL file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_3/sim/bd_886d_psr_aclk1_0.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'bd_886d_psr_aclk1_0'
INFO: [VRFC 10-163] Analyzing VHDL file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_proc_sys_reset_0_0/sim/design_1_proc_sys_reset_0_0.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'design_1_proc_sys_reset_0_0'
INFO: [VRFC 10-163] Analyzing VHDL file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_0/sim/bd_45eb_microblaze_I_0.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'bd_45eb_microblaze_I_0'
INFO: [VRFC 10-163] Analyzing VHDL file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_1/sim/bd_45eb_rst_0_0.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'bd_45eb_rst_0_0'
INFO: [VRFC 10-163] Analyzing VHDL file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_2/sim/bd_45eb_ilmb_0.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'bd_45eb_ilmb_0'
INFO: [VRFC 10-163] Analyzing VHDL file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_3/sim/bd_45eb_dlmb_0.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'bd_45eb_dlmb_0'
INFO: [VRFC 10-163] Analyzing VHDL file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_4/sim/bd_45eb_dlmb_cntlr_0.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'bd_45eb_dlmb_cntlr_0'
INFO: [VRFC 10-163] Analyzing VHDL file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_5/sim/bd_45eb_ilmb_cntlr_0.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'bd_45eb_ilmb_cntlr_0'
INFO: [VRFC 10-163] Analyzing VHDL file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_7/sim/bd_45eb_second_dlmb_cntlr_0.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'bd_45eb_second_dlmb_cntlr_0'
INFO: [VRFC 10-163] Analyzing VHDL file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_8/sim/bd_45eb_second_ilmb_cntlr_0.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'bd_45eb_second_ilmb_cntlr_0'
INFO: [VRFC 10-163] Analyzing VHDL file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_10/sim/bd_45eb_iomodule_0_0.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'bd_45eb_iomodule_0_0'
run_program: Time (s): cpu = 00:00:02 ; elapsed = 00:00:35 . Memory (MB): peak = 1920.188 ; gain = 16.047
INFO: [USF-XSim-69] 'compile' step finished in '36' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim'
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L fifo_generator_v13_2_9 -L lib_pkg_v1_0_3 -L lib_fifo_v1_0_18 -L lib_srl_fifo_v1_0_3 -L lib_cdc_v1_0_2 -L axi_datamover_v5_1_31 -L xlconstant_v1_1_8 -L proc_sys_reset_v5_0_14 -L smartconnect_v1_0 -L axi_infrastructure_v1_1_0 -L axi_register_slice_v2_1_29 -L axi_vip_v1_1_15 -L microblaze_v11_0_12 -L lmb_v10_v3_0_13 -L lmb_bram_if_cntlr_v4_0_23 -L blk_mem_gen_v8_4_7 -L iomodule_v3_1_9 -L util_vector_logic_v2_0_3 -L gigantic_mux -L xlconcat_v2_1_5 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_design_1_wrapper_behav xil_defaultlib.tb_design_1_wrapper xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator v2023.2
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2023.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L fifo_generator_v13_2_9 -L lib_pkg_v1_0_3 -L lib_fifo_v1_0_18 -L lib_srl_fifo_v1_0_3 -L lib_cdc_v1_0_2 -L axi_datamover_v5_1_31 -L xlconstant_v1_1_8 -L proc_sys_reset_v5_0_14 -L smartconnect_v1_0 -L axi_infrastructure_v1_1_0 -L axi_register_slice_v2_1_29 -L axi_vip_v1_1_15 -L microblaze_v11_0_12 -L lmb_v10_v3_0_13 -L lmb_bram_if_cntlr_v4_0_23 -L blk_mem_gen_v8_4_7 -L iomodule_v3_1_9 -L util_vector_logic_v2_0_3 -L gigantic_mux -L xlconcat_v2_1_5 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_design_1_wrapper_behav xil_defaultlib.tb_design_1_wrapper xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-8809] cannot index into scalar type parameter/localparam 'DEBUG_MESSAGES' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv:234]
WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 2 for port 'm_axil_awprot' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/08a1/src/ccsds_uart_axi.sv:190]
WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 2 for port 'm_axil_arprot' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/08a1/src/ccsds_uart_axi.sv:202]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_awid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2822]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_bid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2837]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_arid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2841]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_rid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2851]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_awid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2866]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_bid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2881]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_arid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2885]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_rid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2895]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_awid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2954]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_3_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2960]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_bid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2969]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_arid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2973]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_3_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2978]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_rid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2983]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_4_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3004]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_4_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3022]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_5_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3048]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_5_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3066]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_6_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3092]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_6_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3110]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_7_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3136]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_7_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3154]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_8_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3180]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_8_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3198]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_9_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3224]
WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 4 for port 'slot_9_axi_wstrb' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3229]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_9_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3242]
WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 4 for port 'slot_9_axis_tstrb' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3256]
WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 4 for port 'slot_9_axis_tkeep' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3257]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_10_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3268]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_10_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3286]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_11_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3312]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_11_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3330]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_12_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3356]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_12_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3374]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_13_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3400]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_13_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3418]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_14_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3444]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_14_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3462]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_15_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3488]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_15_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3506]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 4 for port 'sel' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4406]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_awuser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4407]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_wuser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4408]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_buser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4409]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_ruser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4411]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_wuser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4413]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_buser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4414]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_aruser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4415]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_ruser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4416]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_2_axi_awuser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4417]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_2_axi_wuser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4418]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_2_axi_buser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4419]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_2_axi_aruser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4420]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_2_axi_ruser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4421]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_awuser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4422]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_wuser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4423]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_buser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4424]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_aruser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4425]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_ruser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4426]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_wid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4588]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_wid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4593]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_wid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4603]
WARNING: [VRFC 10-5021] port 'mb_reset' is not connected on this instance [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/sim/design_1.v:506]
WARNING: [VRFC 10-5021] port 'mb_reset' is not connected on this instance [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/sim/bd_886d.v:2249]
WARNING: [VRFC 10-5021] port 'mb_reset' is not connected on this instance [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/sim/bd_886d.v:2256]
WARNING: [VRFC 10-5021] port 'mb_reset' is not connected on this instance [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/sim/bd_886d.v:2263]
WARNING: [VRFC 10-3705] select index 2 into 'rank' is out of bounds [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_cal_mc_odt.sv:148]
Completed static elaboration
Starting simulation data flow analysis
WARNING: [XSIM 43-4398] File "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_cal_cplx.sv" Line 856 : The System Verilog Assertion will be ignored as it appears inside another process. This assertion is not yet supported.
WARNING: [XSIM 43-4398] File "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_cal_top.sv" Line 1813 : The System Verilog Assertion will be ignored as it appears inside another process. This assertion is not yet supported.
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_unsigned
Compiling package lib_pkg_v1_0_3.lib_pkg
Compiling package xpm.vcomponents
Compiling package synopsys.attributes
Compiling package ieee.std_logic_misc
Compiling package unisim.vcomponents
Compiling package ieee.vital_timing
Compiling package ieee.vital_primitives
Compiling package unisim.vpkg
Compiling package xpm.$unit_xpm_cdc_sv_220102727
Compiling package xpm.axi_xil_sb_pkg_xpm_nsu
Compiling package xpm.axi_data_integrity_checker_xpm_n...
Compiling package xpm.xpm_axi_data_integrity_checker_n...
Compiling package xpm.xpm_axi_xil_sb_pkg_nmu
Compiling package xil_defaultlib.ccsds122p_pkg
Compiling package smartconnect_v1_0.sc_util_v1_0_4_pkg
Compiling module xil_defaultlib.ccsds122_axil_slave
Compiling module xil_defaultlib.design_1_ccsds122_axil_slave_0_0
Compiling module xpm.xpm_fifo_rst_default
Compiling module xpm.xpm_fifo_reg_bit
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=8...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=7...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=2...
Compiling module xpm.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
Compiling module xpm.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling architecture implementation of entity lib_fifo_v1_0_18.sync_fifo_fg [\sync_fifo_fg(c_family="kintexup...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_sfifo_autord [\axi_datamover_sfifo_autord(c_dw...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_rd_sf [\axi_datamover_rd_sf(c_sf_fifo_d...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_skid_buf [\axi_datamover_skid_buf(c_wdata_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_reset [axi_datamover_reset_default]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=4,c_dwidth=8...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=8,c_dep...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=8,c_depth=4...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=8,c...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.cntr_incr_decr_addn_f [\cntr_incr_decr_addn_f(c_size=3,...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=4,c_dwidth=6...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=68,c_de...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=68,c_depth=...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=68,...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_cmd_status [\axi_datamover_cmd_status(c_fami...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_rd_status_cntl [axi_datamover_rd_status_cntl_def...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_strb_gen2 [\axi_datamover_strb_gen2(c_strb_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_strb_gen2 [\axi_datamover_strb_gen2(c_op_mo...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_pcc [\axi_datamover_pcc(c_is_mm2s=1,c...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=3,c_dwidth=5...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=59,c_de...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=59,c_depth=...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=59,...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_addr_cntl [\axi_datamover_addr_cntl(c_addr_...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=3,c_dwidth=5...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=55,c_de...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=55,c_depth=...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=55,...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_rdmux [\axi_datamover_rdmux(c_sel_addr_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_rddata_cntl [\axi_datamover_rddata_cntl(c_ali...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_mm2s_full_wrap [\axi_datamover_mm2s_full_wrap(c_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_ibttcc [\axi_datamover_ibttcc(c_sf_xfer_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_dre_mux2_1_x_n [\axi_datamover_dre_mux2_1_x_n(c_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_dre_mux4_1_x_n [\axi_datamover_dre_mux4_1_x_n(c_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_dre_mux8_1_x_n [\axi_datamover_dre_mux8_1_x_n(c_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_s2mm_dre [axi_datamover_s2mm_dre_default]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_ms_strb_set [axi_datamover_ms_strb_set_defaul...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_mssai_skid_buf [\axi_datamover_mssai_skid_buf(c_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_strb_gen2 [axi_datamover_strb_gen2_default]
Compiling architecture working of entity axi_datamover_v5_1_31.axi_datamover_slice [\axi_datamover_slice(c_data_widt...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.cntr_incr_decr_addn_f [\cntr_incr_decr_addn_f(c_size=5,...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=16,c_dwidth=...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=14,c_fa...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=14,c_family...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=14,...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_s2mm_scatter [\axi_datamover_s2mm_scatter(c_en...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=4,c_dwidth=3...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=38,c_de...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=38,c_depth=...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=38,...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_s2mm_realign [\axi_datamover_s2mm_realign(c_en...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_stbs_set [axi_datamover_stbs_set_default]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_stbs_set [\axi_datamover_stbs_set(c_strobe...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_skid_buf [\axi_datamover_skid_buf(c_wdata_...]
Compiling module xpm.xpm_fifo_rst_default_1
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=5...
Compiling module xpm.xpm_counter_updn
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=1...
Compiling module xpm.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling architecture implementation of entity lib_fifo_v1_0_18.sync_fifo_fg [\sync_fifo_fg(c_family="kintexup...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_sfifo_autord [\axi_datamover_sfifo_autord(c_dw...]
Compiling module xpm.xpm_fifo_rst_default_2
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
Compiling module xpm.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling architecture implementation of entity lib_fifo_v1_0_18.sync_fifo_fg [\sync_fifo_fg(c_family="kintexup...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_sfifo_autord [\axi_datamover_sfifo_autord(c_dw...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_indet_btt [\axi_datamover_indet_btt(c_ibtt_...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=4,c_dwidth=3...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=32,c_de...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=32,c_depth=...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_family="ki...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_cmd_status [\axi_datamover_cmd_status(c_sts_...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=6,c_dwidth=3...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=30,c_de...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=30,c_depth=...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=30,...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.cntr_incr_decr_addn_f [\cntr_incr_decr_addn_f(c_size=4,...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=6,c_dwidth=2...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=2,c_dep...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=2,c_depth=6...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=2,c...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_wr_status_cntl [\axi_datamover_wr_status_cntl(c_...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=4,c_dwidth=5...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=59,c_de...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=59,c_depth=...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=59,...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_addr_cntl [\axi_datamover_addr_cntl(c_addr_...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=4,c_dwidth=5...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=53,c_de...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=53,c_depth=...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=53,...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_wrdata_cntl [\axi_datamover_wrdata_cntl(c_rea...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_wr_demux [\axi_datamover_wr_demux(c_sel_ad...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_skid2mm_buf [\axi_datamover_skid2mm_buf(c_mda...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_s2mm_full_wrap [\axi_datamover_s2mm_full_wrap(c_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover [\axi_datamover(c_include_mm2s=1,...]
Compiling architecture axi_datamover_0_arch of entity xil_defaultlib.axi_datamover_0 [axi_datamover_0_default]
Compiling module xil_defaultlib.ccsds122_addr_calc(AXI_ADDR_W=32...
Compiling module xil_defaultlib.ila_1
Compiling module xil_defaultlib.ccsds122_stream_ctrl(AXI_ADDR_W=...
Compiling module fifo_generator_v13_2_9.fifo_generator_v13_2_9_bhv_ver_s...
Compiling module fifo_generator_v13_2_9.fifo_generator_v13_2_9_bhv_ver_p...
Compiling module fifo_generator_v13_2_9.fifo_generator_v13_2_9_CONV_VER(...
Compiling module fifo_generator_v13_2_9.fifo_generator_vlog_beh(C_COMMON...
Compiling module xil_defaultlib.fifo_generator_0
Compiling module xil_defaultlib.ccsds122_bubble_removal_ctrl(AXI...
Compiling module xil_defaultlib.ccsds122p_ingress_frontend_defau...
Compiling module xil_defaultlib.ccsds122p_dwt_m97_lift_core(COEF...
Compiling module xil_defaultlib.ccsds122p_dwt_h_stage(ROW_SAMPLE...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=61...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xil_defaultlib.ccsds122p_dwt_v_stage(STAGE_SAMP...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=30...
Compiling module xil_defaultlib.ccsds122p_dwt_ll_row_order(STAGE...
Compiling module xil_defaultlib.ccsds122p_dwt_split_stage(STAGE_...
Compiling module xil_defaultlib.ccsds122p_dwt_l0(ENABLE_PROTOCOL...
Compiling module xil_defaultlib.ccsds122p_dwt_h_stage(ROW_SAMPLE...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=30...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xil_defaultlib.ccsds122p_dwt_v_stage(STAGE_SAMP...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=15...
Compiling module xil_defaultlib.ccsds122p_dwt_ll_row_order(STAGE...
Compiling module xil_defaultlib.ccsds122p_dwt_split_stage(STAGE_...
Compiling module xil_defaultlib.ccsds122p_dwt_l1(ENABLE_PROTOCOL...
Compiling module xil_defaultlib.ccsds122p_dwt_h_stage(ROW_SAMPLE...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=15...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xil_defaultlib.ccsds122p_dwt_v_stage(STAGE_SAMP...
Compiling module xil_defaultlib.ccsds122p_dwt_l2(ENABLE_PROTOCOL...
Compiling module xil_defaultlib.ccsds122p_dwt_merge(ENABLE_PROTO...
Compiling module xil_defaultlib.ccsds122p_subband_router(ENABLE_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=15...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram_masked(DATA...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=81...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xil_defaultlib.ccsds122p_segment_reorder(ENABLE...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=24...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xil_defaultlib.ccsds122p_segment_bank
Compiling module xil_defaultlib.ccsds122p_segment_fill(ENABLE_PR...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=25...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xil_defaultlib.ccsds122p_block_state_ram(DATA_W...
Compiling module xil_defaultlib.ccsds122p_segment_state_bank
Compiling module xil_defaultlib.ccsds122p_dc_option_select
Compiling module xil_defaultlib.ccsds122p_dc_code_emitter
Compiling module xil_defaultlib.ccsds122p_dc_entropy_encoder
Compiling module xil_defaultlib.ccsds122p_ac_depth_option_select...
Compiling module xil_defaultlib.ccsds122p_ac_depth_code_emitter_...
Compiling module xil_defaultlib.ccsds122p_ac_depth_encoder_defau...
Compiling module xil_defaultlib.ccsds122p_ac_stage0_dc_emit
Compiling module xil_defaultlib.ccsds122p_segment_block_reader
Compiling module xil_defaultlib.ccsds122p_stage_block_scan(FIXED...
Compiling module xil_defaultlib.ccsds122p_stage_pattern_map
Compiling module xil_defaultlib.ccsds122p_stage_option_select(US...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=15...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=14...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=51...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=33...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xil_defaultlib.ccsds122p_stage_rice_emitter
Compiling module xil_defaultlib.ccsds122p_stage_symbol_emit
Compiling module xil_defaultlib.ccsds122p_stage_refine_emit
Compiling module xil_defaultlib.ccsds122p_ac_bitplane_cached_com...
Compiling module xil_defaultlib.ccsds122p_ac_bitplane_gaggle_enc...
Compiling module xil_defaultlib.ccsds122p_segment_encoder_core
Compiling module xil_defaultlib.ccsds122p_bitstream_packer(ENABL...
Compiling module xil_defaultlib.ccsds122p_backend_lane(ENABLE_PR...
Compiling module xil_defaultlib.ccsds122p_bit_length24(BITS_W=32...
Compiling module xil_defaultlib.ccsds122p_segment_bitdepth
Compiling module xil_defaultlib.ccsds122p_header_writer_default
Compiling module xil_defaultlib.ccsds122p_segment_stats
Compiling module xil_defaultlib.ccsds122p_dc_seed
Compiling module xil_defaultlib.ccsds122p_block_state_pack_defau...
Compiling module xil_defaultlib.ccsds122p_segment_first_pass(OWN...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=23...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xil_defaultlib.ccsds122p_encoded_segment_reorde...
Compiling module xil_defaultlib.ccsds122p_backend_farm(LANE_COUN...
Compiling module xil_defaultlib.top_bpe_encoder(BACKEND_LANE_COU...
Compiling module xil_defaultlib.ccsds122_compression_top(AXI_ADD...
Compiling module xil_defaultlib.ccsds122_datamover(MEMORY_BLOCK_...
Compiling module xil_defaultlib.design_1_ccsds122_datamover_0_0
Compiling module xil_defaultlib.uart_rx
Compiling module xil_defaultlib.uart_tx
Compiling module xil_defaultlib.vio_0
Compiling module xil_defaultlib.axi_uart_upload_default
Compiling module xil_defaultlib.ccsds_uart_axi_default
Compiling module xil_defaultlib.design_1_ccsds_uart_axi_0_0
Compiling module unisims_ver.BUFG
Compiling module unisims_ver.MMCME4_ADV(CLKFBOUT_MULT_F=7.0,C...
Compiling module xil_defaultlib.ddr4_v2_2_20_infrastructure(CLKI...
Compiling module unisims_ver.OBUF
Compiling module unisims_ver.IBUFDS(IBUF_LOW_PWR="FALSE")
Compiling module unisims_ver.PLLE4_ADV(CLKFBOUT_MULT=4,CLKFBO...
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_pll(PLL_WIDTH=2,...
Compiling module unisims_ver.HPIO_VREF(VREF_CNTR="FABRIC_RANG...
Compiling module unisims_ver.IOBUFE3_default
Compiling module unisims_ver.IOBUFDS
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_iob_byte(IOBTYPE...
Compiling module unisims_ver.OBUFDS
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_iob_byte(IOBTYPE...
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_iob_byte(IOBTYPE...
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_iob_byte(IOBTYPE...
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_iob(BYTES=6,IOBT...
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_fifo_sv(DEPTH=16...
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_bitslice_behav
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_xiphy_behav(BYTE...
Compiling module xil_defaultlib.design_1_ddr4_0_0_phy_ddr4_defau...
Compiling module xil_defaultlib.design_1_ddr4_0_0_phy
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_group(ABITS=17,A...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_act_rank(tFAW=28...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_act_timer(tFAW=2...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_arb_a
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_wtr(tWTR_L=6,tWT...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_rd_wr(tWTR_L=6,t...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_arb_c_default
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_arb_p
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_cmd_mux_ap(ABITS...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_arb_mux_p(ABITS=...
WARNING: [VRFC 10-3705] select index 2 into 'rank' is out of bounds [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_cal_mc_odt.sv:148]
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_mc_odt(ODTBITS=...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_ctl(ABITS=17,BGB...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_cmd_mux_c
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_ref(LR_WIDTH=1,S...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_periodic
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_ecc(TCQ=0.1,PAYL...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc(ABITS=17,BGBITS=...
Compiling module xil_defaultlib.ddr4_v2_2_20_ui_cmd(TCQ=100.0,AD...
Compiling module unisims_ver.RAM32M
Compiling module xil_defaultlib.ddr4_v2_2_20_ui_wr_data(TCQ=100....
Compiling module xil_defaultlib.ddr4_v2_2_20_ui_rd_data(TCQ=100....
Compiling module xil_defaultlib.ddr4_v2_2_20_ui(TCQ=100.0,ADDR_W...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_debug_microblaz...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_cplx_data_defau...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_cplx(ABITS=17,B...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_addr_decode(DRA...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_config_rom(MEM0...
Compiling module xil_defaultlib.ddr4_v2_2_20_chipscope_xsdb_slav...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_sync(WIDTH=1)
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_sync(WIDTH=16)
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_sync(WIDTH=9)
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_xsdb_arbiter
Compiling module xil_defaultlib.ddr4_v2_2_20_bram_tdp(INIT=2304'...
Compiling module xil_defaultlib.ddr4_v2_2_20_cfg_mem_mod(SIZE=36...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_xsdb_bram(DBYTE...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal(ABITS=17,BGBITS...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_rd_en(RL=32'b01...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_read(RL=32'b010...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_wr_bit
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_wr_byte_default
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_write(WL=32'b01...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_pi(RL=32'b01011...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_top(ABITS=17,BG...
Compiling module unisims_ver.VCC
Compiling module unisims_ver.GND
Compiling module unisims_ver.FDRE_default
Compiling module unisims_ver.FDR
Compiling module unisims_ver.FDSE_default
Compiling module unisims_ver.FDS
Compiling module unisims_ver.FD
Compiling module unisims_ver.FDRE(INIT=1'b1)
Compiling module unisims_ver.FD(INIT=1'b1)
Compiling module unisims_ver.RAM32X1D
Compiling module unisims_ver.FDE
Compiling module unisims_ver.LUT6_2
Compiling module unisims_ver.MUXCY
Compiling module unisims_ver.MUXCY_L
Compiling module unisims_ver.XORCY
Compiling module unisims_ver.x_lut2_mux4
Compiling module unisims_ver.LUT2
Compiling module unisims_ver.MULT_AND
Compiling module unisims_ver.x_lut3_mux8
Compiling module unisims_ver.LUT3
Compiling module unisims_ver.LUT4
Compiling module unisims_ver.LUT6
Compiling module unisims_ver.MUXF5
Compiling module unisims_ver.SRL16E_default
Compiling module unisims_ver.LUT5
Compiling module unisims_ver.FDSE(INIT=1'b0)
Compiling module unisims_ver.x_lut1_mux2
Compiling module unisims_ver.LUT1
Compiling module unisims_ver.MUXF7
Compiling module unisims_ver.INV
Compiling module unisims_ver.RB36_INTERNAL_VLOG(READ_WIDTH_A=...
Compiling module unisims_ver.RAMB36E1(READ_WIDTH_A=2,READ_WID...
Compiling module unisims_ver.RAMB36(READ_WIDTH_A=2,READ_WIDTH...
Compiling module xil_defaultlib.microblaze_mcs
Compiling module xil_defaultlib.design_1_ddr4_0_0_microblaze_mcs
Compiling module xil_defaultlib.design_1_ddr4_0_0_ddr4_cal_riu
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_sync(WIDTH=1,TC...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_sync(WIDTH=32,T...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_sync(WIDTH=20,T...
Compiling module xil_defaultlib.design_1_ddr4_0_0_ddr4_mem_intfc...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_register_slice(...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_register_slice(...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_register_slice(...
Compiling module xil_defaultlib.ddr4_v2_2_20_command_fifo(C_FAMI...
Compiling module xil_defaultlib.ddr4_v2_2_20_a_upsizer(C_AXI_ID_...
Compiling module xil_defaultlib.ddr4_v2_2_20_w_upsizer(C_S_AXI_D...
Compiling module xil_defaultlib.ddr4_v2_2_20_r_upsizer(C_AXI_ID_...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_upsizer(C_AXI_I...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_register_slice(...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_incr_cmd(C_AXI_...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_wrap_cmd(C_AXI_...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_cmd_translator(...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_wr_cmd_fsm
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_aw_channel(C_ID...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_w_channel(C_DAT...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_fifo(C_WIDTH=1,...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_b_channel(C_ID_...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_incr_cmd(C_AXI_...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_wrap_cmd(C_AXI_...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_cmd_translator(...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_cmd_fsm(C_MC_RD...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_ar_channel(C_ID...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_fifo(C_WIDTH=25...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_fifo(C_WIDTH=4,...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_r_channel(C_ID_...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_cmd_arbiter(C_M...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi(C_S_AXI_ID_WIDT...
Compiling module xil_defaultlib.design_1_ddr4_0_0_ddr4_default
Compiling module xil_defaultlib.design_1_ddr4_0_0
Compiling module xil_defaultlib.design_1_ila_0_0
Compiling architecture fdre_v of entity unisim.FDRE [fdre_default]
Compiling architecture fdre_v of entity unisim.FDRE [\FDRE(init='1')\]
Compiling architecture fdr_v of entity unisim.FDR [fdr_default]
Compiling architecture implementation of entity lib_cdc_v1_0_2.cdc_sync [\cdc_sync(c_vector_width=2,c_mtb...]
Compiling architecture srl16e_v of entity unisim.SRL16E [\SRL16E(init="1111111111111111")...]
Compiling architecture srl16_v of entity unisim.SRL16 [\SRL16(init="1111111111111111")(...]
Compiling architecture imp of entity proc_sys_reset_v5_0_14.lpf [\lpf(c_ext_rst_width=4,c_aux_rst...]
Compiling architecture imp of entity proc_sys_reset_v5_0_14.upcnt_n [\upcnt_n(c_size=6)\]
Compiling architecture imp of entity proc_sys_reset_v5_0_14.sequence_psr [sequence_psr_default]
Compiling architecture imp of entity proc_sys_reset_v5_0_14.proc_sys_reset [\proc_sys_reset(c_family="kintex...]
Compiling architecture design_1_proc_sys_reset_0_0_arch of entity xil_defaultlib.design_1_proc_sys_reset_0_0 [design_1_proc_sys_reset_0_0_defa...]
Compiling module xlconstant_v1_1_8.xlconstant_v1_1_8_xlconstant(CON...
Compiling module xil_defaultlib.bd_886d_one_0
Compiling architecture imp of entity proc_sys_reset_v5_0_14.lpf [\lpf(c_ext_rst_width=4,c_aux_rst...]
Compiling architecture imp of entity proc_sys_reset_v5_0_14.proc_sys_reset [\proc_sys_reset(c_family="kintex...]
Compiling architecture bd_886d_psr0_0_arch of entity xil_defaultlib.bd_886d_psr0_0 [bd_886d_psr0_0_default]
Compiling architecture bd_886d_psr_aclk_0_arch of entity xil_defaultlib.bd_886d_psr_aclk_0 [bd_886d_psr_aclk_0_default]
Compiling architecture bd_886d_psr_aclk1_0_arch of entity xil_defaultlib.bd_886d_psr_aclk1_0 [bd_886d_psr_aclk1_0_default]
Compiling module xil_defaultlib.clk_map_imp_1WP46Y0
Compiling module xpm.xpm_cdc_async_rst(DEST_SYNC_FF=3...
Compiling module xil_defaultlib.bd_886d_m00e_0
Compiling module xil_defaultlib.m00_exit_pipeline_imp_4816GJ
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=52...
Compiling module xil_defaultlib.bd_886d_m00arn_0
Compiling module xil_defaultlib.bd_886d_m00awn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=67...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=32...
Compiling module xil_defaultlib.bd_886d_m00bn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=48...
Compiling module xil_defaultlib.bd_886d_m00rn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=4,...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=57...
Compiling module xil_defaultlib.bd_886d_m00wn_0
Compiling module xil_defaultlib.m00_nodes_imp_QDFR33
Compiling module xil_defaultlib.bd_886d_m00s2a_0
Compiling module xil_defaultlib.bd_886d_m01e_0
Compiling module xil_defaultlib.m01_exit_pipeline_imp_6OCSAB
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=32...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=52...
Compiling module xil_defaultlib.bd_886d_m01arn_0
Compiling module xil_defaultlib.bd_886d_m01awn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=67...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=32...
Compiling module xil_defaultlib.bd_886d_m01bn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=48...
Compiling module xil_defaultlib.bd_886d_m01rn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=57...
Compiling module xil_defaultlib.bd_886d_m01wn_0
Compiling module xil_defaultlib.m01_nodes_imp_1HTXBQH
Compiling module xil_defaultlib.bd_886d_m01s2a_0
Compiling module xil_defaultlib.bd_886d_s00a2s_0
Compiling module xil_defaultlib.bd_886d_s00mmu_0
Compiling module xil_defaultlib.bd_886d_s00sic_0
Compiling module xil_defaultlib.bd_886d_s00tr_0
Compiling module xil_defaultlib.s00_entry_pipeline_imp_12V3TGW
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=60...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=46...
Compiling module xil_defaultlib.bd_886d_sarn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=54...
Compiling module xil_defaultlib.bd_886d_srn_0
Compiling module xil_defaultlib.s00_nodes_imp_16MUXNU
Compiling module xil_defaultlib.bd_886d_s01a2s_0
Compiling module xil_defaultlib.bd_886d_s01mmu_0
Compiling module xil_defaultlib.bd_886d_s01sic_0
Compiling module xil_defaultlib.bd_886d_s01tr_0
Compiling module xil_defaultlib.s01_entry_pipeline_imp_6HKV8K
Compiling module xil_defaultlib.bd_886d_sawn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=89...
Compiling module xil_defaultlib.bd_886d_sbn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=51...
Compiling module xil_defaultlib.bd_886d_swn_0
Compiling module xil_defaultlib.s01_nodes_imp_1AH57G
Compiling module xil_defaultlib.bd_886d_s02a2s_0
Compiling module xil_defaultlib.bd_886d_s02mmu_0
Compiling module xil_defaultlib.bd_886d_s02sic_0
Compiling module xil_defaultlib.bd_886d_s02tr_0
Compiling module xil_defaultlib.s02_entry_pipeline_imp_R26R6H
Compiling module xil_defaultlib.bd_886d_sarn_1
Compiling module xil_defaultlib.bd_886d_sawn_1
Compiling module xil_defaultlib.bd_886d_sbn_1
Compiling module xil_defaultlib.bd_886d_srn_1
Compiling module xil_defaultlib.bd_886d_swn_1
Compiling module xil_defaultlib.s02_nodes_imp_XIDFT3
Compiling module xil_defaultlib.bd_886d_s03a2s_0
Compiling module xil_defaultlib.bd_886d_s03mmu_0
Compiling module xil_defaultlib.bd_886d_s03sic_0
Compiling module xil_defaultlib.bd_886d_s03tr_0
Compiling module xil_defaultlib.s03_entry_pipeline_imp_1XMQ8JX
Compiling module xil_defaultlib.bd_886d_sarn_2
Compiling module xil_defaultlib.bd_886d_sawn_2
Compiling module xil_defaultlib.bd_886d_sbn_2
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=54...
Compiling module xil_defaultlib.bd_886d_srn_2
Compiling module xil_defaultlib.bd_886d_swn_2
Compiling module xil_defaultlib.s03_nodes_imp_1RRAM9D
Compiling module xil_defaultlib.bd_886d_arsw_0
Compiling module xil_defaultlib.bd_886d_awsw_0
Compiling module xil_defaultlib.bd_886d_bsw_0
Compiling module xil_defaultlib.bd_886d_rsw_0
Compiling module xil_defaultlib.bd_886d_wsw_0
Compiling module xil_defaultlib.switchboards_imp_1V8ZM66
Compiling module xil_defaultlib.bd_886d
Compiling module xil_defaultlib.design_1_smartconnect_0_1
Compiling module xil_defaultlib.bd_f60c_g_inst_0_gigantic_mux(C_...
Compiling module xil_defaultlib.bd_f60c_g_inst_0
Compiling module xil_defaultlib.bd_f60c_ila_lib_0
Compiling module xlconcat_v2_1_5.xlconcat_v2_1_5_xlconcat_default
Compiling module xil_defaultlib.bd_f60c_slot_0_ar_0
Compiling module xil_defaultlib.bd_f60c_slot_0_aw_0
Compiling module xil_defaultlib.bd_f60c_slot_0_b_0
Compiling module xlconcat_v2_1_5.xlconcat_v2_1_5_xlconcat(dout_wi...
Compiling module xil_defaultlib.bd_f60c_slot_0_r_0
Compiling module xil_defaultlib.bd_f60c_slot_0_w_0
Compiling module xil_defaultlib.bd_f60c_slot_1_ar_0
Compiling module xil_defaultlib.bd_f60c_slot_1_aw_0
Compiling module xil_defaultlib.bd_f60c_slot_1_b_0
Compiling module xil_defaultlib.bd_f60c_slot_1_r_0
Compiling module xil_defaultlib.bd_f60c_slot_1_w_0
Compiling module xil_defaultlib.bd_f60c_slot_2_ar_0
Compiling module xil_defaultlib.bd_f60c_slot_2_aw_0
Compiling module xil_defaultlib.bd_f60c_slot_2_b_0
Compiling module xil_defaultlib.bd_f60c_slot_2_r_0
Compiling module xil_defaultlib.bd_f60c_slot_2_w_0
Compiling module xil_defaultlib.bd_f60c_slot_3_ar_0
Compiling module xil_defaultlib.bd_f60c_slot_3_aw_0
Compiling module xil_defaultlib.bd_f60c_slot_3_b_0
Compiling module xil_defaultlib.bd_f60c_slot_3_r_0
Compiling module xil_defaultlib.bd_f60c_slot_3_w_0
Compiling module xil_defaultlib.bd_f60c
Compiling module xil_defaultlib.design_1_system_ila_0_0
Compiling module util_vector_logic_v2_0_3.util_vector_logic_v2_0_3_util_ve...
Compiling module xil_defaultlib.design_1_util_vector_logic_0_4
Compiling module xil_defaultlib.design_1
Compiling module xil_defaultlib.design_1_wrapper
Compiling module xil_defaultlib.tb_design_1_wrapper
Compiling module xil_defaultlib.glbl
Built simulation snapshot tb_design_1_wrapper_behav
run_program: Time (s): cpu = 00:00:03 ; elapsed = 00:01:06 . Memory (MB): peak = 1921.184 ; gain = 0.996
INFO: [USF-XSim-69] 'elaborate' step finished in '65' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_design_1_wrapper_behav -key {Behavioral:sim_1:Functional:tb_design_1_wrapper} -tclbatch {tb_design_1_wrapper.tcl} -protoinst "protoinst_files/bd_886d.protoinst" -protoinst "protoinst_files/bd_45eb.protoinst" -protoinst "protoinst_files/bd_f60c.protoinst" -protoinst "protoinst_files/design_1.protoinst" -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/bd_886d.protoinst
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m00_exit_pipeline/m00_exit/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m00_exit_pipeline/m00_exit/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m00_exit_pipeline/m_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m00_exit_pipeline/s_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m00_nodes/m00_aw_node/M_AXIS_ARB
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m00_nodes/m00_w_node/S_AXIS_ARB
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m00_sc2axi/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m01_exit_pipeline/m01_exit/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m01_exit_pipeline/m01_exit/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m01_exit_pipeline/m_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m01_exit_pipeline/s_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m01_nodes/m01_aw_node/M_AXIS_ARB
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m01_nodes/m01_w_node/S_AXIS_ARB
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m01_sc2axi/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_axi2sc/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/m_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/s00_mmu/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/s00_mmu/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/s00_si_converter/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/s00_si_converter/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/s00_transaction_regulator/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/s00_transaction_regulator/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/s_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_axi2sc/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/m_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/s01_mmu/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/s01_mmu/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/s01_si_converter/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/s01_si_converter/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/s01_transaction_regulator/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/s01_transaction_regulator/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/s_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_axi2sc/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_entry_pipeline/m_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_entry_pipeline/s02_mmu/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_entry_pipeline/s02_mmu/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_entry_pipeline/s02_si_converter/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_entry_pipeline/s02_si_converter/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_entry_pipeline/s02_transaction_regulator/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_entry_pipeline/s02_transaction_regulator/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_entry_pipeline/s_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_axi2sc/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_entry_pipeline/m_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_entry_pipeline/s03_mmu/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_entry_pipeline/s03_mmu/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_entry_pipeline/s03_si_converter/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_entry_pipeline/s03_si_converter/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_entry_pipeline/s03_transaction_regulator/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_entry_pipeline/s03_transaction_regulator/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_entry_pipeline/s_axi
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/bd_45eb.protoinst
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/bd_45eb.protoinst for the following reason(s):
There are no instances of module "bd_45eb" in the design.
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/bd_f60c.protoinst
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_1.protoinst
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//ccsds122_axil_slave_0/s_axil
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//ccsds122_datamover_0/m_axi_mm2s
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//ccsds122_datamover_0/m_axi_s2mm
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//ccsds_uart_axi_0/m_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//ccsds_uart_axi_0/m_axil
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//ddr4_0/C0_DDR4_S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//smartconnect_0/M00_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//smartconnect_0/M01_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//smartconnect_0/S00_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//smartconnect_0/S01_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//smartconnect_0/S02_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//smartconnect_0/S03_AXI
Time resolution is 1 ps
source tb_design_1_wrapper.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
==== TB: Waiting for DDR4 calib... ====
$finish called at time : 0 fs : File "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/tb_design_1_wrapper.sv" Line 99
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_design_1_wrapper_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:14 ; elapsed = 00:01:50 . Memory (MB): peak = 2003.656 ; gain = 99.516
restart
INFO: [Wavedata 42-604] Simulation restarted
run 7 ms
==== TB: Waiting for DDR4 calib... ====
$finish called at time : 0 fs : File "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/tb_design_1_wrapper.sv" Line 99
run 7 ms
[TB] DDR4 calib done @ 0 ps
[2/6] Config registers
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. tb_design_1_wrapper.u_dut.design_1_i.ccsds122_datamover_0.inst.u_datamover.U0.gen_s2mm_full.I_S2MM_FULL_WRAPPER.gen_enable_indet_btt_sf.I_INDET_BTT.I_XD_FIFO.non_blk_mem.I_SYNC_FIFOGEN_FIFO.xpm_fifo_instance.xpm_fifo_sync_inst.xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/ccsds122_datamover_0/inst/u_datamover/U0/gen_s2mm_full/I_S2MM_FULL_WRAPPER/gen_enable_indet_btt_sf/I_INDET_BTT/I_XD_FIFO/non_blk_mem/I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance/xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial302_83 Scope: tb_design_1_wrapper.u_dut.design_1_i.ccsds122_datamover_0.inst.u_datamover.U0.gen_s2mm_full.I_S2MM_FULL_WRAPPER.gen_enable_indet_btt_sf.I_INDET_BTT.I_XD_FIFO.non_blk_mem.I_SYNC_FIFOGEN_FIFO.xpm_fifo_instance.xpm_fifo_sync_inst.xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 506
[TB] Reset released @ 2997 ps
Warning: [Unisim MMCME4_ADV-12] RST at time 8809 must be asserted at least for 1.5 ns (actual 1.020 ns). Instance tb_design_1_wrapper.u_dut.design_1_i.ddr4_0.inst.u_ddr4_infrastructure.\gen_mmcme4.u_mmcme_adv_inst
Warning: [Unisim MMCME4_ADV-20] Input CLKIN1 period and attribute CLKIN1_PERIOD are not same. Instance tb_design_1_wrapper.u_dut.design_1_i.ddr4_0.inst.u_ddr4_infrastructure.\gen_mmcme4.u_mmcme_adv_inst
Info: [Unisim HPIO_VREF-1] Fabric Tune Value changed to 0011111. Instance: tb_design_1_wrapper.u_dut.design_1_i.ddr4_0.inst.u_ddr4_mem_intfc.u_mig_ddr4_phy.inst.u_ddr_iob.\genByte[0].u_ddr_iob_byte .\genblk1.genVref.u_hpio_vref
Info: [Unisim HPIO_VREF-1] Fabric Tune Value changed to 0011111. Instance: tb_design_1_wrapper.u_dut.design_1_i.ddr4_0.inst.u_ddr4_mem_intfc.u_mig_ddr4_phy.inst.u_ddr_iob.\genByte[3].u_ddr_iob_byte .\genblk1.genVref.u_hpio_vref
Info: [Unisim HPIO_VREF-1] Fabric Tune Value changed to 0011111. Instance: tb_design_1_wrapper.u_dut.design_1_i.ddr4_0.inst.u_ddr4_mem_intfc.u_mig_ddr4_phy.inst.u_ddr_iob.\genByte[4].u_ddr_iob_byte .\genblk1.genVref.u_hpio_vref
Info: [Unisim HPIO_VREF-1] Fabric Tune Value changed to 0011111. Instance: tb_design_1_wrapper.u_dut.design_1_i.ddr4_0.inst.u_ddr4_mem_intfc.u_mig_ddr4_phy.inst.u_ddr_iob.\genByte[5].u_ddr_iob_byte .\genblk1.genVref.u_hpio_vref
Warning: [Unisim PLLE4_ADV-10] input CLKIN period (14.000000) and attribute CLKIN_PERIOD (5.000000) are not same. Instance tb_design_1_wrapper.u_dut.design_1_i.ddr4_0.inst.u_ddr4_mem_intfc.u_mig_ddr4_phy.inst.u_ddr4_phy_pll.\plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER .
Warning: [Unisim PLLE4_ADV-10] input CLKIN period (14.000000) and attribute CLKIN_PERIOD (5.000000) are not same. Instance tb_design_1_wrapper.u_dut.design_1_i.ddr4_0.inst.u_ddr4_mem_intfc.u_mig_ddr4_phy.inst.u_ddr4_phy_pll.\plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER .
run: Time (s): cpu = 00:00:04 ; elapsed = 00:00:26 . Memory (MB): peak = 2046.613 ; gain = 22.496
close_sim
INFO: xsimkernel Simulation Memory Usage: 97572 KB (Peak: 97572 KB), Simulation CPU Usage: 25218 ms
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-12493] Simulation top is 'tb_design_1_wrapper'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
Generating merged BMM file for the design top 'tb_design_1_wrapper'...
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2023.2/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2023.2/data/xsim/xsim.ini' copied to run dir:'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim'
INFO: [SIM-utils-50] Design contains embedded sources, generating MEM files for simulation...
Generating merged BMM file for the design top 'tb_design_1_wrapper'...
WARNING: [Memdata 28-361] Design is having concatenated BRAM controllers(heterogenous memory), this configuration is not supported by Updatemem for current device part. Only the first BRAM controller will be added to .MMI and used by Updatemem to update the bitstream with new data.
Generating merged BMM file for the design top 'tb_design_1_wrapper'...
INFO: [SIM-utils-54] Inspecting design source files for 'tb_design_1_wrapper' in fileset 'sim_1'...
INFO: [SIM-utils-43] Exported 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim/sc_xtlm_design_1_smartconnect_0_1.mem'
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim'
"xvlog --incr --relax -L uvm -L axi_vip_v1_1_15 -L smartconnect_v1_0 -L xilinx_vip -prj tb_design_1_wrapper_vlog.prj"
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/tb_design_1_wrapper.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module tb_design_1_wrapper
"xvhdl --incr --relax -prj tb_design_1_wrapper_vhdl.prj"
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim'
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L fifo_generator_v13_2_9 -L lib_pkg_v1_0_3 -L lib_fifo_v1_0_18 -L lib_srl_fifo_v1_0_3 -L lib_cdc_v1_0_2 -L axi_datamover_v5_1_31 -L xlconstant_v1_1_8 -L proc_sys_reset_v5_0_14 -L smartconnect_v1_0 -L axi_infrastructure_v1_1_0 -L axi_register_slice_v2_1_29 -L axi_vip_v1_1_15 -L microblaze_v11_0_12 -L lmb_v10_v3_0_13 -L lmb_bram_if_cntlr_v4_0_23 -L blk_mem_gen_v8_4_7 -L iomodule_v3_1_9 -L util_vector_logic_v2_0_3 -L gigantic_mux -L xlconcat_v2_1_5 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_design_1_wrapper_behav xil_defaultlib.tb_design_1_wrapper xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator v2023.2
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2023.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L fifo_generator_v13_2_9 -L lib_pkg_v1_0_3 -L lib_fifo_v1_0_18 -L lib_srl_fifo_v1_0_3 -L lib_cdc_v1_0_2 -L axi_datamover_v5_1_31 -L xlconstant_v1_1_8 -L proc_sys_reset_v5_0_14 -L smartconnect_v1_0 -L axi_infrastructure_v1_1_0 -L axi_register_slice_v2_1_29 -L axi_vip_v1_1_15 -L microblaze_v11_0_12 -L lmb_v10_v3_0_13 -L lmb_bram_if_cntlr_v4_0_23 -L blk_mem_gen_v8_4_7 -L iomodule_v3_1_9 -L util_vector_logic_v2_0_3 -L gigantic_mux -L xlconcat_v2_1_5 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_design_1_wrapper_behav xil_defaultlib.tb_design_1_wrapper xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-8809] cannot index into scalar type parameter/localparam 'DEBUG_MESSAGES' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv:234]
WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 2 for port 'm_axil_awprot' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/08a1/src/ccsds_uart_axi.sv:190]
WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 2 for port 'm_axil_arprot' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/08a1/src/ccsds_uart_axi.sv:202]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_awid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2822]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_bid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2837]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_arid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2841]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_rid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2851]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_awid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2866]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_bid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2881]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_arid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2885]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_rid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2895]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_awid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2954]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_3_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2960]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_bid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2969]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_arid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2973]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_3_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2978]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_rid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2983]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_4_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3004]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_4_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3022]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_5_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3048]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_5_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3066]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_6_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3092]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_6_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3110]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_7_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3136]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_7_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3154]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_8_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3180]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_8_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3198]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_9_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3224]
WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 4 for port 'slot_9_axi_wstrb' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3229]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_9_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3242]
WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 4 for port 'slot_9_axis_tstrb' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3256]
WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 4 for port 'slot_9_axis_tkeep' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3257]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_10_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3268]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_10_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3286]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_11_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3312]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_11_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3330]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_12_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3356]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_12_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3374]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_13_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3400]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_13_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3418]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_14_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3444]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_14_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3462]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_15_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3488]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_15_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3506]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 4 for port 'sel' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4406]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_awuser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4407]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_wuser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4408]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_buser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4409]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_ruser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4411]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_wuser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4413]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_buser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4414]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_aruser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4415]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_ruser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4416]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_2_axi_awuser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4417]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_2_axi_wuser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4418]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_2_axi_buser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4419]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_2_axi_aruser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4420]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_2_axi_ruser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4421]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_awuser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4422]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_wuser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4423]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_buser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4424]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_aruser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4425]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_ruser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4426]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_wid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4588]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_wid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4593]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_wid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4603]
WARNING: [VRFC 10-5021] port 'mb_reset' is not connected on this instance [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/sim/design_1.v:506]
WARNING: [VRFC 10-5021] port 'mb_reset' is not connected on this instance [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/sim/bd_886d.v:2249]
WARNING: [VRFC 10-5021] port 'mb_reset' is not connected on this instance [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/sim/bd_886d.v:2256]
WARNING: [VRFC 10-5021] port 'mb_reset' is not connected on this instance [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/sim/bd_886d.v:2263]
WARNING: [VRFC 10-3705] select index 2 into 'rank' is out of bounds [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_cal_mc_odt.sv:148]
Completed static elaboration
Starting simulation data flow analysis
WARNING: [XSIM 43-4398] File "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_cal_cplx.sv" Line 856 : The System Verilog Assertion will be ignored as it appears inside another process. This assertion is not yet supported.
WARNING: [XSIM 43-4398] File "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_cal_top.sv" Line 1813 : The System Verilog Assertion will be ignored as it appears inside another process. This assertion is not yet supported.
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_unsigned
Compiling package lib_pkg_v1_0_3.lib_pkg
Compiling package xpm.vcomponents
Compiling package synopsys.attributes
Compiling package ieee.std_logic_misc
Compiling package unisim.vcomponents
Compiling package ieee.vital_timing
Compiling package ieee.vital_primitives
Compiling package unisim.vpkg
Compiling package xpm.$unit_xpm_cdc_sv_220102727
Compiling package xpm.axi_xil_sb_pkg_xpm_nsu
Compiling package xpm.axi_data_integrity_checker_xpm_n...
Compiling package xpm.xpm_axi_data_integrity_checker_n...
Compiling package xpm.xpm_axi_xil_sb_pkg_nmu
Compiling package xil_defaultlib.ccsds122p_pkg
Compiling package smartconnect_v1_0.sc_util_v1_0_4_pkg
Compiling module xil_defaultlib.ccsds122_axil_slave
Compiling module xil_defaultlib.design_1_ccsds122_axil_slave_0_0
Compiling module xpm.xpm_fifo_rst_default
Compiling module xpm.xpm_fifo_reg_bit
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=8...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=7...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=2...
Compiling module xpm.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
Compiling module xpm.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling architecture implementation of entity lib_fifo_v1_0_18.sync_fifo_fg [\sync_fifo_fg(c_family="kintexup...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_sfifo_autord [\axi_datamover_sfifo_autord(c_dw...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_rd_sf [\axi_datamover_rd_sf(c_sf_fifo_d...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_skid_buf [\axi_datamover_skid_buf(c_wdata_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_reset [axi_datamover_reset_default]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=4,c_dwidth=8...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=8,c_dep...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=8,c_depth=4...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=8,c...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.cntr_incr_decr_addn_f [\cntr_incr_decr_addn_f(c_size=3,...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=4,c_dwidth=6...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=68,c_de...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=68,c_depth=...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=68,...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_cmd_status [\axi_datamover_cmd_status(c_fami...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_rd_status_cntl [axi_datamover_rd_status_cntl_def...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_strb_gen2 [\axi_datamover_strb_gen2(c_strb_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_strb_gen2 [\axi_datamover_strb_gen2(c_op_mo...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_pcc [\axi_datamover_pcc(c_is_mm2s=1,c...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=3,c_dwidth=5...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=59,c_de...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=59,c_depth=...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=59,...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_addr_cntl [\axi_datamover_addr_cntl(c_addr_...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=3,c_dwidth=5...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=55,c_de...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=55,c_depth=...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=55,...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_rdmux [\axi_datamover_rdmux(c_sel_addr_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_rddata_cntl [\axi_datamover_rddata_cntl(c_ali...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_mm2s_full_wrap [\axi_datamover_mm2s_full_wrap(c_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_ibttcc [\axi_datamover_ibttcc(c_sf_xfer_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_dre_mux2_1_x_n [\axi_datamover_dre_mux2_1_x_n(c_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_dre_mux4_1_x_n [\axi_datamover_dre_mux4_1_x_n(c_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_dre_mux8_1_x_n [\axi_datamover_dre_mux8_1_x_n(c_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_s2mm_dre [axi_datamover_s2mm_dre_default]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_ms_strb_set [axi_datamover_ms_strb_set_defaul...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_mssai_skid_buf [\axi_datamover_mssai_skid_buf(c_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_strb_gen2 [axi_datamover_strb_gen2_default]
Compiling architecture working of entity axi_datamover_v5_1_31.axi_datamover_slice [\axi_datamover_slice(c_data_widt...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.cntr_incr_decr_addn_f [\cntr_incr_decr_addn_f(c_size=5,...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=16,c_dwidth=...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=14,c_fa...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=14,c_family...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=14,...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_s2mm_scatter [\axi_datamover_s2mm_scatter(c_en...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=4,c_dwidth=3...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=38,c_de...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=38,c_depth=...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=38,...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_s2mm_realign [\axi_datamover_s2mm_realign(c_en...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_stbs_set [axi_datamover_stbs_set_default]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_stbs_set [\axi_datamover_stbs_set(c_strobe...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_skid_buf [\axi_datamover_skid_buf(c_wdata_...]
Compiling module xpm.xpm_fifo_rst_default_1
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=5...
Compiling module xpm.xpm_counter_updn
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=1...
Compiling module xpm.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling architecture implementation of entity lib_fifo_v1_0_18.sync_fifo_fg [\sync_fifo_fg(c_family="kintexup...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_sfifo_autord [\axi_datamover_sfifo_autord(c_dw...]
Compiling module xpm.xpm_fifo_rst_default_2
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
Compiling module xpm.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling architecture implementation of entity lib_fifo_v1_0_18.sync_fifo_fg [\sync_fifo_fg(c_family="kintexup...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_sfifo_autord [\axi_datamover_sfifo_autord(c_dw...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_indet_btt [\axi_datamover_indet_btt(c_ibtt_...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=4,c_dwidth=3...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=32,c_de...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=32,c_depth=...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_family="ki...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_cmd_status [\axi_datamover_cmd_status(c_sts_...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=6,c_dwidth=3...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=30,c_de...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=30,c_depth=...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=30,...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.cntr_incr_decr_addn_f [\cntr_incr_decr_addn_f(c_size=4,...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=6,c_dwidth=2...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=2,c_dep...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=2,c_depth=6...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=2,c...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_wr_status_cntl [\axi_datamover_wr_status_cntl(c_...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=4,c_dwidth=5...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=59,c_de...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=59,c_depth=...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=59,...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_addr_cntl [\axi_datamover_addr_cntl(c_addr_...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=4,c_dwidth=5...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=53,c_de...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=53,c_depth=...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=53,...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_wrdata_cntl [\axi_datamover_wrdata_cntl(c_rea...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_wr_demux [\axi_datamover_wr_demux(c_sel_ad...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_skid2mm_buf [\axi_datamover_skid2mm_buf(c_mda...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_s2mm_full_wrap [\axi_datamover_s2mm_full_wrap(c_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover [\axi_datamover(c_include_mm2s=1,...]
Compiling architecture axi_datamover_0_arch of entity xil_defaultlib.axi_datamover_0 [axi_datamover_0_default]
Compiling module xil_defaultlib.ccsds122_addr_calc(AXI_ADDR_W=32...
Compiling module xil_defaultlib.ila_1
Compiling module xil_defaultlib.ccsds122_stream_ctrl(AXI_ADDR_W=...
Compiling module fifo_generator_v13_2_9.fifo_generator_v13_2_9_bhv_ver_s...
Compiling module fifo_generator_v13_2_9.fifo_generator_v13_2_9_bhv_ver_p...
Compiling module fifo_generator_v13_2_9.fifo_generator_v13_2_9_CONV_VER(...
Compiling module fifo_generator_v13_2_9.fifo_generator_vlog_beh(C_COMMON...
Compiling module xil_defaultlib.fifo_generator_0
Compiling module xil_defaultlib.ccsds122_bubble_removal_ctrl(AXI...
Compiling module xil_defaultlib.ccsds122p_ingress_frontend_defau...
Compiling module xil_defaultlib.ccsds122p_dwt_m97_lift_core(COEF...
Compiling module xil_defaultlib.ccsds122p_dwt_h_stage(ROW_SAMPLE...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=61...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xil_defaultlib.ccsds122p_dwt_v_stage(STAGE_SAMP...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=30...
Compiling module xil_defaultlib.ccsds122p_dwt_ll_row_order(STAGE...
Compiling module xil_defaultlib.ccsds122p_dwt_split_stage(STAGE_...
Compiling module xil_defaultlib.ccsds122p_dwt_l0(ENABLE_PROTOCOL...
Compiling module xil_defaultlib.ccsds122p_dwt_h_stage(ROW_SAMPLE...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=30...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xil_defaultlib.ccsds122p_dwt_v_stage(STAGE_SAMP...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=15...
Compiling module xil_defaultlib.ccsds122p_dwt_ll_row_order(STAGE...
Compiling module xil_defaultlib.ccsds122p_dwt_split_stage(STAGE_...
Compiling module xil_defaultlib.ccsds122p_dwt_l1(ENABLE_PROTOCOL...
Compiling module xil_defaultlib.ccsds122p_dwt_h_stage(ROW_SAMPLE...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=15...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xil_defaultlib.ccsds122p_dwt_v_stage(STAGE_SAMP...
Compiling module xil_defaultlib.ccsds122p_dwt_l2(ENABLE_PROTOCOL...
Compiling module xil_defaultlib.ccsds122p_dwt_merge(ENABLE_PROTO...
Compiling module xil_defaultlib.ccsds122p_subband_router(ENABLE_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=15...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram_masked(DATA...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=81...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xil_defaultlib.ccsds122p_segment_reorder(ENABLE...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=24...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xil_defaultlib.ccsds122p_segment_bank
Compiling module xil_defaultlib.ccsds122p_segment_fill(ENABLE_PR...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=25...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xil_defaultlib.ccsds122p_block_state_ram(DATA_W...
Compiling module xil_defaultlib.ccsds122p_segment_state_bank
Compiling module xil_defaultlib.ccsds122p_dc_option_select
Compiling module xil_defaultlib.ccsds122p_dc_code_emitter
Compiling module xil_defaultlib.ccsds122p_dc_entropy_encoder
Compiling module xil_defaultlib.ccsds122p_ac_depth_option_select...
Compiling module xil_defaultlib.ccsds122p_ac_depth_code_emitter_...
Compiling module xil_defaultlib.ccsds122p_ac_depth_encoder_defau...
Compiling module xil_defaultlib.ccsds122p_ac_stage0_dc_emit
Compiling module xil_defaultlib.ccsds122p_segment_block_reader
Compiling module xil_defaultlib.ccsds122p_stage_block_scan(FIXED...
Compiling module xil_defaultlib.ccsds122p_stage_pattern_map
Compiling module xil_defaultlib.ccsds122p_stage_option_select(US...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=15...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=14...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=51...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=33...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xil_defaultlib.ccsds122p_stage_rice_emitter
Compiling module xil_defaultlib.ccsds122p_stage_symbol_emit
Compiling module xil_defaultlib.ccsds122p_stage_refine_emit
Compiling module xil_defaultlib.ccsds122p_ac_bitplane_cached_com...
Compiling module xil_defaultlib.ccsds122p_ac_bitplane_gaggle_enc...
Compiling module xil_defaultlib.ccsds122p_segment_encoder_core
Compiling module xil_defaultlib.ccsds122p_bitstream_packer(ENABL...
Compiling module xil_defaultlib.ccsds122p_backend_lane(ENABLE_PR...
Compiling module xil_defaultlib.ccsds122p_bit_length24(BITS_W=32...
Compiling module xil_defaultlib.ccsds122p_segment_bitdepth
Compiling module xil_defaultlib.ccsds122p_header_writer_default
Compiling module xil_defaultlib.ccsds122p_segment_stats
Compiling module xil_defaultlib.ccsds122p_dc_seed
Compiling module xil_defaultlib.ccsds122p_block_state_pack_defau...
Compiling module xil_defaultlib.ccsds122p_segment_first_pass(OWN...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=23...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xil_defaultlib.ccsds122p_encoded_segment_reorde...
Compiling module xil_defaultlib.ccsds122p_backend_farm(LANE_COUN...
Compiling module xil_defaultlib.top_bpe_encoder(BACKEND_LANE_COU...
Compiling module xil_defaultlib.ccsds122_compression_top(AXI_ADD...
Compiling module xil_defaultlib.ccsds122_datamover(MEMORY_BLOCK_...
Compiling module xil_defaultlib.design_1_ccsds122_datamover_0_0
Compiling module xil_defaultlib.uart_rx
Compiling module xil_defaultlib.uart_tx
Compiling module xil_defaultlib.vio_0
Compiling module xil_defaultlib.axi_uart_upload_default
Compiling module xil_defaultlib.ccsds_uart_axi_default
Compiling module xil_defaultlib.design_1_ccsds_uart_axi_0_0
Compiling module unisims_ver.BUFG
Compiling module unisims_ver.MMCME4_ADV(CLKFBOUT_MULT_F=7.0,C...
Compiling module xil_defaultlib.ddr4_v2_2_20_infrastructure(CLKI...
Compiling module unisims_ver.OBUF
Compiling module unisims_ver.IBUFDS(IBUF_LOW_PWR="FALSE")
Compiling module unisims_ver.PLLE4_ADV(CLKFBOUT_MULT=4,CLKFBO...
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_pll(PLL_WIDTH=2,...
Compiling module unisims_ver.HPIO_VREF(VREF_CNTR="FABRIC_RANG...
Compiling module unisims_ver.IOBUFE3_default
Compiling module unisims_ver.IOBUFDS
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_iob_byte(IOBTYPE...
Compiling module unisims_ver.OBUFDS
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_iob_byte(IOBTYPE...
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_iob_byte(IOBTYPE...
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_iob_byte(IOBTYPE...
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_iob(BYTES=6,IOBT...
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_fifo_sv(DEPTH=16...
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_bitslice_behav
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_xiphy_behav(BYTE...
Compiling module xil_defaultlib.design_1_ddr4_0_0_phy_ddr4_defau...
Compiling module xil_defaultlib.design_1_ddr4_0_0_phy
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_group(ABITS=17,A...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_act_rank(tFAW=28...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_act_timer(tFAW=2...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_arb_a
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_wtr(tWTR_L=6,tWT...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_rd_wr(tWTR_L=6,t...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_arb_c_default
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_arb_p
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_cmd_mux_ap(ABITS...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_arb_mux_p(ABITS=...
WARNING: [VRFC 10-3705] select index 2 into 'rank' is out of bounds [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_cal_mc_odt.sv:148]
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_mc_odt(ODTBITS=...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_ctl(ABITS=17,BGB...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_cmd_mux_c
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_ref(LR_WIDTH=1,S...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_periodic
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_ecc(TCQ=0.1,PAYL...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc(ABITS=17,BGBITS=...
Compiling module xil_defaultlib.ddr4_v2_2_20_ui_cmd(TCQ=100.0,AD...
Compiling module unisims_ver.RAM32M
Compiling module xil_defaultlib.ddr4_v2_2_20_ui_wr_data(TCQ=100....
Compiling module xil_defaultlib.ddr4_v2_2_20_ui_rd_data(TCQ=100....
Compiling module xil_defaultlib.ddr4_v2_2_20_ui(TCQ=100.0,ADDR_W...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_debug_microblaz...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_cplx_data_defau...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_cplx(ABITS=17,B...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_addr_decode(DRA...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_config_rom(MEM0...
Compiling module xil_defaultlib.ddr4_v2_2_20_chipscope_xsdb_slav...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_sync(WIDTH=1)
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_sync(WIDTH=16)
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_sync(WIDTH=9)
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_xsdb_arbiter
Compiling module xil_defaultlib.ddr4_v2_2_20_bram_tdp(INIT=2304'...
Compiling module xil_defaultlib.ddr4_v2_2_20_cfg_mem_mod(SIZE=36...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_xsdb_bram(DBYTE...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal(ABITS=17,BGBITS...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_rd_en(RL=32'b01...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_read(RL=32'b010...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_wr_bit
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_wr_byte_default
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_write(WL=32'b01...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_pi(RL=32'b01011...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_top(ABITS=17,BG...
Compiling module unisims_ver.VCC
Compiling module unisims_ver.GND
Compiling module unisims_ver.FDRE_default
Compiling module unisims_ver.FDR
Compiling module unisims_ver.FDSE_default
Compiling module unisims_ver.FDS
Compiling module unisims_ver.FD
Compiling module unisims_ver.FDRE(INIT=1'b1)
Compiling module unisims_ver.FD(INIT=1'b1)
Compiling module unisims_ver.RAM32X1D
Compiling module unisims_ver.FDE
Compiling module unisims_ver.LUT6_2
Compiling module unisims_ver.MUXCY
Compiling module unisims_ver.MUXCY_L
Compiling module unisims_ver.XORCY
Compiling module unisims_ver.x_lut2_mux4
Compiling module unisims_ver.LUT2
Compiling module unisims_ver.MULT_AND
Compiling module unisims_ver.x_lut3_mux8
Compiling module unisims_ver.LUT3
Compiling module unisims_ver.LUT4
Compiling module unisims_ver.LUT6
Compiling module unisims_ver.MUXF5
Compiling module unisims_ver.SRL16E_default
Compiling module unisims_ver.LUT5
Compiling module unisims_ver.FDSE(INIT=1'b0)
Compiling module unisims_ver.x_lut1_mux2
Compiling module unisims_ver.LUT1
Compiling module unisims_ver.MUXF7
Compiling module unisims_ver.INV
Compiling module unisims_ver.RB36_INTERNAL_VLOG(READ_WIDTH_A=...
Compiling module unisims_ver.RAMB36E1(READ_WIDTH_A=2,READ_WID...
Compiling module unisims_ver.RAMB36(READ_WIDTH_A=2,READ_WIDTH...
Compiling module xil_defaultlib.microblaze_mcs
Compiling module xil_defaultlib.design_1_ddr4_0_0_microblaze_mcs
Compiling module xil_defaultlib.design_1_ddr4_0_0_ddr4_cal_riu
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_sync(WIDTH=1,TC...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_sync(WIDTH=32,T...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_sync(WIDTH=20,T...
Compiling module xil_defaultlib.design_1_ddr4_0_0_ddr4_mem_intfc...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_register_slice(...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_register_slice(...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_register_slice(...
Compiling module xil_defaultlib.ddr4_v2_2_20_command_fifo(C_FAMI...
Compiling module xil_defaultlib.ddr4_v2_2_20_a_upsizer(C_AXI_ID_...
Compiling module xil_defaultlib.ddr4_v2_2_20_w_upsizer(C_S_AXI_D...
Compiling module xil_defaultlib.ddr4_v2_2_20_r_upsizer(C_AXI_ID_...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_upsizer(C_AXI_I...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_register_slice(...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_incr_cmd(C_AXI_...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_wrap_cmd(C_AXI_...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_cmd_translator(...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_wr_cmd_fsm
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_aw_channel(C_ID...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_w_channel(C_DAT...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_fifo(C_WIDTH=1,...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_b_channel(C_ID_...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_incr_cmd(C_AXI_...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_wrap_cmd(C_AXI_...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_cmd_translator(...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_cmd_fsm(C_MC_RD...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_ar_channel(C_ID...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_fifo(C_WIDTH=25...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_fifo(C_WIDTH=4,...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_r_channel(C_ID_...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_cmd_arbiter(C_M...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi(C_S_AXI_ID_WIDT...
Compiling module xil_defaultlib.design_1_ddr4_0_0_ddr4_default
Compiling module xil_defaultlib.design_1_ddr4_0_0
Compiling module xil_defaultlib.design_1_ila_0_0
Compiling architecture fdre_v of entity unisim.FDRE [fdre_default]
Compiling architecture fdre_v of entity unisim.FDRE [\FDRE(init='1')\]
Compiling architecture fdr_v of entity unisim.FDR [fdr_default]
Compiling architecture implementation of entity lib_cdc_v1_0_2.cdc_sync [\cdc_sync(c_vector_width=2,c_mtb...]
Compiling architecture srl16e_v of entity unisim.SRL16E [\SRL16E(init="1111111111111111")...]
Compiling architecture srl16_v of entity unisim.SRL16 [\SRL16(init="1111111111111111")(...]
Compiling architecture imp of entity proc_sys_reset_v5_0_14.lpf [\lpf(c_ext_rst_width=4,c_aux_rst...]
Compiling architecture imp of entity proc_sys_reset_v5_0_14.upcnt_n [\upcnt_n(c_size=6)\]
Compiling architecture imp of entity proc_sys_reset_v5_0_14.sequence_psr [sequence_psr_default]
Compiling architecture imp of entity proc_sys_reset_v5_0_14.proc_sys_reset [\proc_sys_reset(c_family="kintex...]
Compiling architecture design_1_proc_sys_reset_0_0_arch of entity xil_defaultlib.design_1_proc_sys_reset_0_0 [design_1_proc_sys_reset_0_0_defa...]
Compiling module xlconstant_v1_1_8.xlconstant_v1_1_8_xlconstant(CON...
Compiling module xil_defaultlib.bd_886d_one_0
Compiling architecture imp of entity proc_sys_reset_v5_0_14.lpf [\lpf(c_ext_rst_width=4,c_aux_rst...]
Compiling architecture imp of entity proc_sys_reset_v5_0_14.proc_sys_reset [\proc_sys_reset(c_family="kintex...]
Compiling architecture bd_886d_psr0_0_arch of entity xil_defaultlib.bd_886d_psr0_0 [bd_886d_psr0_0_default]
Compiling architecture bd_886d_psr_aclk_0_arch of entity xil_defaultlib.bd_886d_psr_aclk_0 [bd_886d_psr_aclk_0_default]
Compiling architecture bd_886d_psr_aclk1_0_arch of entity xil_defaultlib.bd_886d_psr_aclk1_0 [bd_886d_psr_aclk1_0_default]
Compiling module xil_defaultlib.clk_map_imp_1WP46Y0
Compiling module xpm.xpm_cdc_async_rst(DEST_SYNC_FF=3...
Compiling module xil_defaultlib.bd_886d_m00e_0
Compiling module xil_defaultlib.m00_exit_pipeline_imp_4816GJ
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=52...
Compiling module xil_defaultlib.bd_886d_m00arn_0
Compiling module xil_defaultlib.bd_886d_m00awn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=67...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=32...
Compiling module xil_defaultlib.bd_886d_m00bn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=48...
Compiling module xil_defaultlib.bd_886d_m00rn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=4,...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=57...
Compiling module xil_defaultlib.bd_886d_m00wn_0
Compiling module xil_defaultlib.m00_nodes_imp_QDFR33
Compiling module xil_defaultlib.bd_886d_m00s2a_0
Compiling module xil_defaultlib.bd_886d_m01e_0
Compiling module xil_defaultlib.m01_exit_pipeline_imp_6OCSAB
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=32...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=52...
Compiling module xil_defaultlib.bd_886d_m01arn_0
Compiling module xil_defaultlib.bd_886d_m01awn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=67...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=32...
Compiling module xil_defaultlib.bd_886d_m01bn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=48...
Compiling module xil_defaultlib.bd_886d_m01rn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=57...
Compiling module xil_defaultlib.bd_886d_m01wn_0
Compiling module xil_defaultlib.m01_nodes_imp_1HTXBQH
Compiling module xil_defaultlib.bd_886d_m01s2a_0
Compiling module xil_defaultlib.bd_886d_s00a2s_0
Compiling module xil_defaultlib.bd_886d_s00mmu_0
Compiling module xil_defaultlib.bd_886d_s00sic_0
Compiling module xil_defaultlib.bd_886d_s00tr_0
Compiling module xil_defaultlib.s00_entry_pipeline_imp_12V3TGW
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=60...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=46...
Compiling module xil_defaultlib.bd_886d_sarn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=54...
Compiling module xil_defaultlib.bd_886d_srn_0
Compiling module xil_defaultlib.s00_nodes_imp_16MUXNU
Compiling module xil_defaultlib.bd_886d_s01a2s_0
Compiling module xil_defaultlib.bd_886d_s01mmu_0
Compiling module xil_defaultlib.bd_886d_s01sic_0
Compiling module xil_defaultlib.bd_886d_s01tr_0
Compiling module xil_defaultlib.s01_entry_pipeline_imp_6HKV8K
Compiling module xil_defaultlib.bd_886d_sawn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=89...
Compiling module xil_defaultlib.bd_886d_sbn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=51...
Compiling module xil_defaultlib.bd_886d_swn_0
Compiling module xil_defaultlib.s01_nodes_imp_1AH57G
Compiling module xil_defaultlib.bd_886d_s02a2s_0
Compiling module xil_defaultlib.bd_886d_s02mmu_0
Compiling module xil_defaultlib.bd_886d_s02sic_0
Compiling module xil_defaultlib.bd_886d_s02tr_0
Compiling module xil_defaultlib.s02_entry_pipeline_imp_R26R6H
Compiling module xil_defaultlib.bd_886d_sarn_1
Compiling module xil_defaultlib.bd_886d_sawn_1
Compiling module xil_defaultlib.bd_886d_sbn_1
Compiling module xil_defaultlib.bd_886d_srn_1
Compiling module xil_defaultlib.bd_886d_swn_1
Compiling module xil_defaultlib.s02_nodes_imp_XIDFT3
Compiling module xil_defaultlib.bd_886d_s03a2s_0
Compiling module xil_defaultlib.bd_886d_s03mmu_0
Compiling module xil_defaultlib.bd_886d_s03sic_0
Compiling module xil_defaultlib.bd_886d_s03tr_0
Compiling module xil_defaultlib.s03_entry_pipeline_imp_1XMQ8JX
Compiling module xil_defaultlib.bd_886d_sarn_2
Compiling module xil_defaultlib.bd_886d_sawn_2
Compiling module xil_defaultlib.bd_886d_sbn_2
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=54...
Compiling module xil_defaultlib.bd_886d_srn_2
Compiling module xil_defaultlib.bd_886d_swn_2
Compiling module xil_defaultlib.s03_nodes_imp_1RRAM9D
Compiling module xil_defaultlib.bd_886d_arsw_0
Compiling module xil_defaultlib.bd_886d_awsw_0
Compiling module xil_defaultlib.bd_886d_bsw_0
Compiling module xil_defaultlib.bd_886d_rsw_0
Compiling module xil_defaultlib.bd_886d_wsw_0
Compiling module xil_defaultlib.switchboards_imp_1V8ZM66
Compiling module xil_defaultlib.bd_886d
Compiling module xil_defaultlib.design_1_smartconnect_0_1
Compiling module xil_defaultlib.bd_f60c_g_inst_0_gigantic_mux(C_...
Compiling module xil_defaultlib.bd_f60c_g_inst_0
Compiling module xil_defaultlib.bd_f60c_ila_lib_0
Compiling module xlconcat_v2_1_5.xlconcat_v2_1_5_xlconcat_default
Compiling module xil_defaultlib.bd_f60c_slot_0_ar_0
Compiling module xil_defaultlib.bd_f60c_slot_0_aw_0
Compiling module xil_defaultlib.bd_f60c_slot_0_b_0
Compiling module xlconcat_v2_1_5.xlconcat_v2_1_5_xlconcat(dout_wi...
Compiling module xil_defaultlib.bd_f60c_slot_0_r_0
Compiling module xil_defaultlib.bd_f60c_slot_0_w_0
Compiling module xil_defaultlib.bd_f60c_slot_1_ar_0
Compiling module xil_defaultlib.bd_f60c_slot_1_aw_0
Compiling module xil_defaultlib.bd_f60c_slot_1_b_0
Compiling module xil_defaultlib.bd_f60c_slot_1_r_0
Compiling module xil_defaultlib.bd_f60c_slot_1_w_0
Compiling module xil_defaultlib.bd_f60c_slot_2_ar_0
Compiling module xil_defaultlib.bd_f60c_slot_2_aw_0
Compiling module xil_defaultlib.bd_f60c_slot_2_b_0
Compiling module xil_defaultlib.bd_f60c_slot_2_r_0
Compiling module xil_defaultlib.bd_f60c_slot_2_w_0
Compiling module xil_defaultlib.bd_f60c_slot_3_ar_0
Compiling module xil_defaultlib.bd_f60c_slot_3_aw_0
Compiling module xil_defaultlib.bd_f60c_slot_3_b_0
Compiling module xil_defaultlib.bd_f60c_slot_3_r_0
Compiling module xil_defaultlib.bd_f60c_slot_3_w_0
Compiling module xil_defaultlib.bd_f60c
Compiling module xil_defaultlib.design_1_system_ila_0_0
Compiling module util_vector_logic_v2_0_3.util_vector_logic_v2_0_3_util_ve...
Compiling module xil_defaultlib.design_1_util_vector_logic_0_4
Compiling module xil_defaultlib.design_1
Compiling module xil_defaultlib.design_1_wrapper
Compiling module xil_defaultlib.tb_design_1_wrapper
Compiling module xil_defaultlib.glbl
Built simulation snapshot tb_design_1_wrapper_behav
run_program: Time (s): cpu = 00:00:03 ; elapsed = 00:01:06 . Memory (MB): peak = 2051.137 ; gain = 0.000
INFO: [USF-XSim-69] 'elaborate' step finished in '65' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_design_1_wrapper_behav -key {Behavioral:sim_1:Functional:tb_design_1_wrapper} -tclbatch {tb_design_1_wrapper.tcl} -protoinst "protoinst_files/bd_886d.protoinst" -protoinst "protoinst_files/bd_45eb.protoinst" -protoinst "protoinst_files/bd_f60c.protoinst" -protoinst "protoinst_files/design_1.protoinst" -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/bd_886d.protoinst
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m00_exit_pipeline/m00_exit/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m00_exit_pipeline/m00_exit/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m00_exit_pipeline/m_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m00_exit_pipeline/s_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m00_nodes/m00_aw_node/M_AXIS_ARB
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m00_nodes/m00_w_node/S_AXIS_ARB
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m00_sc2axi/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m01_exit_pipeline/m01_exit/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m01_exit_pipeline/m01_exit/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m01_exit_pipeline/m_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m01_exit_pipeline/s_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m01_nodes/m01_aw_node/M_AXIS_ARB
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m01_nodes/m01_w_node/S_AXIS_ARB
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m01_sc2axi/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_axi2sc/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/m_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/s00_mmu/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/s00_mmu/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/s00_si_converter/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/s00_si_converter/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/s00_transaction_regulator/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/s00_transaction_regulator/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/s_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_axi2sc/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/m_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/s01_mmu/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/s01_mmu/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/s01_si_converter/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/s01_si_converter/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/s01_transaction_regulator/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/s01_transaction_regulator/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/s_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_axi2sc/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_entry_pipeline/m_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_entry_pipeline/s02_mmu/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_entry_pipeline/s02_mmu/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_entry_pipeline/s02_si_converter/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_entry_pipeline/s02_si_converter/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_entry_pipeline/s02_transaction_regulator/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_entry_pipeline/s02_transaction_regulator/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_entry_pipeline/s_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_axi2sc/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_entry_pipeline/m_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_entry_pipeline/s03_mmu/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_entry_pipeline/s03_mmu/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_entry_pipeline/s03_si_converter/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_entry_pipeline/s03_si_converter/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_entry_pipeline/s03_transaction_regulator/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_entry_pipeline/s03_transaction_regulator/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_entry_pipeline/s_axi
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/bd_45eb.protoinst
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/bd_45eb.protoinst for the following reason(s):
There are no instances of module "bd_45eb" in the design.
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/bd_f60c.protoinst
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_1.protoinst
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//ccsds122_axil_slave_0/s_axil
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//ccsds122_datamover_0/m_axi_mm2s
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//ccsds122_datamover_0/m_axi_s2mm
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//ccsds_uart_axi_0/m_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//ccsds_uart_axi_0/m_axil
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//ddr4_0/C0_DDR4_S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//smartconnect_0/M00_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//smartconnect_0/M01_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//smartconnect_0/S00_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//smartconnect_0/S01_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//smartconnect_0/S02_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//smartconnect_0/S03_AXI
Time resolution is 1 ps
source tb_design_1_wrapper.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
==== TB: Waiting for DDR4 calib... ====
$finish called at time : 0 fs : File "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/tb_design_1_wrapper.sv" Line 99
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_design_1_wrapper_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:10 ; elapsed = 00:01:16 . Memory (MB): peak = 2051.137 ; gain = 0.000
restart
INFO: [Wavedata 42-604] Simulation restarted
run 7 ms
==== TB: Waiting for DDR4 calib... ====
$finish called at time : 0 fs : File "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/tb_design_1_wrapper.sv" Line 99
run 7 ms
[TB] DDR4 calib done @ 0 ps
[2/6] Config registers
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. tb_design_1_wrapper.u_dut.design_1_i.ccsds122_datamover_0.inst.u_datamover.U0.gen_s2mm_full.I_S2MM_FULL_WRAPPER.gen_enable_indet_btt_sf.I_INDET_BTT.I_XD_FIFO.non_blk_mem.I_SYNC_FIFOGEN_FIFO.xpm_fifo_instance.xpm_fifo_sync_inst.xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/ccsds122_datamover_0/inst/u_datamover/U0/gen_s2mm_full/I_S2MM_FULL_WRAPPER/gen_enable_indet_btt_sf/I_INDET_BTT/I_XD_FIFO/non_blk_mem/I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance/xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial302_83 Scope: tb_design_1_wrapper.u_dut.design_1_i.ccsds122_datamover_0.inst.u_datamover.U0.gen_s2mm_full.I_S2MM_FULL_WRAPPER.gen_enable_indet_btt_sf.I_INDET_BTT.I_XD_FIFO.non_blk_mem.I_SYNC_FIFOGEN_FIFO.xpm_fifo_instance.xpm_fifo_sync_inst.xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 506
Info: [Unisim HPIO_VREF-1] Fabric Tune Value changed to 0011111. Instance: tb_design_1_wrapper.u_dut.design_1_i.ddr4_0.inst.u_ddr4_mem_intfc.u_mig_ddr4_phy.inst.u_ddr_iob.\genByte[0].u_ddr_iob_byte .\genblk1.genVref.u_hpio_vref
Info: [Unisim HPIO_VREF-1] Fabric Tune Value changed to 0011111. Instance: tb_design_1_wrapper.u_dut.design_1_i.ddr4_0.inst.u_ddr4_mem_intfc.u_mig_ddr4_phy.inst.u_ddr_iob.\genByte[3].u_ddr_iob_byte .\genblk1.genVref.u_hpio_vref
Info: [Unisim HPIO_VREF-1] Fabric Tune Value changed to 0011111. Instance: tb_design_1_wrapper.u_dut.design_1_i.ddr4_0.inst.u_ddr4_mem_intfc.u_mig_ddr4_phy.inst.u_ddr_iob.\genByte[4].u_ddr_iob_byte .\genblk1.genVref.u_hpio_vref
Info: [Unisim HPIO_VREF-1] Fabric Tune Value changed to 0011111. Instance: tb_design_1_wrapper.u_dut.design_1_i.ddr4_0.inst.u_ddr4_mem_intfc.u_mig_ddr4_phy.inst.u_ddr_iob.\genByte[5].u_ddr_iob_byte .\genblk1.genVref.u_hpio_vref
[TB] Reset released @ 2498000 ps
run: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 2054.586 ; gain = 3.449
current_wave_config {Untitled 2}
Untitled 2
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/ccsds_uart_axi_0}}
current_wave_config {Untitled 2}
Untitled 2
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/ccsds_uart_axi_0/inst/u_core}}
current_wave_config {Untitled 2}
Untitled 2
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/ccsds122_axil_slave_0}}
current_wave_config {Untitled 2}
Untitled 2
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/ccsds122_datamover_0/inst}}
current_wave_config {Untitled 2}
Untitled 2
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl}}
restart
INFO: [Wavedata 42-604] Simulation restarted
run 7 ms
==== TB: Waiting for DDR4 calib... ====
$finish called at time : 0 fs : File "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/tb_design_1_wrapper.sv" Line 99
run 7 ms
[TB] DDR4 calib done @ 0 ps
[2/6] Config registers
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. tb_design_1_wrapper.u_dut.design_1_i.ccsds122_datamover_0.inst.u_datamover.U0.gen_s2mm_full.I_S2MM_FULL_WRAPPER.gen_enable_indet_btt_sf.I_INDET_BTT.I_XD_FIFO.non_blk_mem.I_SYNC_FIFOGEN_FIFO.xpm_fifo_instance.xpm_fifo_sync_inst.xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/ccsds122_datamover_0/inst/u_datamover/U0/gen_s2mm_full/I_S2MM_FULL_WRAPPER/gen_enable_indet_btt_sf/I_INDET_BTT/I_XD_FIFO/non_blk_mem/I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance/xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial302_83 Scope: tb_design_1_wrapper.u_dut.design_1_i.ccsds122_datamover_0.inst.u_datamover.U0.gen_s2mm_full.I_S2MM_FULL_WRAPPER.gen_enable_indet_btt_sf.I_INDET_BTT.I_XD_FIFO.non_blk_mem.I_SYNC_FIFOGEN_FIFO.xpm_fifo_instance.xpm_fifo_sync_inst.xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 506
Info: [Unisim HPIO_VREF-1] Fabric Tune Value changed to 0011111. Instance: tb_design_1_wrapper.u_dut.design_1_i.ddr4_0.inst.u_ddr4_mem_intfc.u_mig_ddr4_phy.inst.u_ddr_iob.\genByte[0].u_ddr_iob_byte .\genblk1.genVref.u_hpio_vref
Info: [Unisim HPIO_VREF-1] Fabric Tune Value changed to 0011111. Instance: tb_design_1_wrapper.u_dut.design_1_i.ddr4_0.inst.u_ddr4_mem_intfc.u_mig_ddr4_phy.inst.u_ddr_iob.\genByte[3].u_ddr_iob_byte .\genblk1.genVref.u_hpio_vref
Info: [Unisim HPIO_VREF-1] Fabric Tune Value changed to 0011111. Instance: tb_design_1_wrapper.u_dut.design_1_i.ddr4_0.inst.u_ddr4_mem_intfc.u_mig_ddr4_phy.inst.u_ddr_iob.\genByte[4].u_ddr_iob_byte .\genblk1.genVref.u_hpio_vref
Info: [Unisim HPIO_VREF-1] Fabric Tune Value changed to 0011111. Instance: tb_design_1_wrapper.u_dut.design_1_i.ddr4_0.inst.u_ddr4_mem_intfc.u_mig_ddr4_phy.inst.u_ddr_iob.\genByte[5].u_ddr_iob_byte .\genblk1.genVref.u_hpio_vref
[TB] Reset released @ 2498000 ps
[3/6] Start compress
[4/6] Poll STATUS
run: Time (s): cpu = 00:02:15 ; elapsed = 00:06:50 . Memory (MB): peak = 3647.270 ; gain = 1241.969
current_wave_config {Untitled 2}
Untitled 2
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/ccsds122_axil_slave_0}}
current_wave_config {Untitled 2}
Untitled 2
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/ccsds_uart_axi_0/inst/u_core}}
current_wave_config {Untitled 2}
Untitled 2
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/ccsds_uart_axi_0/inst}}
current_wave_config {Untitled 2}
Untitled 2
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/ccsds_uart_axi_0/inst}}
current_wave_config {Untitled 2}
Untitled 2
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/ccsds_uart_axi_0/inst/u_core}}
close_sim
INFO: xsimkernel Simulation Memory Usage: 97764 KB (Peak: 97764 KB), Simulation CPU Usage: 408140 ms
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-12493] Simulation top is 'tb_design_1_wrapper'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
Generating merged BMM file for the design top 'tb_design_1_wrapper'...
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2023.2/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2023.2/data/xsim/xsim.ini' copied to run dir:'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim'
INFO: [SIM-utils-50] Design contains embedded sources, generating MEM files for simulation...
Generating merged BMM file for the design top 'tb_design_1_wrapper'...
WARNING: [Memdata 28-361] Design is having concatenated BRAM controllers(heterogenous memory), this configuration is not supported by Updatemem for current device part. Only the first BRAM controller will be added to .MMI and used by Updatemem to update the bitstream with new data.
Generating merged BMM file for the design top 'tb_design_1_wrapper'...
INFO: [SIM-utils-54] Inspecting design source files for 'tb_design_1_wrapper' in fileset 'sim_1'...
INFO: [SIM-utils-43] Exported 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim/sc_xtlm_design_1_smartconnect_0_1.mem'
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim'
"xvlog --incr --relax -L uvm -L axi_vip_v1_1_15 -L smartconnect_v1_0 -L xilinx_vip -prj tb_design_1_wrapper_vlog.prj"
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/tb_design_1_wrapper.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module tb_design_1_wrapper
"xvhdl --incr --relax -prj tb_design_1_wrapper_vhdl.prj"
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim'
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L fifo_generator_v13_2_9 -L lib_pkg_v1_0_3 -L lib_fifo_v1_0_18 -L lib_srl_fifo_v1_0_3 -L lib_cdc_v1_0_2 -L axi_datamover_v5_1_31 -L xlconstant_v1_1_8 -L proc_sys_reset_v5_0_14 -L smartconnect_v1_0 -L axi_infrastructure_v1_1_0 -L axi_register_slice_v2_1_29 -L axi_vip_v1_1_15 -L microblaze_v11_0_12 -L lmb_v10_v3_0_13 -L lmb_bram_if_cntlr_v4_0_23 -L blk_mem_gen_v8_4_7 -L iomodule_v3_1_9 -L util_vector_logic_v2_0_3 -L gigantic_mux -L xlconcat_v2_1_5 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_design_1_wrapper_behav xil_defaultlib.tb_design_1_wrapper xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator v2023.2
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2023.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L fifo_generator_v13_2_9 -L lib_pkg_v1_0_3 -L lib_fifo_v1_0_18 -L lib_srl_fifo_v1_0_3 -L lib_cdc_v1_0_2 -L axi_datamover_v5_1_31 -L xlconstant_v1_1_8 -L proc_sys_reset_v5_0_14 -L smartconnect_v1_0 -L axi_infrastructure_v1_1_0 -L axi_register_slice_v2_1_29 -L axi_vip_v1_1_15 -L microblaze_v11_0_12 -L lmb_v10_v3_0_13 -L lmb_bram_if_cntlr_v4_0_23 -L blk_mem_gen_v8_4_7 -L iomodule_v3_1_9 -L util_vector_logic_v2_0_3 -L gigantic_mux -L xlconcat_v2_1_5 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_design_1_wrapper_behav xil_defaultlib.tb_design_1_wrapper xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-8809] cannot index into scalar type parameter/localparam 'DEBUG_MESSAGES' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv:234]
WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 2 for port 'm_axil_awprot' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/08a1/src/ccsds_uart_axi.sv:190]
WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 2 for port 'm_axil_arprot' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/08a1/src/ccsds_uart_axi.sv:202]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_awid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2822]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_bid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2837]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_arid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2841]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_rid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2851]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_awid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2866]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_bid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2881]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_arid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2885]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_rid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2895]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_awid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2954]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_3_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2960]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_bid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2969]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_arid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2973]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_3_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2978]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_rid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2983]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_4_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3004]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_4_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3022]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_5_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3048]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_5_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3066]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_6_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3092]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_6_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3110]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_7_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3136]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_7_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3154]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_8_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3180]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_8_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3198]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_9_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3224]
WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 4 for port 'slot_9_axi_wstrb' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3229]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_9_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3242]
WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 4 for port 'slot_9_axis_tstrb' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3256]
WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 4 for port 'slot_9_axis_tkeep' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3257]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_10_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3268]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_10_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3286]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_11_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3312]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_11_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3330]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_12_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3356]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_12_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3374]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_13_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3400]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_13_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3418]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_14_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3444]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_14_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3462]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_15_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3488]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_15_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3506]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 4 for port 'sel' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4406]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_awuser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4407]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_wuser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4408]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_buser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4409]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_ruser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4411]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_wuser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4413]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_buser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4414]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_aruser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4415]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_ruser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4416]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_2_axi_awuser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4417]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_2_axi_wuser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4418]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_2_axi_buser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4419]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_2_axi_aruser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4420]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_2_axi_ruser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4421]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_awuser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4422]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_wuser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4423]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_buser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4424]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_aruser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4425]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_ruser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4426]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_wid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4588]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_wid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4593]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_wid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4603]
WARNING: [VRFC 10-5021] port 'mb_reset' is not connected on this instance [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/sim/design_1.v:506]
WARNING: [VRFC 10-5021] port 'mb_reset' is not connected on this instance [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/sim/bd_886d.v:2249]
WARNING: [VRFC 10-5021] port 'mb_reset' is not connected on this instance [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/sim/bd_886d.v:2256]
WARNING: [VRFC 10-5021] port 'mb_reset' is not connected on this instance [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/sim/bd_886d.v:2263]
WARNING: [VRFC 10-3705] select index 2 into 'rank' is out of bounds [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_cal_mc_odt.sv:148]
Completed static elaboration
Starting simulation data flow analysis
WARNING: [XSIM 43-4398] File "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_cal_cplx.sv" Line 856 : The System Verilog Assertion will be ignored as it appears inside another process. This assertion is not yet supported.
WARNING: [XSIM 43-4398] File "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_cal_top.sv" Line 1813 : The System Verilog Assertion will be ignored as it appears inside another process. This assertion is not yet supported.
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_unsigned
Compiling package lib_pkg_v1_0_3.lib_pkg
Compiling package xpm.vcomponents
Compiling package synopsys.attributes
Compiling package ieee.std_logic_misc
Compiling package unisim.vcomponents
Compiling package ieee.vital_timing
Compiling package ieee.vital_primitives
Compiling package unisim.vpkg
Compiling package xpm.$unit_xpm_cdc_sv_220102727
Compiling package xpm.axi_xil_sb_pkg_xpm_nsu
Compiling package xpm.axi_data_integrity_checker_xpm_n...
Compiling package xpm.xpm_axi_data_integrity_checker_n...
Compiling package xpm.xpm_axi_xil_sb_pkg_nmu
Compiling package xil_defaultlib.ccsds122p_pkg
Compiling package smartconnect_v1_0.sc_util_v1_0_4_pkg
Compiling module xil_defaultlib.ccsds122_axil_slave
Compiling module xil_defaultlib.design_1_ccsds122_axil_slave_0_0
Compiling module xpm.xpm_fifo_rst_default
Compiling module xpm.xpm_fifo_reg_bit
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=8...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=7...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=2...
Compiling module xpm.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
Compiling module xpm.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling architecture implementation of entity lib_fifo_v1_0_18.sync_fifo_fg [\sync_fifo_fg(c_family="kintexup...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_sfifo_autord [\axi_datamover_sfifo_autord(c_dw...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_rd_sf [\axi_datamover_rd_sf(c_sf_fifo_d...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_skid_buf [\axi_datamover_skid_buf(c_wdata_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_reset [axi_datamover_reset_default]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=4,c_dwidth=8...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=8,c_dep...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=8,c_depth=4...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=8,c...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.cntr_incr_decr_addn_f [\cntr_incr_decr_addn_f(c_size=3,...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=4,c_dwidth=6...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=68,c_de...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=68,c_depth=...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=68,...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_cmd_status [\axi_datamover_cmd_status(c_fami...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_rd_status_cntl [axi_datamover_rd_status_cntl_def...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_strb_gen2 [\axi_datamover_strb_gen2(c_strb_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_strb_gen2 [\axi_datamover_strb_gen2(c_op_mo...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_pcc [\axi_datamover_pcc(c_is_mm2s=1,c...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=3,c_dwidth=5...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=59,c_de...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=59,c_depth=...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=59,...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_addr_cntl [\axi_datamover_addr_cntl(c_addr_...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=3,c_dwidth=5...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=55,c_de...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=55,c_depth=...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=55,...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_rdmux [\axi_datamover_rdmux(c_sel_addr_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_rddata_cntl [\axi_datamover_rddata_cntl(c_ali...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_mm2s_full_wrap [\axi_datamover_mm2s_full_wrap(c_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_ibttcc [\axi_datamover_ibttcc(c_sf_xfer_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_dre_mux2_1_x_n [\axi_datamover_dre_mux2_1_x_n(c_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_dre_mux4_1_x_n [\axi_datamover_dre_mux4_1_x_n(c_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_dre_mux8_1_x_n [\axi_datamover_dre_mux8_1_x_n(c_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_s2mm_dre [axi_datamover_s2mm_dre_default]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_ms_strb_set [axi_datamover_ms_strb_set_defaul...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_mssai_skid_buf [\axi_datamover_mssai_skid_buf(c_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_strb_gen2 [axi_datamover_strb_gen2_default]
Compiling architecture working of entity axi_datamover_v5_1_31.axi_datamover_slice [\axi_datamover_slice(c_data_widt...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.cntr_incr_decr_addn_f [\cntr_incr_decr_addn_f(c_size=5,...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=16,c_dwidth=...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=14,c_fa...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=14,c_family...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=14,...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_s2mm_scatter [\axi_datamover_s2mm_scatter(c_en...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=4,c_dwidth=3...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=38,c_de...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=38,c_depth=...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=38,...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_s2mm_realign [\axi_datamover_s2mm_realign(c_en...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_stbs_set [axi_datamover_stbs_set_default]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_stbs_set [\axi_datamover_stbs_set(c_strobe...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_skid_buf [\axi_datamover_skid_buf(c_wdata_...]
Compiling module xpm.xpm_fifo_rst_default_1
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=5...
Compiling module xpm.xpm_counter_updn
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=1...
Compiling module xpm.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling architecture implementation of entity lib_fifo_v1_0_18.sync_fifo_fg [\sync_fifo_fg(c_family="kintexup...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_sfifo_autord [\axi_datamover_sfifo_autord(c_dw...]
Compiling module xpm.xpm_fifo_rst_default_2
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
Compiling module xpm.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling architecture implementation of entity lib_fifo_v1_0_18.sync_fifo_fg [\sync_fifo_fg(c_family="kintexup...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_sfifo_autord [\axi_datamover_sfifo_autord(c_dw...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_indet_btt [\axi_datamover_indet_btt(c_ibtt_...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=4,c_dwidth=3...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=32,c_de...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=32,c_depth=...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_family="ki...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_cmd_status [\axi_datamover_cmd_status(c_sts_...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=6,c_dwidth=3...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=30,c_de...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=30,c_depth=...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=30,...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.cntr_incr_decr_addn_f [\cntr_incr_decr_addn_f(c_size=4,...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=6,c_dwidth=2...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=2,c_dep...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=2,c_depth=6...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=2,c...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_wr_status_cntl [\axi_datamover_wr_status_cntl(c_...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=4,c_dwidth=5...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=59,c_de...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=59,c_depth=...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=59,...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_addr_cntl [\axi_datamover_addr_cntl(c_addr_...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=4,c_dwidth=5...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=53,c_de...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=53,c_depth=...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=53,...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_wrdata_cntl [\axi_datamover_wrdata_cntl(c_rea...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_wr_demux [\axi_datamover_wr_demux(c_sel_ad...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_skid2mm_buf [\axi_datamover_skid2mm_buf(c_mda...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_s2mm_full_wrap [\axi_datamover_s2mm_full_wrap(c_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover [\axi_datamover(c_include_mm2s=1,...]
Compiling architecture axi_datamover_0_arch of entity xil_defaultlib.axi_datamover_0 [axi_datamover_0_default]
Compiling module xil_defaultlib.ccsds122_addr_calc(AXI_ADDR_W=32...
Compiling module xil_defaultlib.ila_1
Compiling module xil_defaultlib.ccsds122_stream_ctrl(AXI_ADDR_W=...
Compiling module fifo_generator_v13_2_9.fifo_generator_v13_2_9_bhv_ver_s...
Compiling module fifo_generator_v13_2_9.fifo_generator_v13_2_9_bhv_ver_p...
Compiling module fifo_generator_v13_2_9.fifo_generator_v13_2_9_CONV_VER(...
Compiling module fifo_generator_v13_2_9.fifo_generator_vlog_beh(C_COMMON...
Compiling module xil_defaultlib.fifo_generator_0
Compiling module xil_defaultlib.ccsds122_bubble_removal_ctrl(AXI...
Compiling module xil_defaultlib.ccsds122p_ingress_frontend_defau...
Compiling module xil_defaultlib.ccsds122p_dwt_m97_lift_core(COEF...
Compiling module xil_defaultlib.ccsds122p_dwt_h_stage(ROW_SAMPLE...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=61...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xil_defaultlib.ccsds122p_dwt_v_stage(STAGE_SAMP...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=30...
Compiling module xil_defaultlib.ccsds122p_dwt_ll_row_order(STAGE...
Compiling module xil_defaultlib.ccsds122p_dwt_split_stage(STAGE_...
Compiling module xil_defaultlib.ccsds122p_dwt_l0(ENABLE_PROTOCOL...
Compiling module xil_defaultlib.ccsds122p_dwt_h_stage(ROW_SAMPLE...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=30...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xil_defaultlib.ccsds122p_dwt_v_stage(STAGE_SAMP...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=15...
Compiling module xil_defaultlib.ccsds122p_dwt_ll_row_order(STAGE...
Compiling module xil_defaultlib.ccsds122p_dwt_split_stage(STAGE_...
Compiling module xil_defaultlib.ccsds122p_dwt_l1(ENABLE_PROTOCOL...
Compiling module xil_defaultlib.ccsds122p_dwt_h_stage(ROW_SAMPLE...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=15...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xil_defaultlib.ccsds122p_dwt_v_stage(STAGE_SAMP...
Compiling module xil_defaultlib.ccsds122p_dwt_l2(ENABLE_PROTOCOL...
Compiling module xil_defaultlib.ccsds122p_dwt_merge(ENABLE_PROTO...
Compiling module xil_defaultlib.ccsds122p_subband_router(ENABLE_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=15...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram_masked(DATA...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=81...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xil_defaultlib.ccsds122p_segment_reorder(ENABLE...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=24...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xil_defaultlib.ccsds122p_segment_bank
Compiling module xil_defaultlib.ccsds122p_segment_fill(ENABLE_PR...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=25...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xil_defaultlib.ccsds122p_block_state_ram(DATA_W...
Compiling module xil_defaultlib.ccsds122p_segment_state_bank
Compiling module xil_defaultlib.ccsds122p_dc_option_select
Compiling module xil_defaultlib.ccsds122p_dc_code_emitter
Compiling module xil_defaultlib.ccsds122p_dc_entropy_encoder
Compiling module xil_defaultlib.ccsds122p_ac_depth_option_select...
Compiling module xil_defaultlib.ccsds122p_ac_depth_code_emitter_...
Compiling module xil_defaultlib.ccsds122p_ac_depth_encoder_defau...
Compiling module xil_defaultlib.ccsds122p_ac_stage0_dc_emit
Compiling module xil_defaultlib.ccsds122p_segment_block_reader
Compiling module xil_defaultlib.ccsds122p_stage_block_scan(FIXED...
Compiling module xil_defaultlib.ccsds122p_stage_pattern_map
Compiling module xil_defaultlib.ccsds122p_stage_option_select(US...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=15...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=14...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=51...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=33...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xil_defaultlib.ccsds122p_stage_rice_emitter
Compiling module xil_defaultlib.ccsds122p_stage_symbol_emit
Compiling module xil_defaultlib.ccsds122p_stage_refine_emit
Compiling module xil_defaultlib.ccsds122p_ac_bitplane_cached_com...
Compiling module xil_defaultlib.ccsds122p_ac_bitplane_gaggle_enc...
Compiling module xil_defaultlib.ccsds122p_segment_encoder_core
Compiling module xil_defaultlib.ccsds122p_bitstream_packer(ENABL...
Compiling module xil_defaultlib.ccsds122p_backend_lane(ENABLE_PR...
Compiling module xil_defaultlib.ccsds122p_bit_length24(BITS_W=32...
Compiling module xil_defaultlib.ccsds122p_segment_bitdepth
Compiling module xil_defaultlib.ccsds122p_header_writer_default
Compiling module xil_defaultlib.ccsds122p_segment_stats
Compiling module xil_defaultlib.ccsds122p_dc_seed
Compiling module xil_defaultlib.ccsds122p_block_state_pack_defau...
Compiling module xil_defaultlib.ccsds122p_segment_first_pass(OWN...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=23...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xil_defaultlib.ccsds122p_encoded_segment_reorde...
Compiling module xil_defaultlib.ccsds122p_backend_farm(LANE_COUN...
Compiling module xil_defaultlib.top_bpe_encoder(BACKEND_LANE_COU...
Compiling module xil_defaultlib.ccsds122_compression_top(AXI_ADD...
Compiling module xil_defaultlib.ccsds122_datamover(MEMORY_BLOCK_...
Compiling module xil_defaultlib.design_1_ccsds122_datamover_0_0
Compiling module xil_defaultlib.uart_rx
Compiling module xil_defaultlib.uart_tx
Compiling module xil_defaultlib.vio_0
Compiling module xil_defaultlib.axi_uart_upload_default
Compiling module xil_defaultlib.ccsds_uart_axi_default
Compiling module xil_defaultlib.design_1_ccsds_uart_axi_0_0
Compiling module unisims_ver.BUFG
Compiling module unisims_ver.MMCME4_ADV(CLKFBOUT_MULT_F=7.0,C...
Compiling module xil_defaultlib.ddr4_v2_2_20_infrastructure(CLKI...
Compiling module unisims_ver.OBUF
Compiling module unisims_ver.IBUFDS(IBUF_LOW_PWR="FALSE")
Compiling module unisims_ver.PLLE4_ADV(CLKFBOUT_MULT=4,CLKFBO...
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_pll(PLL_WIDTH=2,...
Compiling module unisims_ver.HPIO_VREF(VREF_CNTR="FABRIC_RANG...
Compiling module unisims_ver.IOBUFE3_default
Compiling module unisims_ver.IOBUFDS
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_iob_byte(IOBTYPE...
Compiling module unisims_ver.OBUFDS
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_iob_byte(IOBTYPE...
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_iob_byte(IOBTYPE...
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_iob_byte(IOBTYPE...
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_iob(BYTES=6,IOBT...
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_fifo_sv(DEPTH=16...
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_bitslice_behav
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_xiphy_behav(BYTE...
Compiling module xil_defaultlib.design_1_ddr4_0_0_phy_ddr4_defau...
Compiling module xil_defaultlib.design_1_ddr4_0_0_phy
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_group(ABITS=17,A...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_act_rank(tFAW=28...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_act_timer(tFAW=2...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_arb_a
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_wtr(tWTR_L=6,tWT...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_rd_wr(tWTR_L=6,t...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_arb_c_default
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_arb_p
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_cmd_mux_ap(ABITS...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_arb_mux_p(ABITS=...
WARNING: [VRFC 10-3705] select index 2 into 'rank' is out of bounds [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_cal_mc_odt.sv:148]
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_mc_odt(ODTBITS=...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_ctl(ABITS=17,BGB...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_cmd_mux_c
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_ref(LR_WIDTH=1,S...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_periodic
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_ecc(TCQ=0.1,PAYL...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc(ABITS=17,BGBITS=...
Compiling module xil_defaultlib.ddr4_v2_2_20_ui_cmd(TCQ=100.0,AD...
Compiling module unisims_ver.RAM32M
Compiling module xil_defaultlib.ddr4_v2_2_20_ui_wr_data(TCQ=100....
Compiling module xil_defaultlib.ddr4_v2_2_20_ui_rd_data(TCQ=100....
Compiling module xil_defaultlib.ddr4_v2_2_20_ui(TCQ=100.0,ADDR_W...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_debug_microblaz...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_cplx_data_defau...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_cplx(ABITS=17,B...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_addr_decode(DRA...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_config_rom(MEM0...
Compiling module xil_defaultlib.ddr4_v2_2_20_chipscope_xsdb_slav...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_sync(WIDTH=1)
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_sync(WIDTH=16)
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_sync(WIDTH=9)
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_xsdb_arbiter
Compiling module xil_defaultlib.ddr4_v2_2_20_bram_tdp(INIT=2304'...
Compiling module xil_defaultlib.ddr4_v2_2_20_cfg_mem_mod(SIZE=36...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_xsdb_bram(DBYTE...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal(ABITS=17,BGBITS...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_rd_en(RL=32'b01...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_read(RL=32'b010...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_wr_bit
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_wr_byte_default
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_write(WL=32'b01...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_pi(RL=32'b01011...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_top(ABITS=17,BG...
Compiling module unisims_ver.VCC
Compiling module unisims_ver.GND
Compiling module unisims_ver.FDRE_default
Compiling module unisims_ver.FDR
Compiling module unisims_ver.FDSE_default
Compiling module unisims_ver.FDS
Compiling module unisims_ver.FD
Compiling module unisims_ver.FDRE(INIT=1'b1)
Compiling module unisims_ver.FD(INIT=1'b1)
Compiling module unisims_ver.RAM32X1D
Compiling module unisims_ver.FDE
Compiling module unisims_ver.LUT6_2
Compiling module unisims_ver.MUXCY
Compiling module unisims_ver.MUXCY_L
Compiling module unisims_ver.XORCY
Compiling module unisims_ver.x_lut2_mux4
Compiling module unisims_ver.LUT2
Compiling module unisims_ver.MULT_AND
Compiling module unisims_ver.x_lut3_mux8
Compiling module unisims_ver.LUT3
Compiling module unisims_ver.LUT4
Compiling module unisims_ver.LUT6
Compiling module unisims_ver.MUXF5
Compiling module unisims_ver.SRL16E_default
Compiling module unisims_ver.LUT5
Compiling module unisims_ver.FDSE(INIT=1'b0)
Compiling module unisims_ver.x_lut1_mux2
Compiling module unisims_ver.LUT1
Compiling module unisims_ver.MUXF7
Compiling module unisims_ver.INV
Compiling module unisims_ver.RB36_INTERNAL_VLOG(READ_WIDTH_A=...
Compiling module unisims_ver.RAMB36E1(READ_WIDTH_A=2,READ_WID...
Compiling module unisims_ver.RAMB36(READ_WIDTH_A=2,READ_WIDTH...
Compiling module xil_defaultlib.microblaze_mcs
Compiling module xil_defaultlib.design_1_ddr4_0_0_microblaze_mcs
Compiling module xil_defaultlib.design_1_ddr4_0_0_ddr4_cal_riu
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_sync(WIDTH=1,TC...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_sync(WIDTH=32,T...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_sync(WIDTH=20,T...
Compiling module xil_defaultlib.design_1_ddr4_0_0_ddr4_mem_intfc...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_register_slice(...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_register_slice(...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_register_slice(...
Compiling module xil_defaultlib.ddr4_v2_2_20_command_fifo(C_FAMI...
Compiling module xil_defaultlib.ddr4_v2_2_20_a_upsizer(C_AXI_ID_...
Compiling module xil_defaultlib.ddr4_v2_2_20_w_upsizer(C_S_AXI_D...
Compiling module xil_defaultlib.ddr4_v2_2_20_r_upsizer(C_AXI_ID_...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_upsizer(C_AXI_I...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_register_slice(...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_incr_cmd(C_AXI_...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_wrap_cmd(C_AXI_...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_cmd_translator(...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_wr_cmd_fsm
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_aw_channel(C_ID...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_w_channel(C_DAT...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_fifo(C_WIDTH=1,...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_b_channel(C_ID_...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_incr_cmd(C_AXI_...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_wrap_cmd(C_AXI_...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_cmd_translator(...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_cmd_fsm(C_MC_RD...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_ar_channel(C_ID...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_fifo(C_WIDTH=25...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_fifo(C_WIDTH=4,...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_r_channel(C_ID_...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_cmd_arbiter(C_M...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi(C_S_AXI_ID_WIDT...
Compiling module xil_defaultlib.design_1_ddr4_0_0_ddr4_default
Compiling module xil_defaultlib.design_1_ddr4_0_0
Compiling module xil_defaultlib.design_1_ila_0_0
Compiling architecture fdre_v of entity unisim.FDRE [fdre_default]
Compiling architecture fdre_v of entity unisim.FDRE [\FDRE(init='1')\]
Compiling architecture fdr_v of entity unisim.FDR [fdr_default]
Compiling architecture implementation of entity lib_cdc_v1_0_2.cdc_sync [\cdc_sync(c_vector_width=2,c_mtb...]
Compiling architecture srl16e_v of entity unisim.SRL16E [\SRL16E(init="1111111111111111")...]
Compiling architecture srl16_v of entity unisim.SRL16 [\SRL16(init="1111111111111111")(...]
Compiling architecture imp of entity proc_sys_reset_v5_0_14.lpf [\lpf(c_ext_rst_width=4,c_aux_rst...]
Compiling architecture imp of entity proc_sys_reset_v5_0_14.upcnt_n [\upcnt_n(c_size=6)\]
Compiling architecture imp of entity proc_sys_reset_v5_0_14.sequence_psr [sequence_psr_default]
Compiling architecture imp of entity proc_sys_reset_v5_0_14.proc_sys_reset [\proc_sys_reset(c_family="kintex...]
Compiling architecture design_1_proc_sys_reset_0_0_arch of entity xil_defaultlib.design_1_proc_sys_reset_0_0 [design_1_proc_sys_reset_0_0_defa...]
Compiling module xlconstant_v1_1_8.xlconstant_v1_1_8_xlconstant(CON...
Compiling module xil_defaultlib.bd_886d_one_0
Compiling architecture imp of entity proc_sys_reset_v5_0_14.lpf [\lpf(c_ext_rst_width=4,c_aux_rst...]
Compiling architecture imp of entity proc_sys_reset_v5_0_14.proc_sys_reset [\proc_sys_reset(c_family="kintex...]
Compiling architecture bd_886d_psr0_0_arch of entity xil_defaultlib.bd_886d_psr0_0 [bd_886d_psr0_0_default]
Compiling architecture bd_886d_psr_aclk_0_arch of entity xil_defaultlib.bd_886d_psr_aclk_0 [bd_886d_psr_aclk_0_default]
Compiling architecture bd_886d_psr_aclk1_0_arch of entity xil_defaultlib.bd_886d_psr_aclk1_0 [bd_886d_psr_aclk1_0_default]
Compiling module xil_defaultlib.clk_map_imp_1WP46Y0
Compiling module xpm.xpm_cdc_async_rst(DEST_SYNC_FF=3...
Compiling module xil_defaultlib.bd_886d_m00e_0
Compiling module xil_defaultlib.m00_exit_pipeline_imp_4816GJ
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=52...
Compiling module xil_defaultlib.bd_886d_m00arn_0
Compiling module xil_defaultlib.bd_886d_m00awn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=67...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=32...
Compiling module xil_defaultlib.bd_886d_m00bn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=48...
Compiling module xil_defaultlib.bd_886d_m00rn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=4,...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=57...
Compiling module xil_defaultlib.bd_886d_m00wn_0
Compiling module xil_defaultlib.m00_nodes_imp_QDFR33
Compiling module xil_defaultlib.bd_886d_m00s2a_0
Compiling module xil_defaultlib.bd_886d_m01e_0
Compiling module xil_defaultlib.m01_exit_pipeline_imp_6OCSAB
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=32...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=52...
Compiling module xil_defaultlib.bd_886d_m01arn_0
Compiling module xil_defaultlib.bd_886d_m01awn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=67...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=32...
Compiling module xil_defaultlib.bd_886d_m01bn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=48...
Compiling module xil_defaultlib.bd_886d_m01rn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=57...
Compiling module xil_defaultlib.bd_886d_m01wn_0
Compiling module xil_defaultlib.m01_nodes_imp_1HTXBQH
Compiling module xil_defaultlib.bd_886d_m01s2a_0
Compiling module xil_defaultlib.bd_886d_s00a2s_0
Compiling module xil_defaultlib.bd_886d_s00mmu_0
Compiling module xil_defaultlib.bd_886d_s00sic_0
Compiling module xil_defaultlib.bd_886d_s00tr_0
Compiling module xil_defaultlib.s00_entry_pipeline_imp_12V3TGW
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=60...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=46...
Compiling module xil_defaultlib.bd_886d_sarn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=54...
Compiling module xil_defaultlib.bd_886d_srn_0
Compiling module xil_defaultlib.s00_nodes_imp_16MUXNU
Compiling module xil_defaultlib.bd_886d_s01a2s_0
Compiling module xil_defaultlib.bd_886d_s01mmu_0
Compiling module xil_defaultlib.bd_886d_s01sic_0
Compiling module xil_defaultlib.bd_886d_s01tr_0
Compiling module xil_defaultlib.s01_entry_pipeline_imp_6HKV8K
Compiling module xil_defaultlib.bd_886d_sawn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=89...
Compiling module xil_defaultlib.bd_886d_sbn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=51...
Compiling module xil_defaultlib.bd_886d_swn_0
Compiling module xil_defaultlib.s01_nodes_imp_1AH57G
Compiling module xil_defaultlib.bd_886d_s02a2s_0
Compiling module xil_defaultlib.bd_886d_s02mmu_0
Compiling module xil_defaultlib.bd_886d_s02sic_0
Compiling module xil_defaultlib.bd_886d_s02tr_0
Compiling module xil_defaultlib.s02_entry_pipeline_imp_R26R6H
Compiling module xil_defaultlib.bd_886d_sarn_1
Compiling module xil_defaultlib.bd_886d_sawn_1
Compiling module xil_defaultlib.bd_886d_sbn_1
Compiling module xil_defaultlib.bd_886d_srn_1
Compiling module xil_defaultlib.bd_886d_swn_1
Compiling module xil_defaultlib.s02_nodes_imp_XIDFT3
Compiling module xil_defaultlib.bd_886d_s03a2s_0
Compiling module xil_defaultlib.bd_886d_s03mmu_0
Compiling module xil_defaultlib.bd_886d_s03sic_0
Compiling module xil_defaultlib.bd_886d_s03tr_0
Compiling module xil_defaultlib.s03_entry_pipeline_imp_1XMQ8JX
Compiling module xil_defaultlib.bd_886d_sarn_2
Compiling module xil_defaultlib.bd_886d_sawn_2
Compiling module xil_defaultlib.bd_886d_sbn_2
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=54...
Compiling module xil_defaultlib.bd_886d_srn_2
Compiling module xil_defaultlib.bd_886d_swn_2
Compiling module xil_defaultlib.s03_nodes_imp_1RRAM9D
Compiling module xil_defaultlib.bd_886d_arsw_0
Compiling module xil_defaultlib.bd_886d_awsw_0
Compiling module xil_defaultlib.bd_886d_bsw_0
Compiling module xil_defaultlib.bd_886d_rsw_0
Compiling module xil_defaultlib.bd_886d_wsw_0
Compiling module xil_defaultlib.switchboards_imp_1V8ZM66
Compiling module xil_defaultlib.bd_886d
Compiling module xil_defaultlib.design_1_smartconnect_0_1
Compiling module xil_defaultlib.bd_f60c_g_inst_0_gigantic_mux(C_...
Compiling module xil_defaultlib.bd_f60c_g_inst_0
Compiling module xil_defaultlib.bd_f60c_ila_lib_0
Compiling module xlconcat_v2_1_5.xlconcat_v2_1_5_xlconcat_default
Compiling module xil_defaultlib.bd_f60c_slot_0_ar_0
Compiling module xil_defaultlib.bd_f60c_slot_0_aw_0
Compiling module xil_defaultlib.bd_f60c_slot_0_b_0
Compiling module xlconcat_v2_1_5.xlconcat_v2_1_5_xlconcat(dout_wi...
Compiling module xil_defaultlib.bd_f60c_slot_0_r_0
Compiling module xil_defaultlib.bd_f60c_slot_0_w_0
Compiling module xil_defaultlib.bd_f60c_slot_1_ar_0
Compiling module xil_defaultlib.bd_f60c_slot_1_aw_0
Compiling module xil_defaultlib.bd_f60c_slot_1_b_0
Compiling module xil_defaultlib.bd_f60c_slot_1_r_0
Compiling module xil_defaultlib.bd_f60c_slot_1_w_0
Compiling module xil_defaultlib.bd_f60c_slot_2_ar_0
Compiling module xil_defaultlib.bd_f60c_slot_2_aw_0
Compiling module xil_defaultlib.bd_f60c_slot_2_b_0
Compiling module xil_defaultlib.bd_f60c_slot_2_r_0
Compiling module xil_defaultlib.bd_f60c_slot_2_w_0
Compiling module xil_defaultlib.bd_f60c_slot_3_ar_0
Compiling module xil_defaultlib.bd_f60c_slot_3_aw_0
Compiling module xil_defaultlib.bd_f60c_slot_3_b_0
Compiling module xil_defaultlib.bd_f60c_slot_3_r_0
Compiling module xil_defaultlib.bd_f60c_slot_3_w_0
Compiling module xil_defaultlib.bd_f60c
Compiling module xil_defaultlib.design_1_system_ila_0_0
Compiling module util_vector_logic_v2_0_3.util_vector_logic_v2_0_3_util_ve...
Compiling module xil_defaultlib.design_1_util_vector_logic_0_4
Compiling module xil_defaultlib.design_1
Compiling module xil_defaultlib.design_1_wrapper
Compiling module xil_defaultlib.tb_design_1_wrapper
Compiling module xil_defaultlib.glbl
Built simulation snapshot tb_design_1_wrapper_behav
run_program: Time (s): cpu = 00:00:04 ; elapsed = 00:01:05 . Memory (MB): peak = 3664.047 ; gain = 0.000
INFO: [USF-XSim-69] 'elaborate' step finished in '66' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_design_1_wrapper_behav -key {Behavioral:sim_1:Functional:tb_design_1_wrapper} -tclbatch {tb_design_1_wrapper.tcl} -protoinst "protoinst_files/bd_886d.protoinst" -protoinst "protoinst_files/bd_45eb.protoinst" -protoinst "protoinst_files/bd_f60c.protoinst" -protoinst "protoinst_files/design_1.protoinst" -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/bd_886d.protoinst
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m00_exit_pipeline/m00_exit/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m00_exit_pipeline/m00_exit/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m00_exit_pipeline/m_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m00_exit_pipeline/s_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m00_nodes/m00_aw_node/M_AXIS_ARB
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m00_nodes/m00_w_node/S_AXIS_ARB
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m00_sc2axi/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m01_exit_pipeline/m01_exit/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m01_exit_pipeline/m01_exit/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m01_exit_pipeline/m_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m01_exit_pipeline/s_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m01_nodes/m01_aw_node/M_AXIS_ARB
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m01_nodes/m01_w_node/S_AXIS_ARB
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m01_sc2axi/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_axi2sc/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/m_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/s00_mmu/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/s00_mmu/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/s00_si_converter/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/s00_si_converter/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/s00_transaction_regulator/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/s00_transaction_regulator/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/s_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_axi2sc/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/m_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/s01_mmu/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/s01_mmu/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/s01_si_converter/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/s01_si_converter/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/s01_transaction_regulator/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/s01_transaction_regulator/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/s_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_axi2sc/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_entry_pipeline/m_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_entry_pipeline/s02_mmu/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_entry_pipeline/s02_mmu/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_entry_pipeline/s02_si_converter/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_entry_pipeline/s02_si_converter/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_entry_pipeline/s02_transaction_regulator/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_entry_pipeline/s02_transaction_regulator/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_entry_pipeline/s_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_axi2sc/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_entry_pipeline/m_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_entry_pipeline/s03_mmu/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_entry_pipeline/s03_mmu/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_entry_pipeline/s03_si_converter/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_entry_pipeline/s03_si_converter/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_entry_pipeline/s03_transaction_regulator/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_entry_pipeline/s03_transaction_regulator/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_entry_pipeline/s_axi
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/bd_45eb.protoinst
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/bd_45eb.protoinst for the following reason(s):
There are no instances of module "bd_45eb" in the design.
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/bd_f60c.protoinst
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_1.protoinst
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//ccsds122_axil_slave_0/s_axil
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//ccsds122_datamover_0/m_axi_mm2s
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//ccsds122_datamover_0/m_axi_s2mm
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//ccsds_uart_axi_0/m_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//ccsds_uart_axi_0/m_axil
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//ddr4_0/C0_DDR4_S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//smartconnect_0/M00_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//smartconnect_0/M01_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//smartconnect_0/S00_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//smartconnect_0/S01_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//smartconnect_0/S02_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//smartconnect_0/S03_AXI
Time resolution is 1 ps
source tb_design_1_wrapper.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
==== TB: Waiting for DDR4 calib... ====
$finish called at time : 0 fs : File "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/tb_design_1_wrapper.sv" Line 99
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_design_1_wrapper_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:10 ; elapsed = 00:01:15 . Memory (MB): peak = 3664.047 ; gain = 0.000
current_wave_config {Untitled 3}
Untitled 3
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i}}
current_wave_config {Untitled 3}
Untitled 3
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/ccsds122_axil_slave_0}}
current_wave_config {Untitled 3}
Untitled 3
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl}}
current_wave_config {Untitled 3}
Untitled 3
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_bubble_removal}}
current_wave_config {Untitled 3}
Untitled 3
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/ccsds_uart_axi_0}}
current_wave_config {Untitled 3}
Untitled 3
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/ccsds_uart_axi_0/inst/u_core}}
restart
INFO: [Wavedata 42-604] Simulation restarted
run 7 ms
==== TB: Waiting for DDR4 calib... ====
$finish called at time : 0 fs : File "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/tb_design_1_wrapper.sv" Line 99
run 7 ms
[TB] DDR4 calib done @ 0 ps
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. tb_design_1_wrapper.u_dut.design_1_i.ccsds122_datamover_0.inst.u_datamover.U0.gen_s2mm_full.I_S2MM_FULL_WRAPPER.gen_enable_indet_btt_sf.I_INDET_BTT.I_XD_FIFO.non_blk_mem.I_SYNC_FIFOGEN_FIFO.xpm_fifo_instance.xpm_fifo_sync_inst.xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/ccsds122_datamover_0/inst/u_datamover/U0/gen_s2mm_full/I_S2MM_FULL_WRAPPER/gen_enable_indet_btt_sf/I_INDET_BTT/I_XD_FIFO/non_blk_mem/I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance/xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial302_83 Scope: tb_design_1_wrapper.u_dut.design_1_i.ccsds122_datamover_0.inst.u_datamover.U0.gen_s2mm_full.I_S2MM_FULL_WRAPPER.gen_enable_indet_btt_sf.I_INDET_BTT.I_XD_FIFO.non_blk_mem.I_SYNC_FIFOGEN_FIFO.xpm_fifo_instance.xpm_fifo_sync_inst.xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 506
[2/6] Config registers
Info: [Unisim HPIO_VREF-1] Fabric Tune Value changed to 0011111. Instance: tb_design_1_wrapper.u_dut.design_1_i.ddr4_0.inst.u_ddr4_mem_intfc.u_mig_ddr4_phy.inst.u_ddr_iob.\genByte[0].u_ddr_iob_byte .\genblk1.genVref.u_hpio_vref
Info: [Unisim HPIO_VREF-1] Fabric Tune Value changed to 0011111. Instance: tb_design_1_wrapper.u_dut.design_1_i.ddr4_0.inst.u_ddr4_mem_intfc.u_mig_ddr4_phy.inst.u_ddr_iob.\genByte[3].u_ddr_iob_byte .\genblk1.genVref.u_hpio_vref
Info: [Unisim HPIO_VREF-1] Fabric Tune Value changed to 0011111. Instance: tb_design_1_wrapper.u_dut.design_1_i.ddr4_0.inst.u_ddr4_mem_intfc.u_mig_ddr4_phy.inst.u_ddr_iob.\genByte[4].u_ddr_iob_byte .\genblk1.genVref.u_hpio_vref
Info: [Unisim HPIO_VREF-1] Fabric Tune Value changed to 0011111. Instance: tb_design_1_wrapper.u_dut.design_1_i.ddr4_0.inst.u_ddr4_mem_intfc.u_mig_ddr4_phy.inst.u_ddr_iob.\genByte[5].u_ddr_iob_byte .\genblk1.genVref.u_hpio_vref
[TB] Reset released @ 2498000 ps
[3/6] Start compress
[4/6] Poll STATUS
run: Time (s): cpu = 00:02:58 ; elapsed = 00:05:48 . Memory (MB): peak = 3929.680 ; gain = 265.633
open_bd_design {C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd}
Reading block design file <C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd>...
Adding component instance block -- xilinx.com:user:ccsds122_datamover:1.0 - ccsds122_datamover_0
Adding component instance block -- xilinx.com:ip:smartconnect:1.0 - smartconnect_0
Adding component instance block -- xilinx.com:user:ccsds122_axil_slave:1.0 - ccsds122_axil_slave_0
Adding component instance block -- xilinx.com:ip:ila:6.2 - ila_0
INFO: [xilinx.com:ip:ila:6.2-6] /ila_0: AMD recommends using the System ILA IP in IP Integrator. The System ILA IP is functionally equivalent to an ILA and offers additional benefits in debugging interfaces both within IP Integrator and the Hardware Manager. Consult the Programming and Debug User Guide UG908 for further details.
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - proc_sys_reset_0
Adding component instance block -- xilinx.com:user:ccsds_uart_axi:1.0 - ccsds_uart_axi_0
Adding component instance block -- xilinx.com:ip:ddr4:2.2 - ddr4_0
Adding component instance block -- xilinx.com:ip:util_vector_logic:2.0 - util_vector_logic_0
Adding component instance block -- xilinx.com:ip:system_ila:1.1 - system_ila_0
Successfully read diagram <design_1> from block design file <C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd>
close_bd_design [get_bd_designs design_1]
Wrote : <C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
current_wave_config {Untitled 3}
Untitled 3
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/ccsds_uart_axi_0}}
current_wave_config {Untitled 3}
Untitled 3
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/ccsds_uart_axi_0/inst/u_core}}
current_wave_config {Untitled 3}
Untitled 3
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/ccsds_uart_axi_0/inst/u_core}}
close_sim
INFO: xsimkernel Simulation Memory Usage: 97136 KB (Peak: 97136 KB), Simulation CPU Usage: 340936 ms
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-12493] Simulation top is 'tb_design_1_wrapper'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
Generating merged BMM file for the design top 'tb_design_1_wrapper'...
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2023.2/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2023.2/data/xsim/xsim.ini' copied to run dir:'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim'
INFO: [SIM-utils-50] Design contains embedded sources, generating MEM files for simulation...
Generating merged BMM file for the design top 'tb_design_1_wrapper'...
WARNING: [Memdata 28-361] Design is having concatenated BRAM controllers(heterogenous memory), this configuration is not supported by Updatemem for current device part. Only the first BRAM controller will be added to .MMI and used by Updatemem to update the bitstream with new data.
Generating merged BMM file for the design top 'tb_design_1_wrapper'...
INFO: [SIM-utils-54] Inspecting design source files for 'tb_design_1_wrapper' in fileset 'sim_1'...
INFO: [SIM-utils-43] Exported 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim/sc_xtlm_design_1_smartconnect_0_1.mem'
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim'
"xvlog --incr --relax -L uvm -L axi_vip_v1_1_15 -L smartconnect_v1_0 -L xilinx_vip -prj tb_design_1_wrapper_vlog.prj"
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/tb_design_1_wrapper.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module tb_design_1_wrapper
"xvhdl --incr --relax -prj tb_design_1_wrapper_vhdl.prj"
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim'
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L fifo_generator_v13_2_9 -L lib_pkg_v1_0_3 -L lib_fifo_v1_0_18 -L lib_srl_fifo_v1_0_3 -L lib_cdc_v1_0_2 -L axi_datamover_v5_1_31 -L xlconstant_v1_1_8 -L proc_sys_reset_v5_0_14 -L smartconnect_v1_0 -L axi_infrastructure_v1_1_0 -L axi_register_slice_v2_1_29 -L axi_vip_v1_1_15 -L microblaze_v11_0_12 -L lmb_v10_v3_0_13 -L lmb_bram_if_cntlr_v4_0_23 -L blk_mem_gen_v8_4_7 -L iomodule_v3_1_9 -L util_vector_logic_v2_0_3 -L gigantic_mux -L xlconcat_v2_1_5 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_design_1_wrapper_behav xil_defaultlib.tb_design_1_wrapper xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator v2023.2
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2023.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L fifo_generator_v13_2_9 -L lib_pkg_v1_0_3 -L lib_fifo_v1_0_18 -L lib_srl_fifo_v1_0_3 -L lib_cdc_v1_0_2 -L axi_datamover_v5_1_31 -L xlconstant_v1_1_8 -L proc_sys_reset_v5_0_14 -L smartconnect_v1_0 -L axi_infrastructure_v1_1_0 -L axi_register_slice_v2_1_29 -L axi_vip_v1_1_15 -L microblaze_v11_0_12 -L lmb_v10_v3_0_13 -L lmb_bram_if_cntlr_v4_0_23 -L blk_mem_gen_v8_4_7 -L iomodule_v3_1_9 -L util_vector_logic_v2_0_3 -L gigantic_mux -L xlconcat_v2_1_5 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_design_1_wrapper_behav xil_defaultlib.tb_design_1_wrapper xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-8809] cannot index into scalar type parameter/localparam 'DEBUG_MESSAGES' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv:234]
WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 2 for port 'm_axil_awprot' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/08a1/src/ccsds_uart_axi.sv:190]
WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 2 for port 'm_axil_arprot' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/08a1/src/ccsds_uart_axi.sv:202]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_awid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2822]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_bid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2837]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_arid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2841]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_rid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2851]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_awid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2866]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_bid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2881]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_arid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2885]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_rid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2895]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_awid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2954]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_3_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2960]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_bid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2969]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_arid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2973]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_3_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2978]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_rid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2983]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_4_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3004]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_4_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3022]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_5_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3048]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_5_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3066]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_6_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3092]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_6_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3110]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_7_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3136]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_7_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3154]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_8_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3180]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_8_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3198]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_9_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3224]
WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 4 for port 'slot_9_axi_wstrb' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3229]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_9_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3242]
WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 4 for port 'slot_9_axis_tstrb' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3256]
WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 4 for port 'slot_9_axis_tkeep' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3257]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_10_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3268]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_10_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3286]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_11_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3312]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_11_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3330]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_12_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3356]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_12_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3374]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_13_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3400]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_13_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3418]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_14_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3444]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_14_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3462]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_15_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3488]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_15_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3506]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 4 for port 'sel' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4406]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_awuser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4407]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_wuser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4408]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_buser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4409]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_ruser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4411]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_wuser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4413]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_buser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4414]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_aruser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4415]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_ruser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4416]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_2_axi_awuser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4417]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_2_axi_wuser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4418]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_2_axi_buser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4419]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_2_axi_aruser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4420]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_2_axi_ruser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4421]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_awuser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4422]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_wuser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4423]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_buser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4424]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_aruser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4425]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_ruser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4426]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_wid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4588]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_wid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4593]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_wid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4603]
WARNING: [VRFC 10-5021] port 'mb_reset' is not connected on this instance [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/sim/design_1.v:506]
WARNING: [VRFC 10-5021] port 'mb_reset' is not connected on this instance [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/sim/bd_886d.v:2249]
WARNING: [VRFC 10-5021] port 'mb_reset' is not connected on this instance [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/sim/bd_886d.v:2256]
WARNING: [VRFC 10-5021] port 'mb_reset' is not connected on this instance [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/sim/bd_886d.v:2263]
WARNING: [VRFC 10-3705] select index 2 into 'rank' is out of bounds [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_cal_mc_odt.sv:148]
Completed static elaboration
Starting simulation data flow analysis
WARNING: [XSIM 43-4398] File "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_cal_cplx.sv" Line 856 : The System Verilog Assertion will be ignored as it appears inside another process. This assertion is not yet supported.
WARNING: [XSIM 43-4398] File "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_cal_top.sv" Line 1813 : The System Verilog Assertion will be ignored as it appears inside another process. This assertion is not yet supported.
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_unsigned
Compiling package lib_pkg_v1_0_3.lib_pkg
Compiling package xpm.vcomponents
Compiling package synopsys.attributes
Compiling package ieee.std_logic_misc
Compiling package unisim.vcomponents
Compiling package ieee.vital_timing
Compiling package ieee.vital_primitives
Compiling package unisim.vpkg
Compiling package xpm.$unit_xpm_cdc_sv_220102727
Compiling package xpm.axi_xil_sb_pkg_xpm_nsu
Compiling package xpm.axi_data_integrity_checker_xpm_n...
Compiling package xpm.xpm_axi_data_integrity_checker_n...
Compiling package xpm.xpm_axi_xil_sb_pkg_nmu
Compiling package xil_defaultlib.ccsds122p_pkg
Compiling package smartconnect_v1_0.sc_util_v1_0_4_pkg
Compiling module xil_defaultlib.ccsds122_axil_slave
Compiling module xil_defaultlib.design_1_ccsds122_axil_slave_0_0
Compiling module xpm.xpm_fifo_rst_default
Compiling module xpm.xpm_fifo_reg_bit
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=8...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=7...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=2...
Compiling module xpm.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
Compiling module xpm.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling architecture implementation of entity lib_fifo_v1_0_18.sync_fifo_fg [\sync_fifo_fg(c_family="kintexup...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_sfifo_autord [\axi_datamover_sfifo_autord(c_dw...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_rd_sf [\axi_datamover_rd_sf(c_sf_fifo_d...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_skid_buf [\axi_datamover_skid_buf(c_wdata_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_reset [axi_datamover_reset_default]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=4,c_dwidth=8...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=8,c_dep...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=8,c_depth=4...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=8,c...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.cntr_incr_decr_addn_f [\cntr_incr_decr_addn_f(c_size=3,...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=4,c_dwidth=6...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=68,c_de...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=68,c_depth=...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=68,...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_cmd_status [\axi_datamover_cmd_status(c_fami...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_rd_status_cntl [axi_datamover_rd_status_cntl_def...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_strb_gen2 [\axi_datamover_strb_gen2(c_strb_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_strb_gen2 [\axi_datamover_strb_gen2(c_op_mo...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_pcc [\axi_datamover_pcc(c_is_mm2s=1,c...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=3,c_dwidth=5...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=59,c_de...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=59,c_depth=...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=59,...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_addr_cntl [\axi_datamover_addr_cntl(c_addr_...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=3,c_dwidth=5...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=55,c_de...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=55,c_depth=...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=55,...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_rdmux [\axi_datamover_rdmux(c_sel_addr_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_rddata_cntl [\axi_datamover_rddata_cntl(c_ali...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_mm2s_full_wrap [\axi_datamover_mm2s_full_wrap(c_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_ibttcc [\axi_datamover_ibttcc(c_sf_xfer_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_dre_mux2_1_x_n [\axi_datamover_dre_mux2_1_x_n(c_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_dre_mux4_1_x_n [\axi_datamover_dre_mux4_1_x_n(c_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_dre_mux8_1_x_n [\axi_datamover_dre_mux8_1_x_n(c_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_s2mm_dre [axi_datamover_s2mm_dre_default]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_ms_strb_set [axi_datamover_ms_strb_set_defaul...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_mssai_skid_buf [\axi_datamover_mssai_skid_buf(c_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_strb_gen2 [axi_datamover_strb_gen2_default]
Compiling architecture working of entity axi_datamover_v5_1_31.axi_datamover_slice [\axi_datamover_slice(c_data_widt...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.cntr_incr_decr_addn_f [\cntr_incr_decr_addn_f(c_size=5,...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=16,c_dwidth=...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=14,c_fa...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=14,c_family...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=14,...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_s2mm_scatter [\axi_datamover_s2mm_scatter(c_en...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=4,c_dwidth=3...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=38,c_de...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=38,c_depth=...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=38,...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_s2mm_realign [\axi_datamover_s2mm_realign(c_en...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_stbs_set [axi_datamover_stbs_set_default]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_stbs_set [\axi_datamover_stbs_set(c_strobe...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_skid_buf [\axi_datamover_skid_buf(c_wdata_...]
Compiling module xpm.xpm_fifo_rst_default_1
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=5...
Compiling module xpm.xpm_counter_updn
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=1...
Compiling module xpm.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling architecture implementation of entity lib_fifo_v1_0_18.sync_fifo_fg [\sync_fifo_fg(c_family="kintexup...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_sfifo_autord [\axi_datamover_sfifo_autord(c_dw...]
Compiling module xpm.xpm_fifo_rst_default_2
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
Compiling module xpm.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling architecture implementation of entity lib_fifo_v1_0_18.sync_fifo_fg [\sync_fifo_fg(c_family="kintexup...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_sfifo_autord [\axi_datamover_sfifo_autord(c_dw...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_indet_btt [\axi_datamover_indet_btt(c_ibtt_...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=4,c_dwidth=3...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=32,c_de...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=32,c_depth=...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_family="ki...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_cmd_status [\axi_datamover_cmd_status(c_sts_...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=6,c_dwidth=3...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=30,c_de...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=30,c_depth=...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=30,...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.cntr_incr_decr_addn_f [\cntr_incr_decr_addn_f(c_size=4,...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=6,c_dwidth=2...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=2,c_dep...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=2,c_depth=6...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=2,c...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_wr_status_cntl [\axi_datamover_wr_status_cntl(c_...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=4,c_dwidth=5...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=59,c_de...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=59,c_depth=...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=59,...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_addr_cntl [\axi_datamover_addr_cntl(c_addr_...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=4,c_dwidth=5...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=53,c_de...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=53,c_depth=...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=53,...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_wrdata_cntl [\axi_datamover_wrdata_cntl(c_rea...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_wr_demux [\axi_datamover_wr_demux(c_sel_ad...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_skid2mm_buf [\axi_datamover_skid2mm_buf(c_mda...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_s2mm_full_wrap [\axi_datamover_s2mm_full_wrap(c_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover [\axi_datamover(c_include_mm2s=1,...]
Compiling architecture axi_datamover_0_arch of entity xil_defaultlib.axi_datamover_0 [axi_datamover_0_default]
Compiling module xil_defaultlib.ccsds122_addr_calc(AXI_ADDR_W=32...
Compiling module xil_defaultlib.ila_1
Compiling module xil_defaultlib.ccsds122_stream_ctrl(AXI_ADDR_W=...
Compiling module fifo_generator_v13_2_9.fifo_generator_v13_2_9_bhv_ver_s...
Compiling module fifo_generator_v13_2_9.fifo_generator_v13_2_9_bhv_ver_p...
Compiling module fifo_generator_v13_2_9.fifo_generator_v13_2_9_CONV_VER(...
Compiling module fifo_generator_v13_2_9.fifo_generator_vlog_beh(C_COMMON...
Compiling module xil_defaultlib.fifo_generator_0
Compiling module xil_defaultlib.ccsds122_bubble_removal_ctrl(AXI...
Compiling module xil_defaultlib.ccsds122p_ingress_frontend_defau...
Compiling module xil_defaultlib.ccsds122p_dwt_m97_lift_core(COEF...
Compiling module xil_defaultlib.ccsds122p_dwt_h_stage(ROW_SAMPLE...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=61...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xil_defaultlib.ccsds122p_dwt_v_stage(STAGE_SAMP...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=30...
Compiling module xil_defaultlib.ccsds122p_dwt_ll_row_order(STAGE...
Compiling module xil_defaultlib.ccsds122p_dwt_split_stage(STAGE_...
Compiling module xil_defaultlib.ccsds122p_dwt_l0(ENABLE_PROTOCOL...
Compiling module xil_defaultlib.ccsds122p_dwt_h_stage(ROW_SAMPLE...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=30...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xil_defaultlib.ccsds122p_dwt_v_stage(STAGE_SAMP...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=15...
Compiling module xil_defaultlib.ccsds122p_dwt_ll_row_order(STAGE...
Compiling module xil_defaultlib.ccsds122p_dwt_split_stage(STAGE_...
Compiling module xil_defaultlib.ccsds122p_dwt_l1(ENABLE_PROTOCOL...
Compiling module xil_defaultlib.ccsds122p_dwt_h_stage(ROW_SAMPLE...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=15...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xil_defaultlib.ccsds122p_dwt_v_stage(STAGE_SAMP...
Compiling module xil_defaultlib.ccsds122p_dwt_l2(ENABLE_PROTOCOL...
Compiling module xil_defaultlib.ccsds122p_dwt_merge(ENABLE_PROTO...
Compiling module xil_defaultlib.ccsds122p_subband_router(ENABLE_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=15...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram_masked(DATA...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=81...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xil_defaultlib.ccsds122p_segment_reorder(ENABLE...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=24...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xil_defaultlib.ccsds122p_segment_bank
Compiling module xil_defaultlib.ccsds122p_segment_fill(ENABLE_PR...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=25...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xil_defaultlib.ccsds122p_block_state_ram(DATA_W...
Compiling module xil_defaultlib.ccsds122p_segment_state_bank
Compiling module xil_defaultlib.ccsds122p_dc_option_select
Compiling module xil_defaultlib.ccsds122p_dc_code_emitter
Compiling module xil_defaultlib.ccsds122p_dc_entropy_encoder
Compiling module xil_defaultlib.ccsds122p_ac_depth_option_select...
Compiling module xil_defaultlib.ccsds122p_ac_depth_code_emitter_...
Compiling module xil_defaultlib.ccsds122p_ac_depth_encoder_defau...
Compiling module xil_defaultlib.ccsds122p_ac_stage0_dc_emit
Compiling module xil_defaultlib.ccsds122p_segment_block_reader
Compiling module xil_defaultlib.ccsds122p_stage_block_scan(FIXED...
Compiling module xil_defaultlib.ccsds122p_stage_pattern_map
Compiling module xil_defaultlib.ccsds122p_stage_option_select(US...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=15...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=14...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=51...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=33...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xil_defaultlib.ccsds122p_stage_rice_emitter
Compiling module xil_defaultlib.ccsds122p_stage_symbol_emit
Compiling module xil_defaultlib.ccsds122p_stage_refine_emit
Compiling module xil_defaultlib.ccsds122p_ac_bitplane_cached_com...
Compiling module xil_defaultlib.ccsds122p_ac_bitplane_gaggle_enc...
Compiling module xil_defaultlib.ccsds122p_segment_encoder_core
Compiling module xil_defaultlib.ccsds122p_bitstream_packer(ENABL...
Compiling module xil_defaultlib.ccsds122p_backend_lane(ENABLE_PR...
Compiling module xil_defaultlib.ccsds122p_bit_length24(BITS_W=32...
Compiling module xil_defaultlib.ccsds122p_segment_bitdepth
Compiling module xil_defaultlib.ccsds122p_header_writer_default
Compiling module xil_defaultlib.ccsds122p_segment_stats
Compiling module xil_defaultlib.ccsds122p_dc_seed
Compiling module xil_defaultlib.ccsds122p_block_state_pack_defau...
Compiling module xil_defaultlib.ccsds122p_segment_first_pass(OWN...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=23...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xil_defaultlib.ccsds122p_encoded_segment_reorde...
Compiling module xil_defaultlib.ccsds122p_backend_farm(LANE_COUN...
Compiling module xil_defaultlib.top_bpe_encoder(BACKEND_LANE_COU...
Compiling module xil_defaultlib.ccsds122_compression_top(AXI_ADD...
Compiling module xil_defaultlib.ccsds122_datamover(MEMORY_BLOCK_...
Compiling module xil_defaultlib.design_1_ccsds122_datamover_0_0
Compiling module xil_defaultlib.uart_rx
Compiling module xil_defaultlib.uart_tx
Compiling module xil_defaultlib.vio_0
Compiling module xil_defaultlib.axi_uart_upload_default
Compiling module xil_defaultlib.ccsds_uart_axi_default
Compiling module xil_defaultlib.design_1_ccsds_uart_axi_0_0
Compiling module unisims_ver.BUFG
Compiling module unisims_ver.MMCME4_ADV(CLKFBOUT_MULT_F=7.0,C...
Compiling module xil_defaultlib.ddr4_v2_2_20_infrastructure(CLKI...
Compiling module unisims_ver.OBUF
Compiling module unisims_ver.IBUFDS(IBUF_LOW_PWR="FALSE")
Compiling module unisims_ver.PLLE4_ADV(CLKFBOUT_MULT=4,CLKFBO...
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_pll(PLL_WIDTH=2,...
Compiling module unisims_ver.HPIO_VREF(VREF_CNTR="FABRIC_RANG...
Compiling module unisims_ver.IOBUFE3_default
Compiling module unisims_ver.IOBUFDS
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_iob_byte(IOBTYPE...
Compiling module unisims_ver.OBUFDS
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_iob_byte(IOBTYPE...
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_iob_byte(IOBTYPE...
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_iob_byte(IOBTYPE...
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_iob(BYTES=6,IOBT...
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_fifo_sv(DEPTH=16...
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_bitslice_behav
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_xiphy_behav(BYTE...
Compiling module xil_defaultlib.design_1_ddr4_0_0_phy_ddr4_defau...
Compiling module xil_defaultlib.design_1_ddr4_0_0_phy
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_group(ABITS=17,A...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_act_rank(tFAW=28...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_act_timer(tFAW=2...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_arb_a
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_wtr(tWTR_L=6,tWT...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_rd_wr(tWTR_L=6,t...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_arb_c_default
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_arb_p
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_cmd_mux_ap(ABITS...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_arb_mux_p(ABITS=...
WARNING: [VRFC 10-3705] select index 2 into 'rank' is out of bounds [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_cal_mc_odt.sv:148]
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_mc_odt(ODTBITS=...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_ctl(ABITS=17,BGB...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_cmd_mux_c
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_ref(LR_WIDTH=1,S...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_periodic
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_ecc(TCQ=0.1,PAYL...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc(ABITS=17,BGBITS=...
Compiling module xil_defaultlib.ddr4_v2_2_20_ui_cmd(TCQ=100.0,AD...
Compiling module unisims_ver.RAM32M
Compiling module xil_defaultlib.ddr4_v2_2_20_ui_wr_data(TCQ=100....
Compiling module xil_defaultlib.ddr4_v2_2_20_ui_rd_data(TCQ=100....
Compiling module xil_defaultlib.ddr4_v2_2_20_ui(TCQ=100.0,ADDR_W...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_debug_microblaz...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_cplx_data_defau...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_cplx(ABITS=17,B...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_addr_decode(DRA...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_config_rom(MEM0...
Compiling module xil_defaultlib.ddr4_v2_2_20_chipscope_xsdb_slav...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_sync(WIDTH=1)
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_sync(WIDTH=16)
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_sync(WIDTH=9)
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_xsdb_arbiter
Compiling module xil_defaultlib.ddr4_v2_2_20_bram_tdp(INIT=2304'...
Compiling module xil_defaultlib.ddr4_v2_2_20_cfg_mem_mod(SIZE=36...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_xsdb_bram(DBYTE...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal(ABITS=17,BGBITS...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_rd_en(RL=32'b01...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_read(RL=32'b010...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_wr_bit
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_wr_byte_default
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_write(WL=32'b01...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_pi(RL=32'b01011...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_top(ABITS=17,BG...
Compiling module unisims_ver.VCC
Compiling module unisims_ver.GND
Compiling module unisims_ver.FDRE_default
Compiling module unisims_ver.FDR
Compiling module unisims_ver.FDSE_default
Compiling module unisims_ver.FDS
Compiling module unisims_ver.FD
Compiling module unisims_ver.FDRE(INIT=1'b1)
Compiling module unisims_ver.FD(INIT=1'b1)
Compiling module unisims_ver.RAM32X1D
Compiling module unisims_ver.FDE
Compiling module unisims_ver.LUT6_2
Compiling module unisims_ver.MUXCY
Compiling module unisims_ver.MUXCY_L
Compiling module unisims_ver.XORCY
Compiling module unisims_ver.x_lut2_mux4
Compiling module unisims_ver.LUT2
Compiling module unisims_ver.MULT_AND
Compiling module unisims_ver.x_lut3_mux8
Compiling module unisims_ver.LUT3
Compiling module unisims_ver.LUT4
Compiling module unisims_ver.LUT6
Compiling module unisims_ver.MUXF5
Compiling module unisims_ver.SRL16E_default
Compiling module unisims_ver.LUT5
Compiling module unisims_ver.FDSE(INIT=1'b0)
Compiling module unisims_ver.x_lut1_mux2
Compiling module unisims_ver.LUT1
Compiling module unisims_ver.MUXF7
Compiling module unisims_ver.INV
Compiling module unisims_ver.RB36_INTERNAL_VLOG(READ_WIDTH_A=...
Compiling module unisims_ver.RAMB36E1(READ_WIDTH_A=2,READ_WID...
Compiling module unisims_ver.RAMB36(READ_WIDTH_A=2,READ_WIDTH...
Compiling module xil_defaultlib.microblaze_mcs
Compiling module xil_defaultlib.design_1_ddr4_0_0_microblaze_mcs
Compiling module xil_defaultlib.design_1_ddr4_0_0_ddr4_cal_riu
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_sync(WIDTH=1,TC...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_sync(WIDTH=32,T...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_sync(WIDTH=20,T...
Compiling module xil_defaultlib.design_1_ddr4_0_0_ddr4_mem_intfc...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_register_slice(...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_register_slice(...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_register_slice(...
Compiling module xil_defaultlib.ddr4_v2_2_20_command_fifo(C_FAMI...
Compiling module xil_defaultlib.ddr4_v2_2_20_a_upsizer(C_AXI_ID_...
Compiling module xil_defaultlib.ddr4_v2_2_20_w_upsizer(C_S_AXI_D...
Compiling module xil_defaultlib.ddr4_v2_2_20_r_upsizer(C_AXI_ID_...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_upsizer(C_AXI_I...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_register_slice(...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_incr_cmd(C_AXI_...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_wrap_cmd(C_AXI_...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_cmd_translator(...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_wr_cmd_fsm
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_aw_channel(C_ID...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_w_channel(C_DAT...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_fifo(C_WIDTH=1,...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_b_channel(C_ID_...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_incr_cmd(C_AXI_...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_wrap_cmd(C_AXI_...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_cmd_translator(...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_cmd_fsm(C_MC_RD...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_ar_channel(C_ID...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_fifo(C_WIDTH=25...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_fifo(C_WIDTH=4,...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_r_channel(C_ID_...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_cmd_arbiter(C_M...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi(C_S_AXI_ID_WIDT...
Compiling module xil_defaultlib.design_1_ddr4_0_0_ddr4_default
Compiling module xil_defaultlib.design_1_ddr4_0_0
Compiling module xil_defaultlib.design_1_ila_0_0
Compiling architecture fdre_v of entity unisim.FDRE [fdre_default]
Compiling architecture fdre_v of entity unisim.FDRE [\FDRE(init='1')\]
Compiling architecture fdr_v of entity unisim.FDR [fdr_default]
Compiling architecture implementation of entity lib_cdc_v1_0_2.cdc_sync [\cdc_sync(c_vector_width=2,c_mtb...]
Compiling architecture srl16e_v of entity unisim.SRL16E [\SRL16E(init="1111111111111111")...]
Compiling architecture srl16_v of entity unisim.SRL16 [\SRL16(init="1111111111111111")(...]
Compiling architecture imp of entity proc_sys_reset_v5_0_14.lpf [\lpf(c_ext_rst_width=4,c_aux_rst...]
Compiling architecture imp of entity proc_sys_reset_v5_0_14.upcnt_n [\upcnt_n(c_size=6)\]
Compiling architecture imp of entity proc_sys_reset_v5_0_14.sequence_psr [sequence_psr_default]
Compiling architecture imp of entity proc_sys_reset_v5_0_14.proc_sys_reset [\proc_sys_reset(c_family="kintex...]
Compiling architecture design_1_proc_sys_reset_0_0_arch of entity xil_defaultlib.design_1_proc_sys_reset_0_0 [design_1_proc_sys_reset_0_0_defa...]
Compiling module xlconstant_v1_1_8.xlconstant_v1_1_8_xlconstant(CON...
Compiling module xil_defaultlib.bd_886d_one_0
Compiling architecture imp of entity proc_sys_reset_v5_0_14.lpf [\lpf(c_ext_rst_width=4,c_aux_rst...]
Compiling architecture imp of entity proc_sys_reset_v5_0_14.proc_sys_reset [\proc_sys_reset(c_family="kintex...]
Compiling architecture bd_886d_psr0_0_arch of entity xil_defaultlib.bd_886d_psr0_0 [bd_886d_psr0_0_default]
Compiling architecture bd_886d_psr_aclk_0_arch of entity xil_defaultlib.bd_886d_psr_aclk_0 [bd_886d_psr_aclk_0_default]
Compiling architecture bd_886d_psr_aclk1_0_arch of entity xil_defaultlib.bd_886d_psr_aclk1_0 [bd_886d_psr_aclk1_0_default]
Compiling module xil_defaultlib.clk_map_imp_1WP46Y0
Compiling module xpm.xpm_cdc_async_rst(DEST_SYNC_FF=3...
Compiling module xil_defaultlib.bd_886d_m00e_0
Compiling module xil_defaultlib.m00_exit_pipeline_imp_4816GJ
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=52...
Compiling module xil_defaultlib.bd_886d_m00arn_0
Compiling module xil_defaultlib.bd_886d_m00awn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=67...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=32...
Compiling module xil_defaultlib.bd_886d_m00bn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=48...
Compiling module xil_defaultlib.bd_886d_m00rn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=4,...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=57...
Compiling module xil_defaultlib.bd_886d_m00wn_0
Compiling module xil_defaultlib.m00_nodes_imp_QDFR33
Compiling module xil_defaultlib.bd_886d_m00s2a_0
Compiling module xil_defaultlib.bd_886d_m01e_0
Compiling module xil_defaultlib.m01_exit_pipeline_imp_6OCSAB
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=32...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=52...
Compiling module xil_defaultlib.bd_886d_m01arn_0
Compiling module xil_defaultlib.bd_886d_m01awn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=67...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=32...
Compiling module xil_defaultlib.bd_886d_m01bn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=48...
Compiling module xil_defaultlib.bd_886d_m01rn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=57...
Compiling module xil_defaultlib.bd_886d_m01wn_0
Compiling module xil_defaultlib.m01_nodes_imp_1HTXBQH
Compiling module xil_defaultlib.bd_886d_m01s2a_0
Compiling module xil_defaultlib.bd_886d_s00a2s_0
Compiling module xil_defaultlib.bd_886d_s00mmu_0
Compiling module xil_defaultlib.bd_886d_s00sic_0
Compiling module xil_defaultlib.bd_886d_s00tr_0
Compiling module xil_defaultlib.s00_entry_pipeline_imp_12V3TGW
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=60...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=46...
Compiling module xil_defaultlib.bd_886d_sarn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=54...
Compiling module xil_defaultlib.bd_886d_srn_0
Compiling module xil_defaultlib.s00_nodes_imp_16MUXNU
Compiling module xil_defaultlib.bd_886d_s01a2s_0
Compiling module xil_defaultlib.bd_886d_s01mmu_0
Compiling module xil_defaultlib.bd_886d_s01sic_0
Compiling module xil_defaultlib.bd_886d_s01tr_0
Compiling module xil_defaultlib.s01_entry_pipeline_imp_6HKV8K
Compiling module xil_defaultlib.bd_886d_sawn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=89...
Compiling module xil_defaultlib.bd_886d_sbn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=51...
Compiling module xil_defaultlib.bd_886d_swn_0
Compiling module xil_defaultlib.s01_nodes_imp_1AH57G
Compiling module xil_defaultlib.bd_886d_s02a2s_0
Compiling module xil_defaultlib.bd_886d_s02mmu_0
Compiling module xil_defaultlib.bd_886d_s02sic_0
Compiling module xil_defaultlib.bd_886d_s02tr_0
Compiling module xil_defaultlib.s02_entry_pipeline_imp_R26R6H
Compiling module xil_defaultlib.bd_886d_sarn_1
Compiling module xil_defaultlib.bd_886d_sawn_1
Compiling module xil_defaultlib.bd_886d_sbn_1
Compiling module xil_defaultlib.bd_886d_srn_1
Compiling module xil_defaultlib.bd_886d_swn_1
Compiling module xil_defaultlib.s02_nodes_imp_XIDFT3
Compiling module xil_defaultlib.bd_886d_s03a2s_0
Compiling module xil_defaultlib.bd_886d_s03mmu_0
Compiling module xil_defaultlib.bd_886d_s03sic_0
Compiling module xil_defaultlib.bd_886d_s03tr_0
Compiling module xil_defaultlib.s03_entry_pipeline_imp_1XMQ8JX
Compiling module xil_defaultlib.bd_886d_sarn_2
Compiling module xil_defaultlib.bd_886d_sawn_2
Compiling module xil_defaultlib.bd_886d_sbn_2
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=54...
Compiling module xil_defaultlib.bd_886d_srn_2
Compiling module xil_defaultlib.bd_886d_swn_2
Compiling module xil_defaultlib.s03_nodes_imp_1RRAM9D
Compiling module xil_defaultlib.bd_886d_arsw_0
Compiling module xil_defaultlib.bd_886d_awsw_0
Compiling module xil_defaultlib.bd_886d_bsw_0
Compiling module xil_defaultlib.bd_886d_rsw_0
Compiling module xil_defaultlib.bd_886d_wsw_0
Compiling module xil_defaultlib.switchboards_imp_1V8ZM66
Compiling module xil_defaultlib.bd_886d
Compiling module xil_defaultlib.design_1_smartconnect_0_1
Compiling module xil_defaultlib.bd_f60c_g_inst_0_gigantic_mux(C_...
Compiling module xil_defaultlib.bd_f60c_g_inst_0
Compiling module xil_defaultlib.bd_f60c_ila_lib_0
Compiling module xlconcat_v2_1_5.xlconcat_v2_1_5_xlconcat_default
Compiling module xil_defaultlib.bd_f60c_slot_0_ar_0
Compiling module xil_defaultlib.bd_f60c_slot_0_aw_0
Compiling module xil_defaultlib.bd_f60c_slot_0_b_0
Compiling module xlconcat_v2_1_5.xlconcat_v2_1_5_xlconcat(dout_wi...
Compiling module xil_defaultlib.bd_f60c_slot_0_r_0
Compiling module xil_defaultlib.bd_f60c_slot_0_w_0
Compiling module xil_defaultlib.bd_f60c_slot_1_ar_0
Compiling module xil_defaultlib.bd_f60c_slot_1_aw_0
Compiling module xil_defaultlib.bd_f60c_slot_1_b_0
Compiling module xil_defaultlib.bd_f60c_slot_1_r_0
Compiling module xil_defaultlib.bd_f60c_slot_1_w_0
Compiling module xil_defaultlib.bd_f60c_slot_2_ar_0
Compiling module xil_defaultlib.bd_f60c_slot_2_aw_0
Compiling module xil_defaultlib.bd_f60c_slot_2_b_0
Compiling module xil_defaultlib.bd_f60c_slot_2_r_0
Compiling module xil_defaultlib.bd_f60c_slot_2_w_0
Compiling module xil_defaultlib.bd_f60c_slot_3_ar_0
Compiling module xil_defaultlib.bd_f60c_slot_3_aw_0
Compiling module xil_defaultlib.bd_f60c_slot_3_b_0
Compiling module xil_defaultlib.bd_f60c_slot_3_r_0
Compiling module xil_defaultlib.bd_f60c_slot_3_w_0
Compiling module xil_defaultlib.bd_f60c
Compiling module xil_defaultlib.design_1_system_ila_0_0
Compiling module util_vector_logic_v2_0_3.util_vector_logic_v2_0_3_util_ve...
Compiling module xil_defaultlib.design_1_util_vector_logic_0_4
Compiling module xil_defaultlib.design_1
Compiling module xil_defaultlib.design_1_wrapper
Compiling module xil_defaultlib.tb_design_1_wrapper
Compiling module xil_defaultlib.glbl
Built simulation snapshot tb_design_1_wrapper_behav
run_program: Time (s): cpu = 00:00:03 ; elapsed = 00:01:05 . Memory (MB): peak = 4020.594 ; gain = 0.000
INFO: [USF-XSim-69] 'elaborate' step finished in '65' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_design_1_wrapper_behav -key {Behavioral:sim_1:Functional:tb_design_1_wrapper} -tclbatch {tb_design_1_wrapper.tcl} -protoinst "protoinst_files/bd_886d.protoinst" -protoinst "protoinst_files/bd_45eb.protoinst" -protoinst "protoinst_files/bd_f60c.protoinst" -protoinst "protoinst_files/design_1.protoinst" -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/bd_886d.protoinst
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m00_exit_pipeline/m00_exit/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m00_exit_pipeline/m00_exit/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m00_exit_pipeline/m_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m00_exit_pipeline/s_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m00_nodes/m00_aw_node/M_AXIS_ARB
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m00_nodes/m00_w_node/S_AXIS_ARB
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m00_sc2axi/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m01_exit_pipeline/m01_exit/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m01_exit_pipeline/m01_exit/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m01_exit_pipeline/m_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m01_exit_pipeline/s_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m01_nodes/m01_aw_node/M_AXIS_ARB
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m01_nodes/m01_w_node/S_AXIS_ARB
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m01_sc2axi/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_axi2sc/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/m_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/s00_mmu/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/s00_mmu/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/s00_si_converter/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/s00_si_converter/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/s00_transaction_regulator/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/s00_transaction_regulator/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/s_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_axi2sc/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/m_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/s01_mmu/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/s01_mmu/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/s01_si_converter/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/s01_si_converter/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/s01_transaction_regulator/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/s01_transaction_regulator/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/s_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_axi2sc/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_entry_pipeline/m_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_entry_pipeline/s02_mmu/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_entry_pipeline/s02_mmu/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_entry_pipeline/s02_si_converter/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_entry_pipeline/s02_si_converter/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_entry_pipeline/s02_transaction_regulator/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_entry_pipeline/s02_transaction_regulator/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_entry_pipeline/s_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_axi2sc/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_entry_pipeline/m_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_entry_pipeline/s03_mmu/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_entry_pipeline/s03_mmu/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_entry_pipeline/s03_si_converter/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_entry_pipeline/s03_si_converter/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_entry_pipeline/s03_transaction_regulator/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_entry_pipeline/s03_transaction_regulator/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_entry_pipeline/s_axi
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/bd_45eb.protoinst
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/bd_45eb.protoinst for the following reason(s):
There are no instances of module "bd_45eb" in the design.
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/bd_f60c.protoinst
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_1.protoinst
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//ccsds122_axil_slave_0/s_axil
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//ccsds122_datamover_0/m_axi_mm2s
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//ccsds122_datamover_0/m_axi_s2mm
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//ccsds_uart_axi_0/m_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//ccsds_uart_axi_0/m_axil
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//ddr4_0/C0_DDR4_S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//smartconnect_0/M00_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//smartconnect_0/M01_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//smartconnect_0/S00_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//smartconnect_0/S01_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//smartconnect_0/S02_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//smartconnect_0/S03_AXI
Time resolution is 1 ps
source tb_design_1_wrapper.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
==== TB: Waiting for DDR4 calib... ====
$finish called at time : 0 fs : File "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/tb_design_1_wrapper.sv" Line 99
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_design_1_wrapper_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:10 ; elapsed = 00:01:15 . Memory (MB): peak = 4020.594 ; gain = 0.000
current_wave_config {Untitled 4}
Untitled 4
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/ccsds_uart_axi_0/inst}}
current_wave_config {Untitled 4}
Untitled 4
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/ccsds_uart_axi_0/inst/u_core}}
restart
INFO: [Wavedata 42-604] Simulation restarted
run 7 ms
==== TB: Waiting for DDR4 calib... ====
$finish called at time : 0 fs : File "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/tb_design_1_wrapper.sv" Line 99
run 7 ms
[TB] DDR4 calib done @ 0 ps
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. tb_design_1_wrapper.u_dut.design_1_i.ccsds122_datamover_0.inst.u_datamover.U0.gen_s2mm_full.I_S2MM_FULL_WRAPPER.gen_enable_indet_btt_sf.I_INDET_BTT.I_XD_FIFO.non_blk_mem.I_SYNC_FIFOGEN_FIFO.xpm_fifo_instance.xpm_fifo_sync_inst.xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/ccsds122_datamover_0/inst/u_datamover/U0/gen_s2mm_full/I_S2MM_FULL_WRAPPER/gen_enable_indet_btt_sf/I_INDET_BTT/I_XD_FIFO/non_blk_mem/I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance/xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial302_83 Scope: tb_design_1_wrapper.u_dut.design_1_i.ccsds122_datamover_0.inst.u_datamover.U0.gen_s2mm_full.I_S2MM_FULL_WRAPPER.gen_enable_indet_btt_sf.I_INDET_BTT.I_XD_FIFO.non_blk_mem.I_SYNC_FIFOGEN_FIFO.xpm_fifo_instance.xpm_fifo_sync_inst.xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 506
Info: [Unisim HPIO_VREF-1] Fabric Tune Value changed to 0011111. Instance: tb_design_1_wrapper.u_dut.design_1_i.ddr4_0.inst.u_ddr4_mem_intfc.u_mig_ddr4_phy.inst.u_ddr_iob.\genByte[0].u_ddr_iob_byte .\genblk1.genVref.u_hpio_vref
Info: [Unisim HPIO_VREF-1] Fabric Tune Value changed to 0011111. Instance: tb_design_1_wrapper.u_dut.design_1_i.ddr4_0.inst.u_ddr4_mem_intfc.u_mig_ddr4_phy.inst.u_ddr_iob.\genByte[3].u_ddr_iob_byte .\genblk1.genVref.u_hpio_vref
Info: [Unisim HPIO_VREF-1] Fabric Tune Value changed to 0011111. Instance: tb_design_1_wrapper.u_dut.design_1_i.ddr4_0.inst.u_ddr4_mem_intfc.u_mig_ddr4_phy.inst.u_ddr_iob.\genByte[4].u_ddr_iob_byte .\genblk1.genVref.u_hpio_vref
Info: [Unisim HPIO_VREF-1] Fabric Tune Value changed to 0011111. Instance: tb_design_1_wrapper.u_dut.design_1_i.ddr4_0.inst.u_ddr4_mem_intfc.u_mig_ddr4_phy.inst.u_ddr_iob.\genByte[5].u_ddr_iob_byte .\genblk1.genVref.u_hpio_vref
[TB] Reset released @ 2498000 ps
[2/6] Config registers
run: Time (s): cpu = 00:00:15 ; elapsed = 00:01:04 . Memory (MB): peak = 4020.594 ; gain = 0.000
current_wave_config {Untitled 4}
Untitled 4
add_wave {{/tb_design_1_wrapper/u_dut}}
current_wave_config {Untitled 4}
Untitled 4
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl}}
current_wave_config {Untitled 4}
Untitled 4
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_bubble_removal}}
current_wave_config {Untitled 4}
Untitled 4
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/ccsds_uart_axi_0}}
current_wave_config {Untitled 4}
Untitled 4
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/ccsds_uart_axi_0/inst/u_core}}
current_wave_config {Untitled 4}
Untitled 4
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/ccsds122_axil_slave_0}}
restart
INFO: [Wavedata 42-604] Simulation restarted
run 7 ms
==== TB: Waiting for DDR4 calib... ====
$finish called at time : 0 fs : File "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/tb_design_1_wrapper.sv" Line 99
run 7 ms
[TB] DDR4 calib done @ 0 ps
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. tb_design_1_wrapper.u_dut.design_1_i.ccsds122_datamover_0.inst.u_datamover.U0.gen_s2mm_full.I_S2MM_FULL_WRAPPER.gen_enable_indet_btt_sf.I_INDET_BTT.I_XD_FIFO.non_blk_mem.I_SYNC_FIFOGEN_FIFO.xpm_fifo_instance.xpm_fifo_sync_inst.xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc
Time: 1 ps Iteration: 0 Process: /tb_design_1_wrapper/u_dut/design_1_i/ccsds122_datamover_0/inst/u_datamover/U0/gen_s2mm_full/I_S2MM_FULL_WRAPPER/gen_enable_indet_btt_sf/I_INDET_BTT/I_XD_FIFO/non_blk_mem/I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance/xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial302_83 Scope: tb_design_1_wrapper.u_dut.design_1_i.ccsds122_datamover_0.inst.u_datamover.U0.gen_s2mm_full.I_S2MM_FULL_WRAPPER.gen_enable_indet_btt_sf.I_INDET_BTT.I_XD_FIFO.non_blk_mem.I_SYNC_FIFOGEN_FIFO.xpm_fifo_instance.xpm_fifo_sync_inst.xpm_fifo_base_inst.\gen_sdpram.xpm_memory_base_inst .config_drc File: C:/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 506
Info: [Unisim HPIO_VREF-1] Fabric Tune Value changed to 0011111. Instance: tb_design_1_wrapper.u_dut.design_1_i.ddr4_0.inst.u_ddr4_mem_intfc.u_mig_ddr4_phy.inst.u_ddr_iob.\genByte[0].u_ddr_iob_byte .\genblk1.genVref.u_hpio_vref
Info: [Unisim HPIO_VREF-1] Fabric Tune Value changed to 0011111. Instance: tb_design_1_wrapper.u_dut.design_1_i.ddr4_0.inst.u_ddr4_mem_intfc.u_mig_ddr4_phy.inst.u_ddr_iob.\genByte[3].u_ddr_iob_byte .\genblk1.genVref.u_hpio_vref
Info: [Unisim HPIO_VREF-1] Fabric Tune Value changed to 0011111. Instance: tb_design_1_wrapper.u_dut.design_1_i.ddr4_0.inst.u_ddr4_mem_intfc.u_mig_ddr4_phy.inst.u_ddr_iob.\genByte[4].u_ddr_iob_byte .\genblk1.genVref.u_hpio_vref
Info: [Unisim HPIO_VREF-1] Fabric Tune Value changed to 0011111. Instance: tb_design_1_wrapper.u_dut.design_1_i.ddr4_0.inst.u_ddr4_mem_intfc.u_mig_ddr4_phy.inst.u_ddr_iob.\genByte[5].u_ddr_iob_byte .\genblk1.genVref.u_hpio_vref
[TB] Reset released @ 2498000 ps
[2/6] Config registers
[3/6] Start compress
[4/6] Poll STATUS
Done: busy=0 done=0
ERROR: done not set
==== 1 errors ====
$finish called at time : 606522500 ps : File "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/tb_design_1_wrapper.sv" Line 134
run: Time (s): cpu = 00:00:41 ; elapsed = 00:02:32 . Memory (MB): peak = 4172.246 ; gain = 151.652
run 7 ms
run: Time (s): cpu = 00:00:38 ; elapsed = 00:01:34 . Memory (MB): peak = 4173.480 ; gain = 1.234
close_sim
INFO: xsimkernel Simulation Memory Usage: 97836 KB (Peak: 97836 KB), Simulation CPU Usage: 304061 ms
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-12493] Simulation top is 'tb_design_1_wrapper'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
Generating merged BMM file for the design top 'tb_design_1_wrapper'...
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2023.2/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2023.2/data/xsim/xsim.ini' copied to run dir:'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim'
INFO: [SIM-utils-50] Design contains embedded sources, generating MEM files for simulation...
Generating merged BMM file for the design top 'tb_design_1_wrapper'...
WARNING: [Memdata 28-361] Design is having concatenated BRAM controllers(heterogenous memory), this configuration is not supported by Updatemem for current device part. Only the first BRAM controller will be added to .MMI and used by Updatemem to update the bitstream with new data.
Generating merged BMM file for the design top 'tb_design_1_wrapper'...
INFO: [SIM-utils-54] Inspecting design source files for 'tb_design_1_wrapper' in fileset 'sim_1'...
INFO: [SIM-utils-43] Exported 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim/sc_xtlm_design_1_smartconnect_0_1.mem'
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim'
"xvlog --incr --relax -L uvm -L axi_vip_v1_1_15 -L smartconnect_v1_0 -L xilinx_vip -prj tb_design_1_wrapper_vlog.prj"
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/tb_design_1_wrapper.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module tb_design_1_wrapper
WARNING: [VRFC 10-3824] variable 'sb' must explicitly be declared as automatic or static [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/tb_design_1_wrapper.sv:185]
ERROR: [VRFC 10-3596] non-static variable 's' cannot be used in initial expression for static variable 'sb' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/tb_design_1_wrapper.sv:185]
ERROR: [VRFC 10-8530] module 'tb_design_1_wrapper' is ignored due to previous errors [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/tb_design_1_wrapper.sv:9]
"xvhdl --incr --relax -prj tb_design_1_wrapper_vhdl.prj"
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-99] Step results log file:'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim/xvlog.log'
ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim/xvlog.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 4173.480 ; gain = 0.000
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-12493] Simulation top is 'tb_design_1_wrapper'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
Generating merged BMM file for the design top 'tb_design_1_wrapper'...
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2023.2/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2023.2/data/xsim/xsim.ini' copied to run dir:'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim'
INFO: [SIM-utils-50] Design contains embedded sources, generating MEM files for simulation...
Generating merged BMM file for the design top 'tb_design_1_wrapper'...
WARNING: [Memdata 28-361] Design is having concatenated BRAM controllers(heterogenous memory), this configuration is not supported by Updatemem for current device part. Only the first BRAM controller will be added to .MMI and used by Updatemem to update the bitstream with new data.
Generating merged BMM file for the design top 'tb_design_1_wrapper'...
INFO: [SIM-utils-54] Inspecting design source files for 'tb_design_1_wrapper' in fileset 'sim_1'...
INFO: [SIM-utils-43] Exported 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim/sc_xtlm_design_1_smartconnect_0_1.mem'
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim'
"xvlog --incr --relax -L uvm -L axi_vip_v1_1_15 -L smartconnect_v1_0 -L xilinx_vip -prj tb_design_1_wrapper_vlog.prj"
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/tb_design_1_wrapper.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module tb_design_1_wrapper
"xvhdl --incr --relax -prj tb_design_1_wrapper_vhdl.prj"
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim'
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L fifo_generator_v13_2_9 -L lib_pkg_v1_0_3 -L lib_fifo_v1_0_18 -L lib_srl_fifo_v1_0_3 -L lib_cdc_v1_0_2 -L axi_datamover_v5_1_31 -L xlconstant_v1_1_8 -L proc_sys_reset_v5_0_14 -L smartconnect_v1_0 -L axi_infrastructure_v1_1_0 -L axi_register_slice_v2_1_29 -L axi_vip_v1_1_15 -L microblaze_v11_0_12 -L lmb_v10_v3_0_13 -L lmb_bram_if_cntlr_v4_0_23 -L blk_mem_gen_v8_4_7 -L iomodule_v3_1_9 -L util_vector_logic_v2_0_3 -L gigantic_mux -L xlconcat_v2_1_5 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_design_1_wrapper_behav xil_defaultlib.tb_design_1_wrapper xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator v2023.2
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2023.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L fifo_generator_v13_2_9 -L lib_pkg_v1_0_3 -L lib_fifo_v1_0_18 -L lib_srl_fifo_v1_0_3 -L lib_cdc_v1_0_2 -L axi_datamover_v5_1_31 -L xlconstant_v1_1_8 -L proc_sys_reset_v5_0_14 -L smartconnect_v1_0 -L axi_infrastructure_v1_1_0 -L axi_register_slice_v2_1_29 -L axi_vip_v1_1_15 -L microblaze_v11_0_12 -L lmb_v10_v3_0_13 -L lmb_bram_if_cntlr_v4_0_23 -L blk_mem_gen_v8_4_7 -L iomodule_v3_1_9 -L util_vector_logic_v2_0_3 -L gigantic_mux -L xlconcat_v2_1_5 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_design_1_wrapper_behav xil_defaultlib.tb_design_1_wrapper xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-8809] cannot index into scalar type parameter/localparam 'DEBUG_MESSAGES' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_cal_xsdb_bram.sv:234]
WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 2 for port 'm_axil_awprot' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/08a1/src/ccsds_uart_axi.sv:190]
WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 2 for port 'm_axil_arprot' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ipshared/08a1/src/ccsds_uart_axi.sv:202]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_awid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2822]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_bid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2837]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_arid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2841]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_rid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2851]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_awid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2866]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_bid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2881]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_arid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2885]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_rid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2895]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_awid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2954]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_3_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2960]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_bid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2969]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_arid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2973]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_3_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2978]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_rid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:2983]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_4_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3004]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_4_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3022]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_5_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3048]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_5_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3066]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_6_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3092]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_6_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3110]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_7_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3136]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_7_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3154]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_8_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3180]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_8_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3198]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_9_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3224]
WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 4 for port 'slot_9_axi_wstrb' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3229]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_9_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3242]
WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 4 for port 'slot_9_axis_tstrb' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3256]
WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 4 for port 'slot_9_axis_tkeep' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3257]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_10_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3268]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_10_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3286]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_11_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3312]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_11_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3330]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_12_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3356]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_12_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3374]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_13_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3400]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_13_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3418]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_14_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3444]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_14_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3462]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_15_axi_awcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3488]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 4 for port 'slot_15_axi_arcache' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:3506]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 4 for port 'sel' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4406]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_awuser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4407]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_wuser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4408]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_buser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4409]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_ruser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4411]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_wuser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4413]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_buser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4414]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_aruser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4415]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_ruser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4416]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_2_axi_awuser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4417]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_2_axi_wuser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4418]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_2_axi_buser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4419]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_2_axi_aruser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4420]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_2_axi_ruser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4421]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_awuser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4422]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_wuser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4423]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_buser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4424]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_aruser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4425]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_ruser' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4426]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_0_axi_wid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4588]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_1_axi_wid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4593]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'slot_3_axi_wid' [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_f60c_g_inst_0.v:4603]
WARNING: [VRFC 10-5021] port 'mb_reset' is not connected on this instance [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/sim/design_1.v:506]
WARNING: [VRFC 10-5021] port 'mb_reset' is not connected on this instance [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/sim/bd_886d.v:2249]
WARNING: [VRFC 10-5021] port 'mb_reset' is not connected on this instance [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/sim/bd_886d.v:2256]
WARNING: [VRFC 10-5021] port 'mb_reset' is not connected on this instance [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/sim/bd_886d.v:2263]
WARNING: [VRFC 10-3705] select index 2 into 'rank' is out of bounds [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_cal_mc_odt.sv:148]
Completed static elaboration
Starting simulation data flow analysis
WARNING: [XSIM 43-4398] File "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_cal_cplx.sv" Line 856 : The System Verilog Assertion will be ignored as it appears inside another process. This assertion is not yet supported.
WARNING: [XSIM 43-4398] File "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_cal_top.sv" Line 1813 : The System Verilog Assertion will be ignored as it appears inside another process. This assertion is not yet supported.
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_unsigned
Compiling package lib_pkg_v1_0_3.lib_pkg
Compiling package xpm.vcomponents
Compiling package synopsys.attributes
Compiling package ieee.std_logic_misc
Compiling package unisim.vcomponents
Compiling package ieee.vital_timing
Compiling package ieee.vital_primitives
Compiling package unisim.vpkg
Compiling package xpm.$unit_xpm_cdc_sv_220102727
Compiling package xpm.axi_xil_sb_pkg_xpm_nsu
Compiling package xpm.axi_data_integrity_checker_xpm_n...
Compiling package xpm.xpm_axi_data_integrity_checker_n...
Compiling package xpm.xpm_axi_xil_sb_pkg_nmu
Compiling package xil_defaultlib.ccsds122p_pkg
Compiling package smartconnect_v1_0.sc_util_v1_0_4_pkg
Compiling module xil_defaultlib.ccsds122_axil_slave
Compiling module xil_defaultlib.design_1_ccsds122_axil_slave_0_0
Compiling module xpm.xpm_fifo_rst_default
Compiling module xpm.xpm_fifo_reg_bit
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=8...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=7...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=2...
Compiling module xpm.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
Compiling module xpm.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling architecture implementation of entity lib_fifo_v1_0_18.sync_fifo_fg [\sync_fifo_fg(c_family="kintexup...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_sfifo_autord [\axi_datamover_sfifo_autord(c_dw...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_rd_sf [\axi_datamover_rd_sf(c_sf_fifo_d...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_skid_buf [\axi_datamover_skid_buf(c_wdata_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_reset [axi_datamover_reset_default]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=4,c_dwidth=8...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=8,c_dep...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=8,c_depth=4...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=8,c...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.cntr_incr_decr_addn_f [\cntr_incr_decr_addn_f(c_size=3,...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=4,c_dwidth=6...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=68,c_de...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=68,c_depth=...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=68,...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_cmd_status [\axi_datamover_cmd_status(c_fami...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_rd_status_cntl [axi_datamover_rd_status_cntl_def...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_strb_gen2 [\axi_datamover_strb_gen2(c_strb_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_strb_gen2 [\axi_datamover_strb_gen2(c_op_mo...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_pcc [\axi_datamover_pcc(c_is_mm2s=1,c...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=3,c_dwidth=5...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=59,c_de...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=59,c_depth=...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=59,...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_addr_cntl [\axi_datamover_addr_cntl(c_addr_...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=3,c_dwidth=5...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=55,c_de...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=55,c_depth=...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=55,...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_rdmux [\axi_datamover_rdmux(c_sel_addr_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_rddata_cntl [\axi_datamover_rddata_cntl(c_ali...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_mm2s_full_wrap [\axi_datamover_mm2s_full_wrap(c_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_ibttcc [\axi_datamover_ibttcc(c_sf_xfer_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_dre_mux2_1_x_n [\axi_datamover_dre_mux2_1_x_n(c_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_dre_mux4_1_x_n [\axi_datamover_dre_mux4_1_x_n(c_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_dre_mux8_1_x_n [\axi_datamover_dre_mux8_1_x_n(c_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_s2mm_dre [axi_datamover_s2mm_dre_default]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_ms_strb_set [axi_datamover_ms_strb_set_defaul...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_mssai_skid_buf [\axi_datamover_mssai_skid_buf(c_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_strb_gen2 [axi_datamover_strb_gen2_default]
Compiling architecture working of entity axi_datamover_v5_1_31.axi_datamover_slice [\axi_datamover_slice(c_data_widt...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.cntr_incr_decr_addn_f [\cntr_incr_decr_addn_f(c_size=5,...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=16,c_dwidth=...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=14,c_fa...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=14,c_family...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=14,...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_s2mm_scatter [\axi_datamover_s2mm_scatter(c_en...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=4,c_dwidth=3...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=38,c_de...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=38,c_depth=...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=38,...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_s2mm_realign [\axi_datamover_s2mm_realign(c_en...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_stbs_set [axi_datamover_stbs_set_default]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_stbs_set [\axi_datamover_stbs_set(c_strobe...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_skid_buf [\axi_datamover_skid_buf(c_wdata_...]
Compiling module xpm.xpm_fifo_rst_default_1
Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=5...
Compiling module xpm.xpm_counter_updn
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=1...
Compiling module xpm.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling architecture implementation of entity lib_fifo_v1_0_18.sync_fifo_fg [\sync_fifo_fg(c_family="kintexup...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_sfifo_autord [\axi_datamover_sfifo_autord(c_dw...]
Compiling module xpm.xpm_fifo_rst_default_2
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
Compiling module xpm.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
Compiling architecture implementation of entity lib_fifo_v1_0_18.sync_fifo_fg [\sync_fifo_fg(c_family="kintexup...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_sfifo_autord [\axi_datamover_sfifo_autord(c_dw...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_indet_btt [\axi_datamover_indet_btt(c_ibtt_...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=4,c_dwidth=3...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=32,c_de...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=32,c_depth=...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_family="ki...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_cmd_status [\axi_datamover_cmd_status(c_sts_...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=6,c_dwidth=3...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=30,c_de...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=30,c_depth=...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=30,...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.cntr_incr_decr_addn_f [\cntr_incr_decr_addn_f(c_size=4,...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=6,c_dwidth=2...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=2,c_dep...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=2,c_depth=6...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=2,c...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_wr_status_cntl [\axi_datamover_wr_status_cntl(c_...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=4,c_dwidth=5...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=59,c_de...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=59,c_depth=...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=59,...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_addr_cntl [\axi_datamover_addr_cntl(c_addr_...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_3.dynshreg_f [\dynshreg_f(c_depth=4,c_dwidth=5...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=53,c_de...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_3.srl_fifo_f [\srl_fifo_f(c_dwidth=53,c_depth=...]
Compiling architecture imp of entity axi_datamover_v5_1_31.axi_datamover_fifo [\axi_datamover_fifo(c_dwidth=53,...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_wrdata_cntl [\axi_datamover_wrdata_cntl(c_rea...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_wr_demux [\axi_datamover_wr_demux(c_sel_ad...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_skid2mm_buf [\axi_datamover_skid2mm_buf(c_mda...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover_s2mm_full_wrap [\axi_datamover_s2mm_full_wrap(c_...]
Compiling architecture implementation of entity axi_datamover_v5_1_31.axi_datamover [\axi_datamover(c_include_mm2s=1,...]
Compiling architecture axi_datamover_0_arch of entity xil_defaultlib.axi_datamover_0 [axi_datamover_0_default]
Compiling module xil_defaultlib.ccsds122_addr_calc(AXI_ADDR_W=32...
Compiling module xil_defaultlib.ila_1
Compiling module xil_defaultlib.ccsds122_stream_ctrl(AXI_ADDR_W=...
Compiling module fifo_generator_v13_2_9.fifo_generator_v13_2_9_bhv_ver_s...
Compiling module fifo_generator_v13_2_9.fifo_generator_v13_2_9_bhv_ver_p...
Compiling module fifo_generator_v13_2_9.fifo_generator_v13_2_9_CONV_VER(...
Compiling module fifo_generator_v13_2_9.fifo_generator_vlog_beh(C_COMMON...
Compiling module xil_defaultlib.fifo_generator_0
Compiling module xil_defaultlib.ccsds122_bubble_removal_ctrl(AXI...
Compiling module xil_defaultlib.ccsds122p_ingress_frontend_defau...
Compiling module xil_defaultlib.ccsds122p_dwt_m97_lift_core(COEF...
Compiling module xil_defaultlib.ccsds122p_dwt_h_stage(ROW_SAMPLE...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=61...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xil_defaultlib.ccsds122p_dwt_v_stage(STAGE_SAMP...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=30...
Compiling module xil_defaultlib.ccsds122p_dwt_ll_row_order(STAGE...
Compiling module xil_defaultlib.ccsds122p_dwt_split_stage(STAGE_...
Compiling module xil_defaultlib.ccsds122p_dwt_l0(ENABLE_PROTOCOL...
Compiling module xil_defaultlib.ccsds122p_dwt_h_stage(ROW_SAMPLE...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=30...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xil_defaultlib.ccsds122p_dwt_v_stage(STAGE_SAMP...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=15...
Compiling module xil_defaultlib.ccsds122p_dwt_ll_row_order(STAGE...
Compiling module xil_defaultlib.ccsds122p_dwt_split_stage(STAGE_...
Compiling module xil_defaultlib.ccsds122p_dwt_l1(ENABLE_PROTOCOL...
Compiling module xil_defaultlib.ccsds122p_dwt_h_stage(ROW_SAMPLE...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=15...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xil_defaultlib.ccsds122p_dwt_v_stage(STAGE_SAMP...
Compiling module xil_defaultlib.ccsds122p_dwt_l2(ENABLE_PROTOCOL...
Compiling module xil_defaultlib.ccsds122p_dwt_merge(ENABLE_PROTO...
Compiling module xil_defaultlib.ccsds122p_subband_router(ENABLE_...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=15...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram_masked(DATA...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=81...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xil_defaultlib.ccsds122p_segment_reorder(ENABLE...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=24...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xil_defaultlib.ccsds122p_segment_bank
Compiling module xil_defaultlib.ccsds122p_segment_fill(ENABLE_PR...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=25...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xil_defaultlib.ccsds122p_block_state_ram(DATA_W...
Compiling module xil_defaultlib.ccsds122p_segment_state_bank
Compiling module xil_defaultlib.ccsds122p_dc_option_select
Compiling module xil_defaultlib.ccsds122p_dc_code_emitter
Compiling module xil_defaultlib.ccsds122p_dc_entropy_encoder
Compiling module xil_defaultlib.ccsds122p_ac_depth_option_select...
Compiling module xil_defaultlib.ccsds122p_ac_depth_code_emitter_...
Compiling module xil_defaultlib.ccsds122p_ac_depth_encoder_defau...
Compiling module xil_defaultlib.ccsds122p_ac_stage0_dc_emit
Compiling module xil_defaultlib.ccsds122p_segment_block_reader
Compiling module xil_defaultlib.ccsds122p_stage_block_scan(FIXED...
Compiling module xil_defaultlib.ccsds122p_stage_pattern_map
Compiling module xil_defaultlib.ccsds122p_stage_option_select(US...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=15...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=14...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=51...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=33...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xil_defaultlib.ccsds122p_stage_rice_emitter
Compiling module xil_defaultlib.ccsds122p_stage_symbol_emit
Compiling module xil_defaultlib.ccsds122p_stage_refine_emit
Compiling module xil_defaultlib.ccsds122p_ac_bitplane_cached_com...
Compiling module xil_defaultlib.ccsds122p_ac_bitplane_gaggle_enc...
Compiling module xil_defaultlib.ccsds122p_segment_encoder_core
Compiling module xil_defaultlib.ccsds122p_bitstream_packer(ENABL...
Compiling module xil_defaultlib.ccsds122p_backend_lane(ENABLE_PR...
Compiling module xil_defaultlib.ccsds122p_bit_length24(BITS_W=32...
Compiling module xil_defaultlib.ccsds122p_segment_bitdepth
Compiling module xil_defaultlib.ccsds122p_header_writer_default
Compiling module xil_defaultlib.ccsds122p_segment_stats
Compiling module xil_defaultlib.ccsds122p_dc_seed
Compiling module xil_defaultlib.ccsds122p_block_state_pack_defau...
Compiling module xil_defaultlib.ccsds122p_segment_first_pass(OWN...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=23...
Compiling module xil_defaultlib.ccsds122p_xpm_sdpram(DATA_W=32'b...
Compiling module xil_defaultlib.ccsds122p_encoded_segment_reorde...
Compiling module xil_defaultlib.ccsds122p_backend_farm(LANE_COUN...
Compiling module xil_defaultlib.top_bpe_encoder(BACKEND_LANE_COU...
Compiling module xil_defaultlib.ccsds122_compression_top(AXI_ADD...
Compiling module xil_defaultlib.ccsds122_datamover(MEMORY_BLOCK_...
Compiling module xil_defaultlib.design_1_ccsds122_datamover_0_0
Compiling module xil_defaultlib.uart_rx
Compiling module xil_defaultlib.uart_tx
Compiling module xil_defaultlib.vio_0
Compiling module xil_defaultlib.axi_uart_upload_default
Compiling module xil_defaultlib.ccsds_uart_axi_default
Compiling module xil_defaultlib.design_1_ccsds_uart_axi_0_0
Compiling module unisims_ver.BUFG
Compiling module unisims_ver.MMCME4_ADV(CLKFBOUT_MULT_F=7.0,C...
Compiling module xil_defaultlib.ddr4_v2_2_20_infrastructure(CLKI...
Compiling module unisims_ver.OBUF
Compiling module unisims_ver.IBUFDS(IBUF_LOW_PWR="FALSE")
Compiling module unisims_ver.PLLE4_ADV(CLKFBOUT_MULT=4,CLKFBO...
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_pll(PLL_WIDTH=2,...
Compiling module unisims_ver.HPIO_VREF(VREF_CNTR="FABRIC_RANG...
Compiling module unisims_ver.IOBUFE3_default
Compiling module unisims_ver.IOBUFDS
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_iob_byte(IOBTYPE...
Compiling module unisims_ver.OBUFDS
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_iob_byte(IOBTYPE...
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_iob_byte(IOBTYPE...
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_iob_byte(IOBTYPE...
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_iob(BYTES=6,IOBT...
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_fifo_sv(DEPTH=16...
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_bitslice_behav
Compiling module xil_defaultlib.ddr4_phy_v2_2_1_xiphy_behav(BYTE...
Compiling module xil_defaultlib.design_1_ddr4_0_0_phy_ddr4_defau...
Compiling module xil_defaultlib.design_1_ddr4_0_0_phy
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_group(ABITS=17,A...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_act_rank(tFAW=28...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_act_timer(tFAW=2...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_arb_a
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_wtr(tWTR_L=6,tWT...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_rd_wr(tWTR_L=6,t...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_arb_c_default
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_arb_p
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_cmd_mux_ap(ABITS...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_arb_mux_p(ABITS=...
WARNING: [VRFC 10-3705] select index 2 into 'rank' is out of bounds [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/bd/design_1/ip/design_1_ddr4_0_0/rtl/cal/ddr4_v2_2_cal_mc_odt.sv:148]
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_mc_odt(ODTBITS=...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_ctl(ABITS=17,BGB...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_cmd_mux_c
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_ref(LR_WIDTH=1,S...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_periodic
Compiling module xil_defaultlib.ddr4_v2_2_20_mc_ecc(TCQ=0.1,PAYL...
Compiling module xil_defaultlib.ddr4_v2_2_20_mc(ABITS=17,BGBITS=...
Compiling module xil_defaultlib.ddr4_v2_2_20_ui_cmd(TCQ=100.0,AD...
Compiling module unisims_ver.RAM32M
Compiling module xil_defaultlib.ddr4_v2_2_20_ui_wr_data(TCQ=100....
Compiling module xil_defaultlib.ddr4_v2_2_20_ui_rd_data(TCQ=100....
Compiling module xil_defaultlib.ddr4_v2_2_20_ui(TCQ=100.0,ADDR_W...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_debug_microblaz...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_cplx_data_defau...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_cplx(ABITS=17,B...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_addr_decode(DRA...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_config_rom(MEM0...
Compiling module xil_defaultlib.ddr4_v2_2_20_chipscope_xsdb_slav...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_sync(WIDTH=1)
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_sync(WIDTH=16)
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_sync(WIDTH=9)
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_xsdb_arbiter
Compiling module xil_defaultlib.ddr4_v2_2_20_bram_tdp(INIT=2304'...
Compiling module xil_defaultlib.ddr4_v2_2_20_cfg_mem_mod(SIZE=36...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_xsdb_bram(DBYTE...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal(ABITS=17,BGBITS...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_rd_en(RL=32'b01...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_read(RL=32'b010...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_wr_bit
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_wr_byte_default
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_write(WL=32'b01...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_pi(RL=32'b01011...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_top(ABITS=17,BG...
Compiling module unisims_ver.VCC
Compiling module unisims_ver.GND
Compiling module unisims_ver.FDRE_default
Compiling module unisims_ver.FDR
Compiling module unisims_ver.FDSE_default
Compiling module unisims_ver.FDS
Compiling module unisims_ver.FD
Compiling module unisims_ver.FDRE(INIT=1'b1)
Compiling module unisims_ver.FD(INIT=1'b1)
Compiling module unisims_ver.RAM32X1D
Compiling module unisims_ver.FDE
Compiling module unisims_ver.LUT6_2
Compiling module unisims_ver.MUXCY
Compiling module unisims_ver.MUXCY_L
Compiling module unisims_ver.XORCY
Compiling module unisims_ver.x_lut2_mux4
Compiling module unisims_ver.LUT2
Compiling module unisims_ver.MULT_AND
Compiling module unisims_ver.x_lut3_mux8
Compiling module unisims_ver.LUT3
Compiling module unisims_ver.LUT4
Compiling module unisims_ver.LUT6
Compiling module unisims_ver.MUXF5
Compiling module unisims_ver.SRL16E_default
Compiling module unisims_ver.LUT5
Compiling module unisims_ver.FDSE(INIT=1'b0)
Compiling module unisims_ver.x_lut1_mux2
Compiling module unisims_ver.LUT1
Compiling module unisims_ver.MUXF7
Compiling module unisims_ver.INV
Compiling module unisims_ver.RB36_INTERNAL_VLOG(READ_WIDTH_A=...
Compiling module unisims_ver.RAMB36E1(READ_WIDTH_A=2,READ_WID...
Compiling module unisims_ver.RAMB36(READ_WIDTH_A=2,READ_WIDTH...
Compiling module xil_defaultlib.microblaze_mcs
Compiling module xil_defaultlib.design_1_ddr4_0_0_microblaze_mcs
Compiling module xil_defaultlib.design_1_ddr4_0_0_ddr4_cal_riu
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_sync(WIDTH=1,TC...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_sync(WIDTH=32,T...
Compiling module xil_defaultlib.ddr4_v2_2_20_cal_sync(WIDTH=20,T...
Compiling module xil_defaultlib.design_1_ddr4_0_0_ddr4_mem_intfc...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_register_slice(...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_register_slice(...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_register_slice(...
Compiling module xil_defaultlib.ddr4_v2_2_20_command_fifo(C_FAMI...
Compiling module xil_defaultlib.ddr4_v2_2_20_a_upsizer(C_AXI_ID_...
Compiling module xil_defaultlib.ddr4_v2_2_20_w_upsizer(C_S_AXI_D...
Compiling module xil_defaultlib.ddr4_v2_2_20_r_upsizer(C_AXI_ID_...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_upsizer(C_AXI_I...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axic_register_slice...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_register_slice(...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_incr_cmd(C_AXI_...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_wrap_cmd(C_AXI_...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_cmd_translator(...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_wr_cmd_fsm
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_aw_channel(C_ID...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_w_channel(C_DAT...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_fifo(C_WIDTH=1,...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_b_channel(C_ID_...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_incr_cmd(C_AXI_...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_wrap_cmd(C_AXI_...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_cmd_translator(...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_cmd_fsm(C_MC_RD...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_ar_channel(C_ID...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_fifo(C_WIDTH=25...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_fifo(C_WIDTH=4,...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_r_channel(C_ID_...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi_cmd_arbiter(C_M...
Compiling module xil_defaultlib.ddr4_v2_2_20_axi(C_S_AXI_ID_WIDT...
Compiling module xil_defaultlib.design_1_ddr4_0_0_ddr4_default
Compiling module xil_defaultlib.design_1_ddr4_0_0
Compiling module xil_defaultlib.design_1_ila_0_0
Compiling architecture fdre_v of entity unisim.FDRE [fdre_default]
Compiling architecture fdre_v of entity unisim.FDRE [\FDRE(init='1')\]
Compiling architecture fdr_v of entity unisim.FDR [fdr_default]
Compiling architecture implementation of entity lib_cdc_v1_0_2.cdc_sync [\cdc_sync(c_vector_width=2,c_mtb...]
Compiling architecture srl16e_v of entity unisim.SRL16E [\SRL16E(init="1111111111111111")...]
Compiling architecture srl16_v of entity unisim.SRL16 [\SRL16(init="1111111111111111")(...]
Compiling architecture imp of entity proc_sys_reset_v5_0_14.lpf [\lpf(c_ext_rst_width=4,c_aux_rst...]
Compiling architecture imp of entity proc_sys_reset_v5_0_14.upcnt_n [\upcnt_n(c_size=6)\]
Compiling architecture imp of entity proc_sys_reset_v5_0_14.sequence_psr [sequence_psr_default]
Compiling architecture imp of entity proc_sys_reset_v5_0_14.proc_sys_reset [\proc_sys_reset(c_family="kintex...]
Compiling architecture design_1_proc_sys_reset_0_0_arch of entity xil_defaultlib.design_1_proc_sys_reset_0_0 [design_1_proc_sys_reset_0_0_defa...]
Compiling module xlconstant_v1_1_8.xlconstant_v1_1_8_xlconstant(CON...
Compiling module xil_defaultlib.bd_886d_one_0
Compiling architecture imp of entity proc_sys_reset_v5_0_14.lpf [\lpf(c_ext_rst_width=4,c_aux_rst...]
Compiling architecture imp of entity proc_sys_reset_v5_0_14.proc_sys_reset [\proc_sys_reset(c_family="kintex...]
Compiling architecture bd_886d_psr0_0_arch of entity xil_defaultlib.bd_886d_psr0_0 [bd_886d_psr0_0_default]
Compiling architecture bd_886d_psr_aclk_0_arch of entity xil_defaultlib.bd_886d_psr_aclk_0 [bd_886d_psr_aclk_0_default]
Compiling architecture bd_886d_psr_aclk1_0_arch of entity xil_defaultlib.bd_886d_psr_aclk1_0 [bd_886d_psr_aclk1_0_default]
Compiling module xil_defaultlib.clk_map_imp_1WP46Y0
Compiling module xpm.xpm_cdc_async_rst(DEST_SYNC_FF=3...
Compiling module xil_defaultlib.bd_886d_m00e_0
Compiling module xil_defaultlib.m00_exit_pipeline_imp_4816GJ
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=52...
Compiling module xil_defaultlib.bd_886d_m00arn_0
Compiling module xil_defaultlib.bd_886d_m00awn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=67...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=32...
Compiling module xil_defaultlib.bd_886d_m00bn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=48...
Compiling module xil_defaultlib.bd_886d_m00rn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=4,...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=57...
Compiling module xil_defaultlib.bd_886d_m00wn_0
Compiling module xil_defaultlib.m00_nodes_imp_QDFR33
Compiling module xil_defaultlib.bd_886d_m00s2a_0
Compiling module xil_defaultlib.bd_886d_m01e_0
Compiling module xil_defaultlib.m01_exit_pipeline_imp_6OCSAB
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=32...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=52...
Compiling module xil_defaultlib.bd_886d_m01arn_0
Compiling module xil_defaultlib.bd_886d_m01awn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=67...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=32...
Compiling module xil_defaultlib.bd_886d_m01bn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=48...
Compiling module xil_defaultlib.bd_886d_m01rn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=57...
Compiling module xil_defaultlib.bd_886d_m01wn_0
Compiling module xil_defaultlib.m01_nodes_imp_1HTXBQH
Compiling module xil_defaultlib.bd_886d_m01s2a_0
Compiling module xil_defaultlib.bd_886d_s00a2s_0
Compiling module xil_defaultlib.bd_886d_s00mmu_0
Compiling module xil_defaultlib.bd_886d_s00sic_0
Compiling module xil_defaultlib.bd_886d_s00tr_0
Compiling module xil_defaultlib.s00_entry_pipeline_imp_12V3TGW
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=60...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=46...
Compiling module xil_defaultlib.bd_886d_sarn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=54...
Compiling module xil_defaultlib.bd_886d_srn_0
Compiling module xil_defaultlib.s00_nodes_imp_16MUXNU
Compiling module xil_defaultlib.bd_886d_s01a2s_0
Compiling module xil_defaultlib.bd_886d_s01mmu_0
Compiling module xil_defaultlib.bd_886d_s01sic_0
Compiling module xil_defaultlib.bd_886d_s01tr_0
Compiling module xil_defaultlib.s01_entry_pipeline_imp_6HKV8K
Compiling module xil_defaultlib.bd_886d_sawn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=89...
Compiling module xil_defaultlib.bd_886d_sbn_0
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=51...
Compiling module xil_defaultlib.bd_886d_swn_0
Compiling module xil_defaultlib.s01_nodes_imp_1AH57G
Compiling module xil_defaultlib.bd_886d_s02a2s_0
Compiling module xil_defaultlib.bd_886d_s02mmu_0
Compiling module xil_defaultlib.bd_886d_s02sic_0
Compiling module xil_defaultlib.bd_886d_s02tr_0
Compiling module xil_defaultlib.s02_entry_pipeline_imp_R26R6H
Compiling module xil_defaultlib.bd_886d_sarn_1
Compiling module xil_defaultlib.bd_886d_sawn_1
Compiling module xil_defaultlib.bd_886d_sbn_1
Compiling module xil_defaultlib.bd_886d_srn_1
Compiling module xil_defaultlib.bd_886d_swn_1
Compiling module xil_defaultlib.s02_nodes_imp_XIDFT3
Compiling module xil_defaultlib.bd_886d_s03a2s_0
Compiling module xil_defaultlib.bd_886d_s03mmu_0
Compiling module xil_defaultlib.bd_886d_s03sic_0
Compiling module xil_defaultlib.bd_886d_s03tr_0
Compiling module xil_defaultlib.s03_entry_pipeline_imp_1XMQ8JX
Compiling module xil_defaultlib.bd_886d_sarn_2
Compiling module xil_defaultlib.bd_886d_sawn_2
Compiling module xil_defaultlib.bd_886d_sbn_2
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=54...
Compiling module xil_defaultlib.bd_886d_srn_2
Compiling module xil_defaultlib.bd_886d_swn_2
Compiling module xil_defaultlib.s03_nodes_imp_1RRAM9D
Compiling module xil_defaultlib.bd_886d_arsw_0
Compiling module xil_defaultlib.bd_886d_awsw_0
Compiling module xil_defaultlib.bd_886d_bsw_0
Compiling module xil_defaultlib.bd_886d_rsw_0
Compiling module xil_defaultlib.bd_886d_wsw_0
Compiling module xil_defaultlib.switchboards_imp_1V8ZM66
Compiling module xil_defaultlib.bd_886d
Compiling module xil_defaultlib.design_1_smartconnect_0_1
Compiling module xil_defaultlib.bd_f60c_g_inst_0_gigantic_mux(C_...
Compiling module xil_defaultlib.bd_f60c_g_inst_0
Compiling module xil_defaultlib.bd_f60c_ila_lib_0
Compiling module xlconcat_v2_1_5.xlconcat_v2_1_5_xlconcat_default
Compiling module xil_defaultlib.bd_f60c_slot_0_ar_0
Compiling module xil_defaultlib.bd_f60c_slot_0_aw_0
Compiling module xil_defaultlib.bd_f60c_slot_0_b_0
Compiling module xlconcat_v2_1_5.xlconcat_v2_1_5_xlconcat(dout_wi...
Compiling module xil_defaultlib.bd_f60c_slot_0_r_0
Compiling module xil_defaultlib.bd_f60c_slot_0_w_0
Compiling module xil_defaultlib.bd_f60c_slot_1_ar_0
Compiling module xil_defaultlib.bd_f60c_slot_1_aw_0
Compiling module xil_defaultlib.bd_f60c_slot_1_b_0
Compiling module xil_defaultlib.bd_f60c_slot_1_r_0
Compiling module xil_defaultlib.bd_f60c_slot_1_w_0
Compiling module xil_defaultlib.bd_f60c_slot_2_ar_0
Compiling module xil_defaultlib.bd_f60c_slot_2_aw_0
Compiling module xil_defaultlib.bd_f60c_slot_2_b_0
Compiling module xil_defaultlib.bd_f60c_slot_2_r_0
Compiling module xil_defaultlib.bd_f60c_slot_2_w_0
Compiling module xil_defaultlib.bd_f60c_slot_3_ar_0
Compiling module xil_defaultlib.bd_f60c_slot_3_aw_0
Compiling module xil_defaultlib.bd_f60c_slot_3_b_0
Compiling module xil_defaultlib.bd_f60c_slot_3_r_0
Compiling module xil_defaultlib.bd_f60c_slot_3_w_0
Compiling module xil_defaultlib.bd_f60c
Compiling module xil_defaultlib.design_1_system_ila_0_0
Compiling module util_vector_logic_v2_0_3.util_vector_logic_v2_0_3_util_ve...
Compiling module xil_defaultlib.design_1_util_vector_logic_0_4
Compiling module xil_defaultlib.design_1
Compiling module xil_defaultlib.design_1_wrapper
Compiling module xil_defaultlib.tb_design_1_wrapper
Compiling module xil_defaultlib.glbl
Built simulation snapshot tb_design_1_wrapper_behav
run_program: Time (s): cpu = 00:00:03 ; elapsed = 00:01:07 . Memory (MB): peak = 4173.480 ; gain = 0.000
INFO: [USF-XSim-69] 'elaborate' step finished in '67' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_design_1_wrapper_behav -key {Behavioral:sim_1:Functional:tb_design_1_wrapper} -tclbatch {tb_design_1_wrapper.tcl} -protoinst "protoinst_files/bd_886d.protoinst" -protoinst "protoinst_files/bd_45eb.protoinst" -protoinst "protoinst_files/bd_f60c.protoinst" -protoinst "protoinst_files/design_1.protoinst" -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/bd_886d.protoinst
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m00_exit_pipeline/m00_exit/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m00_exit_pipeline/m00_exit/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m00_exit_pipeline/m_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m00_exit_pipeline/s_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m00_nodes/m00_aw_node/M_AXIS_ARB
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m00_nodes/m00_w_node/S_AXIS_ARB
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m00_sc2axi/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m01_exit_pipeline/m01_exit/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m01_exit_pipeline/m01_exit/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m01_exit_pipeline/m_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m01_exit_pipeline/s_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m01_nodes/m01_aw_node/M_AXIS_ARB
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m01_nodes/m01_w_node/S_AXIS_ARB
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//m01_sc2axi/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_axi2sc/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/m_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/s00_mmu/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/s00_mmu/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/s00_si_converter/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/s00_si_converter/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/s00_transaction_regulator/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/s00_transaction_regulator/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s00_entry_pipeline/s_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_axi2sc/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/m_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/s01_mmu/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/s01_mmu/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/s01_si_converter/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/s01_si_converter/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/s01_transaction_regulator/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/s01_transaction_regulator/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s01_entry_pipeline/s_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_axi2sc/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_entry_pipeline/m_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_entry_pipeline/s02_mmu/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_entry_pipeline/s02_mmu/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_entry_pipeline/s02_si_converter/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_entry_pipeline/s02_si_converter/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_entry_pipeline/s02_transaction_regulator/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_entry_pipeline/s02_transaction_regulator/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s02_entry_pipeline/s_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_axi2sc/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_entry_pipeline/m_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_entry_pipeline/s03_mmu/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_entry_pipeline/s03_mmu/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_entry_pipeline/s03_si_converter/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_entry_pipeline/s03_si_converter/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_entry_pipeline/s03_transaction_regulator/M_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_entry_pipeline/s03_transaction_regulator/S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0/inst//s03_entry_pipeline/s_axi
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/bd_45eb.protoinst
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/bd_45eb.protoinst for the following reason(s):
There are no instances of module "bd_45eb" in the design.
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/bd_f60c.protoinst
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_1.protoinst
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//ccsds122_axil_slave_0/s_axil
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//ccsds122_datamover_0/m_axi_mm2s
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//ccsds122_datamover_0/m_axi_s2mm
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//ccsds_uart_axi_0/m_axi
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//ccsds_uart_axi_0/m_axil
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//ddr4_0/C0_DDR4_S_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//smartconnect_0/M00_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//smartconnect_0/M01_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//smartconnect_0/S00_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//smartconnect_0/S01_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//smartconnect_0/S02_AXI
INFO: [Wavedata 42-564] Found protocol instance at /tb_design_1_wrapper/u_dut/design_1_i//smartconnect_0/S03_AXI
Time resolution is 1 ps
source tb_design_1_wrapper.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
WARNING: Simulation object /tb_design_1_wrapper/ddr_img was not traceable in the design for the following reason:
Vivado Simulator does not support tracing of System Verilog Dynamic Type object.
# run 1000ns
==== TB Full-System (MIG, Mode 1, Block 128MB) ====
[TB] Build DDR: aux_rows=256, 5 bands
[TB] Metadata @ 0x07fff000: mode=1, rows=256
DDR image: 134217728 bytes (128 MB)
Waiting for DDR4 calibration...
$finish called at time : 0 fs : File "C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/tb_design_1_wrapper.sv" Line 213
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