74 lines
2.1 KiB
Plaintext
74 lines
2.1 KiB
Plaintext
-------------------------------------
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| Tool Version : Vivado v.2023.2
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| Date : Wed Jul 8 18:43:07 2026
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| Host : DESKTOP-EB3SDQ2
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| Design : design_1
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| Device : xcku5p-ffvb676-2-I-
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-------------------------------------
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For more information on clockInfo.txt clock routing debug file see https://support.xilinx.com/s/article/000035660?language=en_US
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***********************
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Running Pre-CRP Checker
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***********************
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Number of global clocks: 7
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Number of BUFGCE: 7
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Number of BUFGCE_HDIO: 0
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Number of BUFG_CTRL: 0
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Number of BUFGCE_DIV: 0
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Number of BUFG_GT: 0
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Number of BUFG_PS: 0
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Number of BUFG_FABRIC: 0
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Running suboptimal placement checker for 3 clocks (and their loads) which do not have the CLOCK_LOW_FANOUT property but have a fanout less than 2000...
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No sub-optimality found
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Pre-CRP Checker took 0 secs
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********************************
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Clock Net Route Info (CRP Input)
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********************************
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Clock 1: design_1_i/ddr4_0/inst/u_ddr4_infrastructure/addn_ui_clkout1
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Clock source type: BUFGCE
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Clock source region: X0Y1
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initial rect ((0, 0), (3, 3))
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Clock 2: design_1_i/proc_sys_reset_0/U0/peripheral_aresetn_BUFG[0]
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Clock source type: BUFGCE
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Clock source region: X0Y1
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initial rect ((0, 0), (3, 3))
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Clock 3: design_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk_0
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Clock source type: BUFGCE
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Clock source region: X0Y1
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Clock regions with locked loads: (0, 0) (0, 1)
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initial rect ((0, 0), (1, 3))
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Clock 4: design_1_i/ddr4_0/inst/u_ddr4_infrastructure/dbg_clk
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Clock source type: BUFGCE
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Clock source region: X0Y1
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initial rect ((0, 1), (2, 3))
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Clock 5: design_1_i/ddr4_0/inst/u_ddr4_infrastructure/c0_riu_clk
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Clock source type: BUFGCE
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Clock source region: X0Y1
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Clock regions with locked loads: (0, 0) (0, 1)
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initial rect ((0, 0), (0, 1))
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Clock 6: dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i
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Clock source type: BUFGCE
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Clock source region: X0Y3
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initial rect ((0, 2), (3, 3))
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Clock 7: design_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
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Clock source type: BUFGCE
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Clock source region: X0Y1
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initial rect ((0, 0), (0, 1))
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*****************
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User Constraints:
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*****************
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No user constraints found
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