#-----------------------------------------------------------
# Vivado v2023.2 (64-bit)
# SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
# Start of session at: Wed Jul  8 18:22:37 2026
# Process ID: 9012
# Current directory: C:/proj/ku5p_ccsds122_datamover_uart
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent39400 C:\proj\ku5p_ccsds122_datamover_uart\ccsds122_storage.xpr
# Log file: C:/proj/ku5p_ccsds122_datamover_uart/vivado.log
# Journal file: C:/proj/ku5p_ccsds122_datamover_uart\vivado.jou
# Running On: DESKTOP-EB3SDQ2, OS: Windows, CPU Frequency: 2112 MHz, CPU Physical cores: 16, Host memory: 16817 MB
#-----------------------------------------------------------
start_gui
open_project C:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.xpr
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.1 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.1/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.0 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.0/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.1 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.1/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.1 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.1/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
INFO: [Project 1-313] Project file moved from 'C:/proj/xc7v_ccsds122_datamover_uart' since last save.
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/proj/FPGA_DESIGN_IP'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2023.2/data/ip'.
WARNING: [filemgmt 56-443] The ECC Algorithm string is empty. Setting the Memory Map to default ECC value to ECC_NONE.
WARNING: [filemgmt 56-443] The ECC Algorithm string is empty. Setting the Memory Map to default ECC value to ECC_NONE.
WARNING: [BD 41-1661] One or more IPs have been locked in the design 'design_1.bd'. Please run report_ip_status for more details and recommendations on how to fix this issue.
List of locked IPs:
design_1_ccsds122_datamover_0_0
design_1_ccsds122_axil_slave_0_0

open_project: Time (s): cpu = 00:00:20 ; elapsed = 00:00:12 . Memory (MB): peak = 1747.895 ; gain = 537.418
update_compile_order -fileset sources_1
open_bd_design {C:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd}
Reading block design file <C:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd>...
Adding component instance block -- xilinx.com:user:ccsds122_datamover:1.0 - ccsds122_datamover_0
Adding component instance block -- xilinx.com:ip:smartconnect:1.0 - smartconnect_0
Adding component instance block -- xilinx.com:user:ccsds122_axil_slave:1.0 - ccsds122_axil_slave_0
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - proc_sys_reset_0
Adding component instance block -- xilinx.com:user:ccsds_uart_axi:1.0 - ccsds_uart_axi_0
Adding component instance block -- xilinx.com:ip:ddr4:2.2 - ddr4_0
Adding component instance block -- xilinx.com:ip:util_vector_logic:2.0 - util_vector_logic_0
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - proc_sys_reset_1
Successfully read diagram <design_1> from block design file <C:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd>
report_ip_status -name ip_status 
upgrade_ip [get_ips  {design_1_ccsds122_datamover_0_0 design_1_ccsds122_axil_slave_0_0}] -log ip_upgrade.log
Upgrading 'C:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd'
INFO: [IP_Flow 19-3420] Updated design_1_ccsds122_axil_slave_0_0 to use current project options
WARNING: [IP_Flow 19-4698] Upgrade has added port 'camera_seq'
WARNING: [IP_Flow 19-3298] Detected external port differences while upgrading 'design_1_ccsds122_axil_slave_0_0'. These changes may impact your design.
INFO: [IP_Flow 19-3420] Updated design_1_ccsds122_datamover_0_0 to use current project options
WARNING: [IP_Flow 19-4698] Upgrade has added port 'camera_seq'
WARNING: [IP_Flow 19-3298] Detected external port differences while upgrading 'design_1_ccsds122_datamover_0_0'. These changes may impact your design.
CRITICAL WARNING: [Coretcl 2-1279] The upgrade of 'design_1_ccsds122_axil_slave_0_0' has identified issues that may require user intervention. Please review the upgrade log 'c:/proj/ku5p_ccsds122_datamover_uart/ip_upgrade.log', and verify that the upgraded IP is correctly configured.
CRITICAL WARNING: [Coretcl 2-1279] The upgrade of 'design_1_ccsds122_datamover_0_0' has identified issues that may require user intervention. Please review the upgrade log 'c:/proj/ku5p_ccsds122_datamover_uart/ip_upgrade.log', and verify that the upgraded IP is correctly configured.
Wrote  : <C:\proj\ku5p_ccsds122_datamover_uart\ccsds122_storage.srcs\sources_1\bd\design_1\design_1.bd> 
Wrote  : <C:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui> 
INFO: [Coretcl 2-1525] Wrote upgrade log to 'C:/proj/ku5p_ccsds122_datamover_uart/ip_upgrade.log'.
export_ip_user_files -of_objects [get_ips {design_1_ccsds122_datamover_0_0 design_1_ccsds122_axil_slave_0_0}] -no_script -sync -force -quiet
report_ip_status -name ip_status 
connect_bd_net [get_bd_pins ccsds122_axil_slave_0/camera_seq] [get_bd_pins ccsds122_datamover_0/camera_seq]
regenerate_bd_layout
validate_bd_design
INFO: [Device 21-403] Loading part xcku5p-ffvb676-2-i
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_1: SmartConnect design_1_smartconnect_0_1 is in High-performance Mode.
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ddr4_0/C0_DDR4_S_AXI(0) and /smartconnect_0/M00_AXI(4)
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ddr4_0/C0_DDR4_S_AXI(0) and /smartconnect_0/M00_AXI(4)
validate_bd_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 3325.590 ; gain = 1484.125
report_ip_status -name ip_status 
reset_run synth_1_copy_1
INFO: [Project 1-1161] Replacing file C:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.srcs/utils_1/imports/synth_1/design_1_wrapper.dcp with file C:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1_copy_1/design_1_wrapper.dcp
launch_runs impl_2 -to_step write_bitstream -jobs 24
INFO: [BD 41-1662] The design 'design_1.bd' is already validated. Therefore parameter propagation will not be re-run.
Wrote  : <C:\proj\ku5p_ccsds122_datamover_uart\ccsds122_storage.srcs\sources_1\bd\design_1\design_1.bd> 
Wrote  : <C:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui> 
Verilog Output written to : c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
Verilog Output written to : c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/sim/design_1.v
Verilog Output written to : c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
INFO: [BD 41-1029] Generation completed for the IP Integrator block ccsds122_datamover_0 .
Exporting to file c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/hw_handoff/design_1_smartconnect_0_1.hwh
Generated Hardware Definition File c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/synth/design_1_smartconnect_0_1.hwdef
INFO: [BD 41-1029] Generation completed for the IP Integrator block smartconnect_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ccsds122_axil_slave_0 .
INFO: [BD 41-1637] Generated targets are already up-to-date for block design 'bd_45eb' - hence not re-generating.
Exporting to file c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh
Generated Hardware Definition File c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.hwdef
INFO: [IP_Flow 19-6930] IPCACHE: runCacheChecks() number of threads = 8
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_ccsds122_axil_slave_0_0
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_ccsds122_datamover_0_0
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_smartconnect_0_1
INFO: [IP_Flow 19-8020] IPCACHE: runCacheChecks() calling threadPool finishWork()
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds122_axil_slave_0_0
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds122_datamover_0_0
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_smartconnect_0_1
INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry ee5612f3004935d6 to dir: c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/e/e/ee5612f3004935d6/design_1_smartconnect_0_1.dcp to c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1.dcp.
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1.dcp
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/e/e/ee5612f3004935d6/design_1_smartconnect_0_1_sim_netlist.v to c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.v.
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.v
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/e/e/ee5612f3004935d6/design_1_smartconnect_0_1_sim_netlist.vhdl to c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.vhdl.
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.vhdl
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/e/e/ee5612f3004935d6/design_1_smartconnect_0_1_stub.v to c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.v.
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.v
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/e/e/ee5612f3004935d6/design_1_smartconnect_0_1_stub.vhdl to c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.vhdl.
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.vhdl
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_smartconnect_0_1, cache-ID = ee5612f3004935d6; cache size = 6544.648 MB.
[Wed Jul  8 18:25:51 2026] Launched design_1_ccsds122_datamover_0_0_synth_1, design_1_ccsds122_axil_slave_0_0_synth_1, synth_1_copy_1...
Run output will be captured here:
design_1_ccsds122_datamover_0_0_synth_1: C:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ccsds122_datamover_0_0_synth_1/runme.log
design_1_ccsds122_axil_slave_0_0_synth_1: C:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ccsds122_axil_slave_0_0_synth_1/runme.log
synth_1_copy_1: C:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1_copy_1/runme.log
[Wed Jul  8 18:25:51 2026] Launched impl_2...
Run output will be captured here: C:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.runs/impl_2/runme.log
launch_runs: Time (s): cpu = 00:00:26 ; elapsed = 00:00:30 . Memory (MB): peak = 3527.219 ; gain = 187.266
exit
INFO: [Common 17-206] Exiting Vivado at Wed Jul  8 19:11:25 2026...