-------------------------------------
| Tool Version : Vivado v.2023.2
| Date         : Wed Jul  8 18:43:07 2026
| Host         : DESKTOP-EB3SDQ2
| Design       : design_1
| Device       : xcku5p-ffvb676-2-I-
-------------------------------------

For more information on clockInfo.txt clock routing debug file see https://support.xilinx.com/s/article/000035660?language=en_US

***********************
Running Pre-CRP Checker
***********************
Number of global clocks: 7
	Number of BUFGCE: 7
	Number of BUFGCE_HDIO: 0
	Number of BUFG_CTRL: 0
	Number of BUFGCE_DIV: 0
	Number of BUFG_GT: 0
	Number of BUFG_PS: 0
	Number of BUFG_FABRIC: 0
	Running suboptimal placement checker for 3 clocks (and their loads) which do not have the CLOCK_LOW_FANOUT property but have a fanout less than 2000...
		No sub-optimality found
Pre-CRP Checker took 0 secs

********************************
Clock Net Route Info (CRP Input)
********************************
Clock 1: design_1_i/ddr4_0/inst/u_ddr4_infrastructure/addn_ui_clkout1
	Clock source type: BUFGCE
	Clock source region: X0Y1
	initial rect ((0, 0), (3, 3))

Clock 2: design_1_i/proc_sys_reset_0/U0/peripheral_aresetn_BUFG[0]
	Clock source type: BUFGCE
	Clock source region: X0Y1
	initial rect ((0, 0), (3, 3))

Clock 3: design_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk_0
	Clock source type: BUFGCE
	Clock source region: X0Y1
	Clock regions with locked loads: (0, 0) (0, 1) 
	initial rect ((0, 0), (1, 3))

Clock 4: design_1_i/ddr4_0/inst/u_ddr4_infrastructure/dbg_clk
	Clock source type: BUFGCE
	Clock source region: X0Y1
	initial rect ((0, 1), (2, 3))

Clock 5: design_1_i/ddr4_0/inst/u_ddr4_infrastructure/c0_riu_clk
	Clock source type: BUFGCE
	Clock source region: X0Y1
	Clock regions with locked loads: (0, 0) (0, 1) 
	initial rect ((0, 0), (0, 1))

Clock 6: dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i
	Clock source type: BUFGCE
	Clock source region: X0Y3
	initial rect ((0, 2), (3, 3))

Clock 7: design_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
	Clock source type: BUFGCE
	Clock source region: X0Y1
	initial rect ((0, 0), (0, 1))



*****************
User Constraints:
*****************
No user constraints found