1276 lines
214 KiB
Plaintext
1276 lines
214 KiB
Plaintext
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#-----------------------------------------------------------
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# Vivado v2023.2 (64-bit)
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# SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023
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# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
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# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
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# Start of session at: Mon Jul 6 23:17:19 2026
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# Process ID: 29448
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# Current directory: C:/proj/xc7v_ccsds122_datamover_uart
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# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent36000 C:\proj\xc7v_ccsds122_datamover_uart\ccsds122_storage.xpr
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# Log file: C:/proj/xc7v_ccsds122_datamover_uart/vivado.log
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# Journal file: C:/proj/xc7v_ccsds122_datamover_uart\vivado.jou
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# Running On: DESKTOP-EB3SDQ2, OS: Windows, CPU Frequency: 2112 MHz, CPU Physical cores: 16, Host memory: 16817 MB
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#-----------------------------------------------------------
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start_gui
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open_project C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.xpr
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.1 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.1/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.0 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.0/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.1 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.1/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.1 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.1/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
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Scanning sources...
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Finished scanning sources
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INFO: [IP_Flow 19-234] Refreshing IP repositories
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INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/proj/FPGA_DESIGN_IP'.
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INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2023.2/data/ip'.
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WARNING: [filemgmt 56-443] The ECC Algorithm string is empty. Setting the Memory Map to default ECC value to ECC_NONE.
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WARNING: [filemgmt 56-443] The ECC Algorithm string is empty. Setting the Memory Map to default ECC value to ECC_NONE.
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open_project: Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1855.602 ; gain = 634.102
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update_compile_order -fileset sources_1
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open_bd_design {C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd}
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Reading block design file <C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd>...
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Adding component instance block -- xilinx.com:user:ccsds122_datamover:1.0 - ccsds122_datamover_0
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Adding component instance block -- xilinx.com:ip:smartconnect:1.0 - smartconnect_0
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Adding component instance block -- xilinx.com:user:ccsds122_axil_slave:1.0 - ccsds122_axil_slave_0
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Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - proc_sys_reset_0
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Adding component instance block -- xilinx.com:user:ccsds_uart_axi:1.0 - ccsds_uart_axi_0
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Adding component instance block -- xilinx.com:ip:ddr4:2.2 - ddr4_0
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Adding component instance block -- xilinx.com:ip:util_vector_logic:2.0 - util_vector_logic_0
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Adding component instance block -- xilinx.com:ip:system_ila:1.1 - system_ila_0
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Adding component instance block -- xilinx.com:ip:system_ila:1.1 - system_ila_1
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Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - proc_sys_reset_1
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Successfully read diagram <design_1> from block design file <C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd>
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INFO: [Device 21-403] Loading part xcku5p-ffvb676-2-i
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CRITICAL WARNING: [Common 17-3551] The parameter 'ipgui.displayPowerEstimation' is obsolete. All references to this parameter should be removed.
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startgroup
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set_property -dict [list \
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CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100} \
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CONFIG.C0.DDR4_InputClockPeriod {10000} \
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] [get_bd_cells ddr4_0]
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WARNING: [BD 5-699] No address segments matched 'get_bd_addr_segs -of_object /ilmb_cntlr/SLMB/Mem'
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WARNING: [BD 5-699] No address segments matched 'get_bd_addr_segs -of_object /second_ilmb_cntlr/SLMB/Mem'
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WARNING: [BD 5-699] No address segments matched 'get_bd_addr_segs -of_object /dlmb_cntlr/SLMB/Mem'
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WARNING: [BD 5-699] No address segments matched 'get_bd_addr_segs -of_object /second_dlmb_cntlr/SLMB/Mem'
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WARNING: [BD 5-699] No address segments matched 'get_bd_addr_segs -of_object /iomodule_0/SLMB/Reg'
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WARNING: [BD 5-699] No address segments matched 'get_bd_addr_segs -of_object /iomodule_0/SLMB/IO'
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endgroup
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regenerate_bd_layout
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validate_bd_design
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INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
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INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
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INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
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INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_1: SmartConnect design_1_smartconnect_0_1 is in High-performance Mode.
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CRITICAL WARNING: [xilinx.com:ip:ddr4:2.2-1] /ddr4_0 Clock frequency of the connected clock (/ddr4_0/C0_SYS_CLK) is 200.000000 MHz while "Reference Input Clock Speed" is 100.000 MHz. Please either reconfigure the parameter "Reference Input Clock Speed (CONFIG.C0.DDR4_InputClockPeriod)" of IP or change frequency of the connected clock (CONFIG.FREQ_HZ) within the range of 99950024.988 to 100050025.013 Hz.
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WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ddr4_0/C0_DDR4_S_AXI(0) and /smartconnect_0/M00_AXI(4)
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WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ddr4_0/C0_DDR4_S_AXI(0) and /smartconnect_0/M00_AXI(4)
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validate_bd_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 3635.137 ; gain = 68.496
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delete_bd_objs [get_bd_intf_nets c0_sys_clk]
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startgroup
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make_bd_intf_pins_external [get_bd_intf_pins ddr4_0/C0_SYS_CLK]
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endgroup
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delete_bd_objs [get_bd_intf_ports c0_sys_clk]
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set_property name c0_sys_clk [get_bd_intf_nets C0_SYS_CLK_0_1]
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c0_sys_clk
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set_property name c0_sys_clk [get_bd_intf_ports C0_SYS_CLK_0]
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validate_bd_design
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INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
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||
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|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
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|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
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INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_1: SmartConnect design_1_smartconnect_0_1 is in High-performance Mode.
|
||
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|
CRITICAL WARNING: [xilinx.com:ip:ddr4:2.2-1] /ddr4_0 Clock frequency of the connected clock (/ddr4_0/C0_SYS_CLK) is 200.000000 MHz while "Reference Input Clock Speed" is 100.000 MHz. Please either reconfigure the parameter "Reference Input Clock Speed (CONFIG.C0.DDR4_InputClockPeriod)" of IP or change frequency of the connected clock (CONFIG.FREQ_HZ) within the range of 99950024.988 to 100050025.013 Hz.
|
||
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WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ddr4_0/C0_DDR4_S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
||
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WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ddr4_0/C0_DDR4_S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
||
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validate_bd_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 3700.312 ; gain = 2.410
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regenerate_bd_layout
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||
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validate_bd_design -force
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INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_1: SmartConnect design_1_smartconnect_0_1 is in High-performance Mode.
|
||
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|
CRITICAL WARNING: [xilinx.com:ip:ddr4:2.2-1] /ddr4_0 Clock frequency of the connected clock (/ddr4_0/C0_SYS_CLK) is 200.000000 MHz while "Reference Input Clock Speed" is 100.000 MHz. Please either reconfigure the parameter "Reference Input Clock Speed (CONFIG.C0.DDR4_InputClockPeriod)" of IP or change frequency of the connected clock (CONFIG.FREQ_HZ) within the range of 99950024.988 to 100050025.013 Hz.
|
||
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WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ddr4_0/C0_DDR4_S_AXI(0) and /smartconnect_0/M00_AXI(4)
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||
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WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ddr4_0/C0_DDR4_S_AXI(0) and /smartconnect_0/M00_AXI(4)
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||
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validate_bd_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 3781.062 ; gain = 36.992
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set_property -dict [list CONFIG.FREQ_HZ 100000000] [get_bd_intf_ports c0_sys_clk]
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regenerate_bd_layout
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validate_bd_design
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INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
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INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
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||
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INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
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||
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INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_1: SmartConnect design_1_smartconnect_0_1 is in High-performance Mode.
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||
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WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ddr4_0/C0_DDR4_S_AXI(0) and /smartconnect_0/M00_AXI(4)
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WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ddr4_0/C0_DDR4_S_AXI(0) and /smartconnect_0/M00_AXI(4)
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validate_bd_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 3790.031 ; gain = 0.000
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reset_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
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WARNING: [filemgmt 56-443] The ECC Algorithm string is empty. Setting the Memory Map to default ECC value to ECC_NONE.
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WARNING: [filemgmt 56-443] The ECC Algorithm string is empty. Setting the Memory Map to default ECC value to ECC_NONE.
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reset_target: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 3821.309 ; gain = 0.000
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export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -sync -no_script -force -quiet
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delete_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
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WARNING: [Vivado 12-1017] Problems encountered:
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||
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1. Failed to delete one or more files in run directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ccsds122_datamover_0_0_synth_1
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||
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||
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WARNING: [Vivado 12-1017] Problems encountered:
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||
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1. Failed to delete one or more files in run directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ccsds122_axil_slave_0_0_synth_1
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||
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|
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||
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WARNING: [Vivado 12-1017] Problems encountered:
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||
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|
1. Failed to delete one or more files in run directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ccsds_uart_axi_0_0_synth_1
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||
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|
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||
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WARNING: [Vivado 12-1017] Problems encountered:
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||
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1. Failed to delete one or more files in run directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ddr4_0_0_synth_1
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||
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||
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WARNING: [Vivado 12-1017] Problems encountered:
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||
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1. Failed to delete one or more files in run directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_system_ila_0_0_synth_1
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reset_run synth_1_copy_1
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INFO: [Project 1-1161] Replacing file C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/utils_1/imports/synth_1/design_1_wrapper.dcp with file C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1_copy_1/design_1_wrapper.dcp
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launch_runs impl_2 -to_step write_bitstream -jobs 24
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INFO: [BD 41-1662] The design 'design_1.bd' is already validated. Therefore parameter propagation will not be re-run.
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Wrote : <C:\proj\xc7v_ccsds122_datamover_uart\ccsds122_storage.srcs\sources_1\bd\design_1\design_1.bd>
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Wrote : <C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
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||
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Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
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Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/sim/design_1.v
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Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
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INFO: [BD 41-1029] Generation completed for the IP Integrator block ccsds122_datamover_0 .
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Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/hw_handoff/design_1_smartconnect_0_1.hwh
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Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/synth/design_1_smartconnect_0_1.hwdef
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||
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INFO: [BD 41-1029] Generation completed for the IP Integrator block smartconnect_0 .
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||
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INFO: [BD 41-1029] Generation completed for the IP Integrator block ccsds122_axil_slave_0 .
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INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_0 .
|
||
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INFO: [BD 41-1029] Generation completed for the IP Integrator block ccsds_uart_axi_0 .
|
||
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WARNING: [filemgmt 56-443] The ECC Algorithm string is empty. Setting the Memory Map to default ECC value to ECC_NONE.
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||
|
|
WARNING: [filemgmt 56-443] The ECC Algorithm string is empty. Setting the Memory Map to default ECC value to ECC_NONE.
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||
|
|
WARNING: [filemgmt 56-443] The ECC Algorithm string is empty. Setting the Memory Map to default ECC value to ECC_NONE.
|
||
|
|
WARNING: [filemgmt 56-443] The ECC Algorithm string is empty. Setting the Memory Map to default ECC value to ECC_NONE.
|
||
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/hw_handoff/design_1_ddr4_0_0_microblaze_mcs.hwh
|
||
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/synth/design_1_ddr4_0_0_microblaze_mcs.hwdef
|
||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block ddr4_0 .
|
||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_vector_logic_0 .
|
||
|
|
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_ooc.xdc'
|
||
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/hw_handoff/design_1_system_ila_0_0.hwh
|
||
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/synth/design_1_system_ila_0_0.hwdef
|
||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block system_ila_0 .
|
||
|
|
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_ooc.xdc'
|
||
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/hw_handoff/design_1_system_ila_0_1.hwh
|
||
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/synth/design_1_system_ila_0_1.hwdef
|
||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block system_ila_1 .
|
||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_1 .
|
||
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh
|
||
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.hwdef
|
||
|
|
INFO: [IP_Flow 19-6930] IPCACHE: runCacheChecks() number of threads = 8
|
||
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_ccsds122_axil_slave_0_0
|
||
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_ccsds122_datamover_0_0
|
||
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_ccsds_uart_axi_0_0
|
||
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_ddr4_0_0
|
||
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_proc_sys_reset_0_0
|
||
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_proc_sys_reset_0_1
|
||
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_smartconnect_0_1
|
||
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_system_ila_0_0
|
||
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_system_ila_0_1
|
||
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_util_vector_logic_0_4
|
||
|
|
INFO: [IP_Flow 19-8020] IPCACHE: runCacheChecks() calling threadPool finishWork()
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds122_axil_slave_0_0
|
||
|
|
INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry 5a7ca8a7bd33a825 to dir: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_axil_slave_0_0
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/5/a/5a7ca8a7bd33a825/design_1_ccsds122_axil_slave_0_0.dcp to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_axil_slave_0_0/design_1_ccsds122_axil_slave_0_0.dcp.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_axil_slave_0_0/design_1_ccsds122_axil_slave_0_0.dcp
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/5/a/5a7ca8a7bd33a825/design_1_ccsds122_axil_slave_0_0_sim_netlist.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_axil_slave_0_0/design_1_ccsds122_axil_slave_0_0_sim_netlist.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_axil_slave_0_0/design_1_ccsds122_axil_slave_0_0_sim_netlist.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/5/a/5a7ca8a7bd33a825/design_1_ccsds122_axil_slave_0_0_sim_netlist.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_axil_slave_0_0/design_1_ccsds122_axil_slave_0_0_sim_netlist.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_axil_slave_0_0/design_1_ccsds122_axil_slave_0_0_sim_netlist.vhdl
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/5/a/5a7ca8a7bd33a825/design_1_ccsds122_axil_slave_0_0_stub.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_axil_slave_0_0/design_1_ccsds122_axil_slave_0_0_stub.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_axil_slave_0_0/design_1_ccsds122_axil_slave_0_0_stub.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/5/a/5a7ca8a7bd33a825/design_1_ccsds122_axil_slave_0_0_stub.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_axil_slave_0_0/design_1_ccsds122_axil_slave_0_0_stub.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_axil_slave_0_0/design_1_ccsds122_axil_slave_0_0_stub.vhdl
|
||
|
|
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_ccsds122_axil_slave_0_0, cache-ID = 5a7ca8a7bd33a825; cache size = 5384.270 MB.
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds122_datamover_0_0
|
||
|
|
INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry 6f5cc5d2a223fc8a to dir: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/6/f/6f5cc5d2a223fc8a/design_1_ccsds122_datamover_0_0.dcp to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/design_1_ccsds122_datamover_0_0.dcp.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/design_1_ccsds122_datamover_0_0.dcp
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/6/f/6f5cc5d2a223fc8a/design_1_ccsds122_datamover_0_0_sim_netlist.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/design_1_ccsds122_datamover_0_0_sim_netlist.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/design_1_ccsds122_datamover_0_0_sim_netlist.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/6/f/6f5cc5d2a223fc8a/design_1_ccsds122_datamover_0_0_sim_netlist.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/design_1_ccsds122_datamover_0_0_sim_netlist.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/design_1_ccsds122_datamover_0_0_sim_netlist.vhdl
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/6/f/6f5cc5d2a223fc8a/design_1_ccsds122_datamover_0_0_stub.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/design_1_ccsds122_datamover_0_0_stub.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/design_1_ccsds122_datamover_0_0_stub.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/6/f/6f5cc5d2a223fc8a/design_1_ccsds122_datamover_0_0_stub.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/design_1_ccsds122_datamover_0_0_stub.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/design_1_ccsds122_datamover_0_0_stub.vhdl
|
||
|
|
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_ccsds122_datamover_0_0, cache-ID = 6f5cc5d2a223fc8a; cache size = 5384.270 MB.
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds_uart_axi_0_0
|
||
|
|
INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry 011720553d57817c to dir: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/0/1/011720553d57817c/design_1_ccsds_uart_axi_0_0.dcp to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/design_1_ccsds_uart_axi_0_0.dcp.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/design_1_ccsds_uart_axi_0_0.dcp
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/0/1/011720553d57817c/design_1_ccsds_uart_axi_0_0_sim_netlist.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/design_1_ccsds_uart_axi_0_0_sim_netlist.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/design_1_ccsds_uart_axi_0_0_sim_netlist.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/0/1/011720553d57817c/design_1_ccsds_uart_axi_0_0_sim_netlist.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/design_1_ccsds_uart_axi_0_0_sim_netlist.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/design_1_ccsds_uart_axi_0_0_sim_netlist.vhdl
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/0/1/011720553d57817c/design_1_ccsds_uart_axi_0_0_stub.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/design_1_ccsds_uart_axi_0_0_stub.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/design_1_ccsds_uart_axi_0_0_stub.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/0/1/011720553d57817c/design_1_ccsds_uart_axi_0_0_stub.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/design_1_ccsds_uart_axi_0_0_stub.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/design_1_ccsds_uart_axi_0_0_stub.vhdl
|
||
|
|
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_ccsds_uart_axi_0_0, cache-ID = 011720553d57817c; cache size = 5384.270 MB.
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ddr4_0_0
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_proc_sys_reset_0_0
|
||
|
|
INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry 7b8f30c2376409d5 to dir: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/b/7b8f30c2376409d5/design_1_proc_sys_reset_0_0.dcp to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0.dcp.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0.dcp
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/b/7b8f30c2376409d5/design_1_proc_sys_reset_0_0_sim_netlist.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0_sim_netlist.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0_sim_netlist.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/b/7b8f30c2376409d5/design_1_proc_sys_reset_0_0_sim_netlist.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0_sim_netlist.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0_sim_netlist.vhdl
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/b/7b8f30c2376409d5/design_1_proc_sys_reset_0_0_stub.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0_stub.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0_stub.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/b/7b8f30c2376409d5/design_1_proc_sys_reset_0_0_stub.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0_stub.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0_stub.vhdl
|
||
|
|
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_proc_sys_reset_0_0, cache-ID = 7b8f30c2376409d5; cache size = 5384.269 MB.
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_proc_sys_reset_0_1
|
||
|
|
INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry a4b02069820e10bb to dir: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/a/4/a4b02069820e10bb/design_1_proc_sys_reset_0_0.dcp to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1.dcp.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1.dcp
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/a/4/a4b02069820e10bb/design_1_proc_sys_reset_0_0_sim_netlist.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1_sim_netlist.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1_sim_netlist.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/a/4/a4b02069820e10bb/design_1_proc_sys_reset_0_0_sim_netlist.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1_sim_netlist.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1_sim_netlist.vhdl
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/a/4/a4b02069820e10bb/design_1_proc_sys_reset_0_0_stub.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1_stub.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1_stub.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/a/4/a4b02069820e10bb/design_1_proc_sys_reset_0_0_stub.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1_stub.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1_stub.vhdl
|
||
|
|
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_proc_sys_reset_0_1, cache-ID = a4b02069820e10bb; cache size = 5384.270 MB.
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_smartconnect_0_1
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_system_ila_0_0
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_system_ila_0_1
|
||
|
|
INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry 754f7c0da7d9e35f to dir: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/5/754f7c0da7d9e35f/design_1_system_ila_0_1.dcp to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1.dcp.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1.dcp
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/5/754f7c0da7d9e35f/design_1_system_ila_0_1_sim_netlist.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_sim_netlist.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_sim_netlist.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/5/754f7c0da7d9e35f/design_1_system_ila_0_1_sim_netlist.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_sim_netlist.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_sim_netlist.vhdl
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/5/754f7c0da7d9e35f/design_1_system_ila_0_1_stub.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_stub.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_stub.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/5/754f7c0da7d9e35f/design_1_system_ila_0_1_stub.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_stub.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_stub.vhdl
|
||
|
|
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_system_ila_0_1, cache-ID = 754f7c0da7d9e35f; cache size = 5384.270 MB.
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_util_vector_logic_0_4
|
||
|
|
INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry ca4b04f643bcc75f to dir: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_4
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/c/a/ca4b04f643bcc75f/design_1_util_vector_logic_0_4.dcp to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_4/design_1_util_vector_logic_0_4.dcp.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_4/design_1_util_vector_logic_0_4.dcp
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/c/a/ca4b04f643bcc75f/design_1_util_vector_logic_0_4_sim_netlist.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_4/design_1_util_vector_logic_0_4_sim_netlist.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_4/design_1_util_vector_logic_0_4_sim_netlist.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/c/a/ca4b04f643bcc75f/design_1_util_vector_logic_0_4_sim_netlist.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_4/design_1_util_vector_logic_0_4_sim_netlist.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_4/design_1_util_vector_logic_0_4_sim_netlist.vhdl
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/c/a/ca4b04f643bcc75f/design_1_util_vector_logic_0_4_stub.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_4/design_1_util_vector_logic_0_4_stub.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_4/design_1_util_vector_logic_0_4_stub.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/c/a/ca4b04f643bcc75f/design_1_util_vector_logic_0_4_stub.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_4/design_1_util_vector_logic_0_4_stub.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_4/design_1_util_vector_logic_0_4_stub.vhdl
|
||
|
|
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_util_vector_logic_0_4, cache-ID = ca4b04f643bcc75f; cache size = 5384.270 MB.
|
||
|
|
config_ip_cache: Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 4215.441 ; gain = 339.805
|
||
|
|
[Mon Jul 6 23:33:58 2026] Launched design_1_ddr4_0_0_synth_1, design_1_smartconnect_0_1_synth_1, design_1_system_ila_0_0_synth_1, synth_1_copy_1...
|
||
|
|
Run output will be captured here:
|
||
|
|
design_1_ddr4_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ddr4_0_0_synth_1/runme.log
|
||
|
|
design_1_smartconnect_0_1_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_smartconnect_0_1_synth_1/runme.log
|
||
|
|
design_1_system_ila_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_system_ila_0_0_synth_1/runme.log
|
||
|
|
synth_1_copy_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1_copy_1/runme.log
|
||
|
|
[Mon Jul 6 23:33:58 2026] Launched impl_2...
|
||
|
|
Run output will be captured here: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/impl_2/runme.log
|
||
|
|
launch_runs: Time (s): cpu = 00:00:38 ; elapsed = 00:00:43 . Memory (MB): peak = 4215.441 ; gain = 394.133
|
||
|
|
delete_bd_objs [get_bd_intf_nets smartconnect_0_M01_AXI]
|
||
|
|
connect_bd_intf_net [get_bd_intf_pins ccsds_uart_axi_0/m_axil] [get_bd_intf_pins system_ila_0/SLOT_0_AXI]
|
||
|
|
undo
|
||
|
|
INFO: [Common 17-17] undo 'connect_bd_intf_net [get_bd_intf_pins ccsds_uart_axi_0/m_axil] [get_bd_intf_pins system_ila_0/SLOT_0_AXI]'
|
||
|
|
connect_bd_intf_net [get_bd_intf_pins ccsds_uart_axi_0/m_axil] [get_bd_intf_pins ccsds122_axil_slave_0/s_axil]
|
||
|
|
connect_bd_intf_net [get_bd_intf_pins system_ila_0/SLOT_0_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI]
|
||
|
|
WARNING: [IP_Flow 19-4318] IP-XACT file does not exist: c:/proj/FPGA_DESIGN_IP/ccsds_uart_axi/component.xml. It will be created.
|
||
|
|
WARNING: [IP_Flow 19-4318] IP-XACT file does not exist: c:/proj/FPGA_DESIGN_IP/ccsds122_datamover/component.xml. It will be created.
|
||
|
|
update_ip_catalog -rebuild -scan_changes
|
||
|
|
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||
|
|
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/proj/FPGA_DESIGN_IP'.
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
upgrade_ip [get_ips {design_1_ccsds122_datamover_0_0 design_1_ccsds_uart_axi_0_0}] -log ip_upgrade.log
|
||
|
|
Upgrading 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd'
|
||
|
|
INFO: [IP_Flow 19-3420] Updated design_1_ccsds122_datamover_0_0 to use current project options
|
||
|
|
INFO: [IP_Flow 19-3420] Updated design_1_ccsds_uart_axi_0_0 to use current project options
|
||
|
|
Wrote : <C:\proj\xc7v_ccsds122_datamover_uart\ccsds122_storage.srcs\sources_1\bd\design_1\design_1.bd>
|
||
|
|
Wrote : <C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
|
||
|
|
INFO: [Coretcl 2-1525] Wrote upgrade log to 'C:/proj/xc7v_ccsds122_datamover_uart/ip_upgrade.log'.
|
||
|
|
export_ip_user_files -of_objects [get_ips {design_1_ccsds122_datamover_0_0 design_1_ccsds_uart_axi_0_0}] -no_script -sync -force -quiet
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
startgroup
|
||
|
|
set_property CONFIG.C_NUM_MONITOR_SLOTS {2} [get_bd_cells system_ila_0]
|
||
|
|
endgroup
|
||
|
|
connect_bd_intf_net [get_bd_intf_pins system_ila_0/SLOT_1_AXI] [get_bd_intf_pins smartconnect_0/S01_AXI]
|
||
|
|
regenerate_bd_layout
|
||
|
|
validate_bd_design
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_1: SmartConnect design_1_smartconnect_0_1 is in High-performance Mode.
|
||
|
|
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ddr4_0/C0_DDR4_S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
||
|
|
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ddr4_0/C0_DDR4_S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
||
|
|
validate_bd_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 4215.441 ; gain = 0.000
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
INFO: [BD 41-1662] The design 'design_1.bd' is already validated. Therefore parameter propagation will not be re-run.
|
||
|
|
Wrote : <C:\proj\xc7v_ccsds122_datamover_uart\ccsds122_storage.srcs\sources_1\bd\design_1\design_1.bd>
|
||
|
|
Wrote : <C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
|
||
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
|
||
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/sim/design_1.v
|
||
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
|
||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block ccsds122_datamover_0 .
|
||
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/hw_handoff/design_1_smartconnect_0_1.hwh
|
||
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/synth/design_1_smartconnect_0_1.hwdef
|
||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block smartconnect_0 .
|
||
|
|
WARNING: [IP_Flow 19-640] IP 'design_1_ccsds_uart_axi_0_0' does not support specified targets: Implementation. Running all supported targets by default.
|
||
|
|
WARNING: [IP_Flow 19-640] IP 'design_1_ccsds_uart_axi_0_0' does not support specified targets: Implementation. Running all supported targets by default.
|
||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block ccsds_uart_axi_0 .
|
||
|
|
INFO: [BD 41-1637] Generated targets are already up-to-date for block design 'bd_45eb' - hence not re-generating.
|
||
|
|
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_ooc.xdc'
|
||
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/hw_handoff/design_1_system_ila_0_0.hwh
|
||
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/synth/design_1_system_ila_0_0.hwdef
|
||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block system_ila_0 .
|
||
|
|
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_ooc.xdc'
|
||
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/hw_handoff/design_1_system_ila_0_1.hwh
|
||
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/synth/design_1_system_ila_0_1.hwdef
|
||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block system_ila_1 .
|
||
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh
|
||
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.hwdef
|
||
|
|
generate_target: Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 4215.441 ; gain = 0.000
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_ccsds122_datamover_0_0] }
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds122_datamover_0_0
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_smartconnect_0_1
|
||
|
|
INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry ee5612f3004935d6 to dir: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/e/e/ee5612f3004935d6/design_1_smartconnect_0_1.dcp to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1.dcp.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1.dcp
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/e/e/ee5612f3004935d6/design_1_smartconnect_0_1_sim_netlist.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/e/e/ee5612f3004935d6/design_1_smartconnect_0_1_sim_netlist.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.vhdl
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/e/e/ee5612f3004935d6/design_1_smartconnect_0_1_stub.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/e/e/ee5612f3004935d6/design_1_smartconnect_0_1_stub.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.vhdl
|
||
|
|
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_smartconnect_0_1, cache-ID = ee5612f3004935d6; cache size = 5461.697 MB.
|
||
|
|
catch { [ delete_ip_run [get_ips -all design_1_smartconnect_0_1] ] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_ccsds_uart_axi_0_0] }
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds_uart_axi_0_0
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_system_ila_0_0
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_1] }
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_system_ila_0_1
|
||
|
|
INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry 754f7c0da7d9e35f to dir: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/5/754f7c0da7d9e35f/design_1_system_ila_0_1.dcp to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1.dcp.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1.dcp
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/5/754f7c0da7d9e35f/design_1_system_ila_0_1_sim_netlist.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_sim_netlist.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_sim_netlist.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/5/754f7c0da7d9e35f/design_1_system_ila_0_1_sim_netlist.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_sim_netlist.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_sim_netlist.vhdl
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/5/754f7c0da7d9e35f/design_1_system_ila_0_1_stub.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_stub.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_stub.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/5/754f7c0da7d9e35f/design_1_system_ila_0_1_stub.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_stub.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_stub.vhdl
|
||
|
|
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_system_ila_0_1, cache-ID = 754f7c0da7d9e35f; cache size = 5461.697 MB.
|
||
|
|
config_ip_cache: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 4215.441 ; gain = 0.000
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
||
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
launch_runs design_1_ccsds122_datamover_0_0_synth_1 design_1_ccsds_uart_axi_0_0_synth_1 design_1_system_ila_0_0_synth_1 -jobs 24
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds122_datamover_0_0
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds_uart_axi_0_0
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_system_ila_0_0
|
||
|
|
[Tue Jul 7 00:47:43 2026] Launched design_1_ccsds122_datamover_0_0_synth_1, design_1_ccsds_uart_axi_0_0_synth_1, design_1_system_ila_0_0_synth_1...
|
||
|
|
Run output will be captured here:
|
||
|
|
design_1_ccsds122_datamover_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ccsds122_datamover_0_0_synth_1/runme.log
|
||
|
|
design_1_ccsds_uart_axi_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ccsds_uart_axi_0_0_synth_1/runme.log
|
||
|
|
design_1_system_ila_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_system_ila_0_0_synth_1/runme.log
|
||
|
|
export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
||
|
|
reset_run synth_1_copy_1
|
||
|
|
INFO: [Project 1-1161] Replacing file C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/utils_1/imports/synth_1/design_1_wrapper.dcp with file C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1_copy_1/design_1_wrapper.dcp
|
||
|
|
WARNING: [Vivado 12-1017] Problems encountered:
|
||
|
|
1. Failed to delete one or more files in run directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1_copy_1
|
||
|
|
|
||
|
|
launch_runs impl_2 -to_step write_bitstream -jobs 24
|
||
|
|
INFO: [IP_Flow 19-6930] IPCACHE: runCacheChecks() number of threads = 8
|
||
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_ccsds122_datamover_0_0
|
||
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_ccsds_uart_axi_0_0
|
||
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_system_ila_0_0
|
||
|
|
INFO: [IP_Flow 19-8020] IPCACHE: runCacheChecks() calling threadPool finishWork()
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds122_datamover_0_0
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds_uart_axi_0_0
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_system_ila_0_0
|
||
|
|
[Tue Jul 7 00:48:12 2026] Launched design_1_system_ila_0_0_synth_1, design_1_ccsds122_datamover_0_0_synth_1, design_1_ccsds_uart_axi_0_0_synth_1, synth_1_copy_1...
|
||
|
|
Run output will be captured here:
|
||
|
|
design_1_system_ila_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_system_ila_0_0_synth_1/runme.log
|
||
|
|
design_1_ccsds122_datamover_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ccsds122_datamover_0_0_synth_1/runme.log
|
||
|
|
design_1_ccsds_uart_axi_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ccsds_uart_axi_0_0_synth_1/runme.log
|
||
|
|
synth_1_copy_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1_copy_1/runme.log
|
||
|
|
[Tue Jul 7 00:48:12 2026] Launched impl_2...
|
||
|
|
Run output will be captured here: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/impl_2/runme.log
|
||
|
|
open_run synth_1_copy_1 -name synth_1_copy_1
|
||
|
|
Design is defaulting to impl run constrset: constrs_1
|
||
|
|
Design is defaulting to synth run part: xcku5p-ffvb676-2-i
|
||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_axil_slave_0_0/design_1_ccsds122_axil_slave_0_0.dcp' for cell 'design_1_i/ccsds122_axil_slave_0'
|
||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/design_1_ccsds122_datamover_0_0.dcp' for cell 'design_1_i/ccsds122_datamover_0'
|
||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/design_1_ccsds_uart_axi_0_0.dcp' for cell 'design_1_i/ccsds_uart_axi_0'
|
||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/design_1_ddr4_0_0.dcp' for cell 'design_1_i/ddr4_0'
|
||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0.dcp' for cell 'design_1_i/proc_sys_reset_0'
|
||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1.dcp' for cell 'design_1_i/proc_sys_reset_1'
|
||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1.dcp' for cell 'design_1_i/smartconnect_0'
|
||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0.dcp' for cell 'design_1_i/system_ila_0'
|
||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1.dcp' for cell 'design_1_i/system_ila_1'
|
||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_4/design_1_util_vector_logic_0_4.dcp' for cell 'design_1_i/util_vector_logic_0'
|
||
|
|
Netlist sorting complete. Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 4713.359 ; gain = 44.770
|
||
|
|
INFO: [Netlist 29-17] Analyzing 6826 Unisim elements for replacement
|
||
|
|
INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
|
||
|
|
INFO: [Project 1-479] Netlist was created with Vivado 2023.2
|
||
|
|
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||
|
|
INFO: [Chipscope 16-324] Core: design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl/u_ila_1 UUID: 9c1f4e79-feb5-532b-8648-e7237e71eda8
|
||
|
|
INFO: [Chipscope 16-324] Core: design_1_i/ccsds_uart_axi_0/inst/u_core/u_vio_soft_rst UUID: 62b2038d-2768-5030-a5ac-9430fcab7cee
|
||
|
|
INFO: [Chipscope 16-324] Core: design_1_i/ddr4_0 UUID: 5055ccf3-ab28-5f28-a888-99587c896c7c
|
||
|
|
INFO: [Chipscope 16-324] Core: design_1_i/system_ila_0/inst/ila_lib UUID: cd4c83c8-23a6-596d-99ad-09be1335c6b0
|
||
|
|
INFO: [Chipscope 16-324] Core: design_1_i/system_ila_1/inst/ila_lib UUID: 1ac8c4c2-d1ac-5faa-b5d9-9a6ca09c91e7
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl/u_ila_1/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl/u_ila_1/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl/u_ila_1/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl/u_ila_1/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/axi_datamover_0/axi_datamover_0.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_datamover/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/axi_datamover_0/axi_datamover_0.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_datamover/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/fifo_generator_0/fifo_generator_0.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_bubble_removal/u_pack_fifo/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/fifo_generator_0/fifo_generator_0.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_bubble_removal/u_pack_fifo/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_1/bd_886d_psr0_0_board.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr0/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_1/bd_886d_psr0_0_board.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr0/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_1/bd_886d_psr0_0.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr0/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_1/bd_886d_psr0_0.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr0/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_2/bd_886d_psr_aclk_0_board.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_2/bd_886d_psr_aclk_0_board.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_2/bd_886d_psr_aclk_0.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_2/bd_886d_psr_aclk_0.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_3/bd_886d_psr_aclk1_0_board.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk1/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_3/bd_886d_psr_aclk1_0_board.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk1/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_3/bd_886d_psr_aclk1_0.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk1/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_3/bd_886d_psr_aclk1_0.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk1/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s00_nodes/s00_ar_node/inst'
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:49]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:52]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:55]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:59]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:63]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:66]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:70]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:73]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:76]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:79]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:82]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:85]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:88]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:91]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:94]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:97]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:100]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:104]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:107]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:110]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:113]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:116]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:119]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-13' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:122]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:125]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:128]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-13' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:131]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:134]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:137]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:140]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:143]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:146]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:149]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:152]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:155]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:161]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:164]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:167]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:171]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:174]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:178]
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s00_nodes/s00_ar_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst'
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:49]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:52]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:55]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:59]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:63]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:66]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:70]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:73]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:76]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:79]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:82]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:85]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:88]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:91]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:94]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:97]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:100]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:104]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:107]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:110]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:113]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:116]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:119]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-13' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:122]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:125]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:128]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-13' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:131]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:134]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:137]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:140]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:143]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:146]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:149]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:152]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:155]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:158]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:161]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:164]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:167]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:171]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:174]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:178]
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst'
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:49]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:52]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:55]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:59]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:63]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:66]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:70]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:73]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:76]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:79]
|
||
|
|
INFO: [Common 17-14] Message 'Vivado 12-180' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:82]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:82]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:85]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:88]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:91]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:94]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:97]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:100]
|
||
|
|
INFO: [Common 17-14] Message 'Vivado_Tcl 4-921' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:100]
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_20/bd_886d_swn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_20/bd_886d_swn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_21/bd_886d_sbn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_21/bd_886d_sbn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_26/bd_886d_sarn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_ar_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_26/bd_886d_sarn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_ar_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_27/bd_886d_srn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_r_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_27/bd_886d_srn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_r_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_28/bd_886d_sawn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_aw_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_28/bd_886d_sawn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_aw_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_29/bd_886d_swn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_w_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_29/bd_886d_swn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_w_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_30/bd_886d_sbn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_b_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_30/bd_886d_sbn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_b_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_32/bd_886d_m00arn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_32/bd_886d_m00arn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_33/bd_886d_m00rn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_33/bd_886d_m00rn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_34/bd_886d_m00awn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_34/bd_886d_m00awn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_35/bd_886d_m00wn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_35/bd_886d_m00wn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_36/bd_886d_m00bn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_36/bd_886d_m00bn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/smartconnect.xdc] for cell 'design_1_i/smartconnect_0/inst'
|
||
|
|
WARNING: [Vivado_Tcl 4-919] Waiver ID 'CDC-1' -from list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/smartconnect.xdc:1]
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/smartconnect.xdc] for cell 'design_1_i/smartconnect_0/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0_board.xdc] for cell 'design_1_i/proc_sys_reset_0/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0_board.xdc] for cell 'design_1_i/proc_sys_reset_0/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0.xdc] for cell 'design_1_i/proc_sys_reset_0/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0.xdc] for cell 'design_1_i/proc_sys_reset_0/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/src/vio_0/vio_0.xdc] for cell 'design_1_i/ccsds_uart_axi_0/inst/u_core/u_vio_soft_rst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/src/vio_0/vio_0.xdc] for cell 'design_1_i/ccsds_uart_axi_0/inst/u_core/u_vio_soft_rst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_0/bd_45eb_microblaze_I_0.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_0/bd_45eb_microblaze_I_0.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_1/bd_45eb_rst_0_0_board.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_1/bd_45eb_rst_0_0_board.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_1/bd_45eb_rst_0_0.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_1/bd_45eb_rst_0_0.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_2/bd_45eb_ilmb_0.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_2/bd_45eb_ilmb_0.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_3/bd_45eb_dlmb_0.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/dlmb/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_3/bd_45eb_dlmb_0.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/dlmb/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_10/bd_45eb_iomodule_0_0_board.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_10/bd_45eb_iomodule_0_0_board.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/ip_0/design_1_ddr4_0_0_microblaze_mcs_board.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/ip_0/design_1_ddr4_0_0_microblaze_mcs_board.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/par/design_1_ddr4_0_0.xdc] for cell 'design_1_i/ddr4_0/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/par/design_1_ddr4_0_0.xdc] for cell 'design_1_i/ddr4_0/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/system_ila_0/inst/ila_lib/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/system_ila_0/inst/ila_lib/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/system_ila_0/inst/ila_lib/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/system_ila_0/inst/ila_lib/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/ip/ip_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/system_ila_1/inst/ila_lib/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/ip/ip_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/system_ila_1/inst/ila_lib/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/ip/ip_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/system_ila_1/inst/ila_lib/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/ip/ip_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/system_ila_1/inst/ila_lib/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1_board.xdc] for cell 'design_1_i/proc_sys_reset_1/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1_board.xdc] for cell 'design_1_i/proc_sys_reset_1/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1.xdc] for cell 'design_1_i/proc_sys_reset_1/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1.xdc] for cell 'design_1_i/proc_sys_reset_1/U0'
|
||
|
|
Parsing XDC File [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/constrs_1/new/ccsds122_storage.xdc]
|
||
|
|
Finished Parsing XDC File [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/constrs_1/new/ccsds122_storage.xdc]
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/axi_datamover_0/axi_datamover_0_clocks.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_datamover/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/axi_datamover_0/axi_datamover_0_clocks.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_datamover/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/design_1_ddr4_0_0_board.xdc] for cell 'design_1_i/ddr4_0/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/design_1_ddr4_0_0_board.xdc] for cell 'design_1_i/ddr4_0/inst'
|
||
|
|
INFO: [Project 1-1714] 284 XPM XDC files have been applied to the design.
|
||
|
|
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||
|
|
Generating merged BMM file for the design top 'design_1_wrapper'...
|
||
|
|
Generating merged BMM file for the design top 'design_1_ddr4_0_0'...
|
||
|
|
INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/sw/calibration_0/Debug/calibration_ddr.elf c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/sw/calibration_0/Debug/calibration_ddr.elf
|
||
|
|
INFO: [Project 1-1687] 641 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design.
|
||
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.065 . Memory (MB): peak = 5973.848 ; gain = 0.000
|
||
|
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
||
|
|
A total of 2138 instances were transformed.
|
||
|
|
CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 1092 instances
|
||
|
|
DSP48E1 => DSP48E2 (DSP_ALU, DSP_A_B_DATA, DSP_C_DATA, DSP_MULTIPLIER, DSP_M_DATA, DSP_OUTPUT, DSP_PREADD, DSP_PREADD_DATA): 3 instances
|
||
|
|
IBUF => IBUF (IBUFCTRL, INBUF): 2 instances
|
||
|
|
IBUFDS => IBUFDS (DIFFINBUF, IBUFCTRL): 1 instance
|
||
|
|
IOBUFDS => IOBUFDS (DIFFINBUF, IBUFCTRL, INV, OBUFT(x2)): 4 instances
|
||
|
|
IOBUFE3 => IOBUFE3 (IBUFCTRL, INBUF, OBUFT_DCIEN): 36 instances
|
||
|
|
LUT6_2 => LUT6_2 (LUT5, LUT6): 31 instances
|
||
|
|
OBUFDS => OBUFDS_DUAL_BUF (INV, OBUF(x2)): 1 instance
|
||
|
|
RAM16X1D => RAM32X1D (RAMD32(x2)): 8 instances
|
||
|
|
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 120 instances
|
||
|
|
RAM32M16 => RAM32M16 (RAMD32(x14), RAMS32(x2)): 838 instances
|
||
|
|
RAM32X1D => RAM32X1D (RAMD32(x2)): 2 instances
|
||
|
|
|
||
|
|
open_run: Time (s): cpu = 00:01:49 ; elapsed = 00:01:36 . Memory (MB): peak = 6128.020 ; gain = 1912.578
|
||
|
|
report_utilization -name utilization_1
|
||
|
|
report_utilization: Time (s): cpu = 00:00:26 ; elapsed = 00:00:15 . Memory (MB): peak = 7238.000 ; gain = 1049.621
|
||
|
|
close_design
|
||
|
|
startgroup
|
||
|
|
set_property CONFIG.C_NUM_MONITOR_SLOTS {3} [get_bd_cells system_ila_0]
|
||
|
|
endgroup
|
||
|
|
connect_bd_intf_net [get_bd_intf_pins system_ila_0/SLOT_2_AXI] [get_bd_intf_pins smartconnect_0/S02_AXI]
|
||
|
|
regenerate_bd_layout
|
||
|
|
validate_bd_design
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_1: SmartConnect design_1_smartconnect_0_1 is in High-performance Mode.
|
||
|
|
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ddr4_0/C0_DDR4_S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
||
|
|
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ddr4_0/C0_DDR4_S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
||
|
|
validate_bd_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 7238.000 ; gain = 0.000
|
||
|
|
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
INFO: [BD 41-1662] The design 'design_1.bd' is already validated. Therefore parameter propagation will not be re-run.
|
||
|
|
Wrote : <C:\proj\xc7v_ccsds122_datamover_uart\ccsds122_storage.srcs\sources_1\bd\design_1\design_1.bd>
|
||
|
|
Wrote : <C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
|
||
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
|
||
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/sim/design_1.v
|
||
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
|
||
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/hw_handoff/design_1_smartconnect_0_1.hwh
|
||
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/synth/design_1_smartconnect_0_1.hwdef
|
||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block smartconnect_0 .
|
||
|
|
WARNING: [IP_Flow 19-640] IP 'design_1_ccsds_uart_axi_0_0' does not support specified targets: Implementation. Running all supported targets by default.
|
||
|
|
WARNING: [IP_Flow 19-640] IP 'design_1_ccsds_uart_axi_0_0' does not support specified targets: Implementation. Running all supported targets by default.
|
||
|
|
INFO: [BD 41-1637] Generated targets are already up-to-date for block design 'bd_45eb' - hence not re-generating.
|
||
|
|
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_ooc.xdc'
|
||
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/hw_handoff/design_1_system_ila_0_0.hwh
|
||
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/synth/design_1_system_ila_0_0.hwdef
|
||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block system_ila_0 .
|
||
|
|
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_ooc.xdc'
|
||
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/hw_handoff/design_1_system_ila_0_1.hwh
|
||
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/synth/design_1_system_ila_0_1.hwdef
|
||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block system_ila_1 .
|
||
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh
|
||
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.hwdef
|
||
|
|
generate_target: Time (s): cpu = 00:00:14 ; elapsed = 00:00:17 . Memory (MB): peak = 7238.000 ; gain = 0.000
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_smartconnect_0_1
|
||
|
|
INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry ee5612f3004935d6 to dir: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/e/e/ee5612f3004935d6/design_1_smartconnect_0_1.dcp to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1.dcp.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1.dcp
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/e/e/ee5612f3004935d6/design_1_smartconnect_0_1_sim_netlist.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/e/e/ee5612f3004935d6/design_1_smartconnect_0_1_sim_netlist.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.vhdl
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/e/e/ee5612f3004935d6/design_1_smartconnect_0_1_stub.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/e/e/ee5612f3004935d6/design_1_smartconnect_0_1_stub.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.vhdl
|
||
|
|
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_smartconnect_0_1, cache-ID = ee5612f3004935d6; cache size = 5729.729 MB.
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_system_ila_0_0
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_1] }
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_system_ila_0_1
|
||
|
|
INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry 754f7c0da7d9e35f to dir: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/5/754f7c0da7d9e35f/design_1_system_ila_0_1.dcp to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1.dcp.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1.dcp
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/5/754f7c0da7d9e35f/design_1_system_ila_0_1_sim_netlist.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_sim_netlist.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_sim_netlist.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/5/754f7c0da7d9e35f/design_1_system_ila_0_1_sim_netlist.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_sim_netlist.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_sim_netlist.vhdl
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/5/754f7c0da7d9e35f/design_1_system_ila_0_1_stub.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_stub.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_stub.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/5/754f7c0da7d9e35f/design_1_system_ila_0_1_stub.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_stub.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_stub.vhdl
|
||
|
|
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_system_ila_0_1, cache-ID = 754f7c0da7d9e35f; cache size = 5729.729 MB.
|
||
|
|
config_ip_cache: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 7238.000 ; gain = 0.000
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
||
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
launch_runs design_1_system_ila_0_0_synth_1 -jobs 24
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_system_ila_0_0
|
||
|
|
[Tue Jul 7 01:37:13 2026] Launched design_1_system_ila_0_0_synth_1...
|
||
|
|
Run output will be captured here: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_system_ila_0_0_synth_1/runme.log
|
||
|
|
export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
||
|
|
regenerate_bd_layout
|
||
|
|
reset_run synth_1_copy_1
|
||
|
|
INFO: [Project 1-1161] Replacing file C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/utils_1/imports/synth_1/design_1_wrapper.dcp with file C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1_copy_1/design_1_wrapper.dcp
|
||
|
|
WARNING: [Vivado 12-1017] Problems encountered:
|
||
|
|
1. Failed to delete one or more files in run directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1_copy_1
|
||
|
|
|
||
|
|
launch_runs impl_2 -to_step write_bitstream -jobs 24
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_system_ila_0_0
|
||
|
|
[Tue Jul 7 01:37:52 2026] Launched design_1_system_ila_0_0_synth_1, synth_1_copy_1...
|
||
|
|
Run output will be captured here:
|
||
|
|
design_1_system_ila_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_system_ila_0_0_synth_1/runme.log
|
||
|
|
synth_1_copy_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1_copy_1/runme.log
|
||
|
|
[Tue Jul 7 01:37:52 2026] Launched impl_2...
|
||
|
|
Run output will be captured here: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/impl_2/runme.log
|
||
|
|
open_run synth_1_copy_1 -name synth_1_copy_1
|
||
|
|
Design is defaulting to impl run constrset: constrs_1
|
||
|
|
Design is defaulting to synth run part: xcku5p-ffvb676-2-i
|
||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_axil_slave_0_0/design_1_ccsds122_axil_slave_0_0.dcp' for cell 'design_1_i/ccsds122_axil_slave_0'
|
||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/design_1_ccsds122_datamover_0_0.dcp' for cell 'design_1_i/ccsds122_datamover_0'
|
||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/design_1_ccsds_uart_axi_0_0.dcp' for cell 'design_1_i/ccsds_uart_axi_0'
|
||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/design_1_ddr4_0_0.dcp' for cell 'design_1_i/ddr4_0'
|
||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0.dcp' for cell 'design_1_i/proc_sys_reset_0'
|
||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1.dcp' for cell 'design_1_i/proc_sys_reset_1'
|
||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1.dcp' for cell 'design_1_i/smartconnect_0'
|
||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0.dcp' for cell 'design_1_i/system_ila_0'
|
||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1.dcp' for cell 'design_1_i/system_ila_1'
|
||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_4/design_1_util_vector_logic_0_4.dcp' for cell 'design_1_i/util_vector_logic_0'
|
||
|
|
Netlist sorting complete. Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 7238.000 ; gain = 0.000
|
||
|
|
INFO: [Netlist 29-17] Analyzing 7393 Unisim elements for replacement
|
||
|
|
INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds
|
||
|
|
INFO: [Project 1-479] Netlist was created with Vivado 2023.2
|
||
|
|
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||
|
|
INFO: [Chipscope 16-324] Core: design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl/u_ila_1 UUID: 9c1f4e79-feb5-532b-8648-e7237e71eda8
|
||
|
|
INFO: [Chipscope 16-324] Core: design_1_i/ccsds_uart_axi_0/inst/u_core/u_vio_soft_rst UUID: 62b2038d-2768-5030-a5ac-9430fcab7cee
|
||
|
|
INFO: [Chipscope 16-324] Core: design_1_i/ddr4_0 UUID: 5055ccf3-ab28-5f28-a888-99587c896c7c
|
||
|
|
INFO: [Chipscope 16-324] Core: design_1_i/system_ila_0/inst/ila_lib UUID: cd4c83c8-23a6-596d-99ad-09be1335c6b0
|
||
|
|
INFO: [Chipscope 16-324] Core: design_1_i/system_ila_1/inst/ila_lib UUID: 1ac8c4c2-d1ac-5faa-b5d9-9a6ca09c91e7
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl/u_ila_1/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl/u_ila_1/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl/u_ila_1/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl/u_ila_1/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/axi_datamover_0/axi_datamover_0.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_datamover/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/axi_datamover_0/axi_datamover_0.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_datamover/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/fifo_generator_0/fifo_generator_0.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_bubble_removal/u_pack_fifo/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/fifo_generator_0/fifo_generator_0.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_bubble_removal/u_pack_fifo/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_1/bd_886d_psr0_0_board.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr0/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_1/bd_886d_psr0_0_board.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr0/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_1/bd_886d_psr0_0.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr0/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_1/bd_886d_psr0_0.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr0/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_2/bd_886d_psr_aclk_0_board.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_2/bd_886d_psr_aclk_0_board.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_2/bd_886d_psr_aclk_0.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_2/bd_886d_psr_aclk_0.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_3/bd_886d_psr_aclk1_0_board.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk1/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_3/bd_886d_psr_aclk1_0_board.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk1/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_3/bd_886d_psr_aclk1_0.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk1/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_3/bd_886d_psr_aclk1_0.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk1/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s00_nodes/s00_ar_node/inst'
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:49]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:52]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:55]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:59]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:63]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:66]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:70]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:73]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:76]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:79]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:82]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:85]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:88]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:91]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:94]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:97]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:100]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:104]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:107]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:110]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:113]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:116]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:119]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-13' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:122]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:125]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:128]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-13' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:131]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:134]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:137]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:140]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:143]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:146]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:149]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:152]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:155]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:161]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:164]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:167]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:171]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:174]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:178]
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s00_nodes/s00_ar_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst'
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:49]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:52]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:55]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:59]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:63]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:66]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:70]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:73]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:76]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:79]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:82]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:85]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:88]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:91]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:94]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:97]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:100]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:104]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:107]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:110]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:113]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:116]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:119]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-13' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:122]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:125]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:128]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-13' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:131]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:134]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:137]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:140]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:143]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:146]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:149]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:152]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:155]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:158]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:161]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:164]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:167]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:171]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:174]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:178]
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst'
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:49]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:52]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:55]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:59]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:63]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:66]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:70]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:73]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:76]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:79]
|
||
|
|
INFO: [Common 17-14] Message 'Vivado 12-180' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:82]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:82]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:85]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:88]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:91]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:94]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:97]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:100]
|
||
|
|
INFO: [Common 17-14] Message 'Vivado_Tcl 4-921' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:100]
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_20/bd_886d_swn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_20/bd_886d_swn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_21/bd_886d_sbn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_21/bd_886d_sbn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_26/bd_886d_sarn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_ar_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_26/bd_886d_sarn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_ar_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_27/bd_886d_srn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_r_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_27/bd_886d_srn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_r_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_28/bd_886d_sawn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_aw_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_28/bd_886d_sawn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_aw_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_29/bd_886d_swn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_w_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_29/bd_886d_swn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_w_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_30/bd_886d_sbn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_b_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_30/bd_886d_sbn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_b_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_32/bd_886d_m00arn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_32/bd_886d_m00arn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_33/bd_886d_m00rn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_33/bd_886d_m00rn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_34/bd_886d_m00awn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_34/bd_886d_m00awn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_35/bd_886d_m00wn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_35/bd_886d_m00wn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_36/bd_886d_m00bn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_36/bd_886d_m00bn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/smartconnect.xdc] for cell 'design_1_i/smartconnect_0/inst'
|
||
|
|
WARNING: [Vivado_Tcl 4-919] Waiver ID 'CDC-1' -from list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/smartconnect.xdc:1]
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/smartconnect.xdc] for cell 'design_1_i/smartconnect_0/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0_board.xdc] for cell 'design_1_i/proc_sys_reset_0/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0_board.xdc] for cell 'design_1_i/proc_sys_reset_0/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0.xdc] for cell 'design_1_i/proc_sys_reset_0/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0.xdc] for cell 'design_1_i/proc_sys_reset_0/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/src/vio_0/vio_0.xdc] for cell 'design_1_i/ccsds_uart_axi_0/inst/u_core/u_vio_soft_rst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/src/vio_0/vio_0.xdc] for cell 'design_1_i/ccsds_uart_axi_0/inst/u_core/u_vio_soft_rst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_0/bd_45eb_microblaze_I_0.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_0/bd_45eb_microblaze_I_0.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_1/bd_45eb_rst_0_0_board.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_1/bd_45eb_rst_0_0_board.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_1/bd_45eb_rst_0_0.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_1/bd_45eb_rst_0_0.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_2/bd_45eb_ilmb_0.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_2/bd_45eb_ilmb_0.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_3/bd_45eb_dlmb_0.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/dlmb/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_3/bd_45eb_dlmb_0.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/dlmb/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_10/bd_45eb_iomodule_0_0_board.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_10/bd_45eb_iomodule_0_0_board.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/ip_0/design_1_ddr4_0_0_microblaze_mcs_board.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/ip_0/design_1_ddr4_0_0_microblaze_mcs_board.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/par/design_1_ddr4_0_0.xdc] for cell 'design_1_i/ddr4_0/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/par/design_1_ddr4_0_0.xdc] for cell 'design_1_i/ddr4_0/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/system_ila_0/inst/ila_lib/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/system_ila_0/inst/ila_lib/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/system_ila_0/inst/ila_lib/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/system_ila_0/inst/ila_lib/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/ip/ip_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/system_ila_1/inst/ila_lib/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/ip/ip_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/system_ila_1/inst/ila_lib/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/ip/ip_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/system_ila_1/inst/ila_lib/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/ip/ip_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/system_ila_1/inst/ila_lib/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1_board.xdc] for cell 'design_1_i/proc_sys_reset_1/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1_board.xdc] for cell 'design_1_i/proc_sys_reset_1/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1.xdc] for cell 'design_1_i/proc_sys_reset_1/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1.xdc] for cell 'design_1_i/proc_sys_reset_1/U0'
|
||
|
|
Parsing XDC File [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/constrs_1/new/ccsds122_storage.xdc]
|
||
|
|
Finished Parsing XDC File [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/constrs_1/new/ccsds122_storage.xdc]
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/axi_datamover_0/axi_datamover_0_clocks.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_datamover/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/axi_datamover_0/axi_datamover_0_clocks.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_datamover/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/design_1_ddr4_0_0_board.xdc] for cell 'design_1_i/ddr4_0/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/design_1_ddr4_0_0_board.xdc] for cell 'design_1_i/ddr4_0/inst'
|
||
|
|
INFO: [Project 1-1714] 284 XPM XDC files have been applied to the design.
|
||
|
|
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||
|
|
Generating merged BMM file for the design top 'design_1_wrapper'...
|
||
|
|
Generating merged BMM file for the design top 'design_1_ddr4_0_0'...
|
||
|
|
INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/sw/calibration_0/Debug/calibration_ddr.elf c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/sw/calibration_0/Debug/calibration_ddr.elf
|
||
|
|
INFO: [Project 1-1687] 641 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design.
|
||
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.065 . Memory (MB): peak = 7238.000 ; gain = 0.000
|
||
|
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
||
|
|
A total of 2422 instances were transformed.
|
||
|
|
CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 1376 instances
|
||
|
|
DSP48E1 => DSP48E2 (DSP_ALU, DSP_A_B_DATA, DSP_C_DATA, DSP_MULTIPLIER, DSP_M_DATA, DSP_OUTPUT, DSP_PREADD, DSP_PREADD_DATA): 3 instances
|
||
|
|
IBUF => IBUF (IBUFCTRL, INBUF): 2 instances
|
||
|
|
IBUFDS => IBUFDS (DIFFINBUF, IBUFCTRL): 1 instance
|
||
|
|
IOBUFDS => IOBUFDS (DIFFINBUF, IBUFCTRL, INV, OBUFT(x2)): 4 instances
|
||
|
|
IOBUFE3 => IOBUFE3 (IBUFCTRL, INBUF, OBUFT_DCIEN): 36 instances
|
||
|
|
LUT6_2 => LUT6_2 (LUT5, LUT6): 31 instances
|
||
|
|
OBUFDS => OBUFDS_DUAL_BUF (INV, OBUF(x2)): 1 instance
|
||
|
|
RAM16X1D => RAM32X1D (RAMD32(x2)): 8 instances
|
||
|
|
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 120 instances
|
||
|
|
RAM32M16 => RAM32M16 (RAMD32(x14), RAMS32(x2)): 838 instances
|
||
|
|
RAM32X1D => RAM32X1D (RAMD32(x2)): 2 instances
|
||
|
|
|
||
|
|
open_run: Time (s): cpu = 00:02:03 ; elapsed = 00:01:55 . Memory (MB): peak = 7238.000 ; gain = 0.000
|
||
|
|
report_utilization -name utilization_1
|
||
|
|
report_utilization: Time (s): cpu = 00:00:21 ; elapsed = 00:00:15 . Memory (MB): peak = 8151.863 ; gain = 913.863
|
||
|
|
close_design
|
||
|
|
WARNING: [IP_Flow 19-4318] IP-XACT file does not exist: c:/proj/FPGA_DESIGN_IP/ccsds122_datamover/component.xml. It will be created.
|
||
|
|
update_ip_catalog -rebuild -scan_changes
|
||
|
|
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||
|
|
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/proj/FPGA_DESIGN_IP'.
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
upgrade_ip -vlnv xilinx.com:user:ccsds122_datamover:1.0 [get_ips design_1_ccsds122_datamover_0_0] -log ip_upgrade.log
|
||
|
|
Upgrading 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd'
|
||
|
|
INFO: [IP_Flow 19-3420] Updated design_1_ccsds122_datamover_0_0 to use current project options
|
||
|
|
Wrote : <C:\proj\xc7v_ccsds122_datamover_uart\ccsds122_storage.srcs\sources_1\bd\design_1\design_1.bd>
|
||
|
|
Wrote : <C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
|
||
|
|
INFO: [Coretcl 2-1525] Wrote upgrade log to 'C:/proj/xc7v_ccsds122_datamover_uart/ip_upgrade.log'.
|
||
|
|
export_ip_user_files -of_objects [get_ips design_1_ccsds122_datamover_0_0] -no_script -sync -force -quiet
|
||
|
|
delete_bd_objs [get_bd_cells system_ila_1]
|
||
|
|
delete_bd_objs [get_bd_cells system_ila_0]
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
regenerate_bd_layout
|
||
|
|
validate_bd_design
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_1: SmartConnect design_1_smartconnect_0_1 is in High-performance Mode.
|
||
|
|
xit::source_ipfile: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 8305.875 ; gain = 0.000
|
||
|
|
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ddr4_0/C0_DDR4_S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
||
|
|
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ddr4_0/C0_DDR4_S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
||
|
|
validate_bd_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 8305.875 ; gain = 0.000
|
||
|
|
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
INFO: [BD 41-1662] The design 'design_1.bd' is already validated. Therefore parameter propagation will not be re-run.
|
||
|
|
Wrote : <C:\proj\xc7v_ccsds122_datamover_uart\ccsds122_storage.srcs\sources_1\bd\design_1\design_1.bd>
|
||
|
|
Wrote : <C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
|
||
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
|
||
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/sim/design_1.v
|
||
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
|
||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block ccsds122_datamover_0 .
|
||
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/hw_handoff/design_1_smartconnect_0_1.hwh
|
||
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/synth/design_1_smartconnect_0_1.hwdef
|
||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block smartconnect_0 .
|
||
|
|
WARNING: [IP_Flow 19-640] IP 'design_1_ccsds_uart_axi_0_0' does not support specified targets: Implementation. Running all supported targets by default.
|
||
|
|
WARNING: [IP_Flow 19-640] IP 'design_1_ccsds_uart_axi_0_0' does not support specified targets: Implementation. Running all supported targets by default.
|
||
|
|
INFO: [BD 41-1637] Generated targets are already up-to-date for block design 'bd_45eb' - hence not re-generating.
|
||
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh
|
||
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.hwdef
|
||
|
|
generate_target: Time (s): cpu = 00:00:27 ; elapsed = 00:00:28 . Memory (MB): peak = 8305.875 ; gain = 0.000
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_ccsds122_datamover_0_0] }
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds122_datamover_0_0
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_smartconnect_0_1
|
||
|
|
INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry ee5612f3004935d6 to dir: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/e/e/ee5612f3004935d6/design_1_smartconnect_0_1.dcp to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1.dcp.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1.dcp
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/e/e/ee5612f3004935d6/design_1_smartconnect_0_1_sim_netlist.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/e/e/ee5612f3004935d6/design_1_smartconnect_0_1_sim_netlist.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.vhdl
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/e/e/ee5612f3004935d6/design_1_smartconnect_0_1_stub.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/e/e/ee5612f3004935d6/design_1_smartconnect_0_1_stub.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.vhdl
|
||
|
|
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_smartconnect_0_1, cache-ID = ee5612f3004935d6; cache size = 5756.787 MB.
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
||
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
launch_runs design_1_ccsds122_datamover_0_0_synth_1 -jobs 24
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds122_datamover_0_0
|
||
|
|
[Tue Jul 7 14:23:44 2026] Launched design_1_ccsds122_datamover_0_0_synth_1...
|
||
|
|
Run output will be captured here: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ccsds122_datamover_0_0_synth_1/runme.log
|
||
|
|
export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
reset_run synth_1_copy_1
|
||
|
|
INFO: [Project 1-1161] Replacing file C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/utils_1/imports/synth_1/design_1_wrapper.dcp with file C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1_copy_1/design_1_wrapper.dcp
|
||
|
|
WARNING: [Vivado 12-1017] Problems encountered:
|
||
|
|
1. Failed to delete one or more files in run directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1_copy_1
|
||
|
|
|
||
|
|
launch_runs impl_2 -to_step write_bitstream -jobs 24
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds122_datamover_0_0
|
||
|
|
[Tue Jul 7 14:24:09 2026] Launched design_1_ccsds122_datamover_0_0_synth_1, synth_1_copy_1...
|
||
|
|
Run output will be captured here:
|
||
|
|
design_1_ccsds122_datamover_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ccsds122_datamover_0_0_synth_1/runme.log
|
||
|
|
synth_1_copy_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1_copy_1/runme.log
|
||
|
|
[Tue Jul 7 14:24:09 2026] Launched impl_2...
|
||
|
|
Run output will be captured here: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/impl_2/runme.log
|
||
|
|
WARNING: [IP_Flow 19-4318] IP-XACT file does not exist: c:/proj/FPGA_DESIGN_IP/ccsds122_datamover/component.xml. It will be created.
|
||
|
|
update_ip_catalog -rebuild -scan_changes
|
||
|
|
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||
|
|
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/proj/FPGA_DESIGN_IP'.
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
upgrade_ip -vlnv xilinx.com:user:ccsds122_datamover:1.0 [get_ips design_1_ccsds122_datamover_0_0] -log ip_upgrade.log
|
||
|
|
Upgrading 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd'
|
||
|
|
INFO: [IP_Flow 19-3420] Updated design_1_ccsds122_datamover_0_0 to use current project options
|
||
|
|
Wrote : <C:\proj\xc7v_ccsds122_datamover_uart\ccsds122_storage.srcs\sources_1\bd\design_1\design_1.bd>
|
||
|
|
Wrote : <C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
|
||
|
|
INFO: [Coretcl 2-1525] Wrote upgrade log to 'C:/proj/xc7v_ccsds122_datamover_uart/ip_upgrade.log'.
|
||
|
|
export_ip_user_files -of_objects [get_ips design_1_ccsds122_datamover_0_0] -no_script -sync -force -quiet
|
||
|
|
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_1: SmartConnect design_1_smartconnect_0_1 is in High-performance Mode.
|
||
|
|
xit::source_ipfile: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 8305.875 ; gain = 0.000
|
||
|
|
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ddr4_0/C0_DDR4_S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
||
|
|
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ddr4_0/C0_DDR4_S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
||
|
|
Wrote : <C:\proj\xc7v_ccsds122_datamover_uart\ccsds122_storage.srcs\sources_1\bd\design_1\design_1.bd>
|
||
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
|
||
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/sim/design_1.v
|
||
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
|
||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block ccsds122_datamover_0 .
|
||
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/hw_handoff/design_1_smartconnect_0_1.hwh
|
||
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/synth/design_1_smartconnect_0_1.hwdef
|
||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block smartconnect_0 .
|
||
|
|
WARNING: [IP_Flow 19-640] IP 'design_1_ccsds_uart_axi_0_0' does not support specified targets: Implementation. Running all supported targets by default.
|
||
|
|
WARNING: [IP_Flow 19-640] IP 'design_1_ccsds_uart_axi_0_0' does not support specified targets: Implementation. Running all supported targets by default.
|
||
|
|
INFO: [BD 41-1637] Generated targets are already up-to-date for block design 'bd_45eb' - hence not re-generating.
|
||
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh
|
||
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.hwdef
|
||
|
|
generate_target: Time (s): cpu = 00:00:39 ; elapsed = 00:00:44 . Memory (MB): peak = 8305.875 ; gain = 0.000
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_ccsds122_datamover_0_0] }
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds122_datamover_0_0
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_smartconnect_0_1
|
||
|
|
INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry ee5612f3004935d6 to dir: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/e/e/ee5612f3004935d6/design_1_smartconnect_0_1.dcp to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1.dcp.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1.dcp
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/e/e/ee5612f3004935d6/design_1_smartconnect_0_1_sim_netlist.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/e/e/ee5612f3004935d6/design_1_smartconnect_0_1_sim_netlist.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.vhdl
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/e/e/ee5612f3004935d6/design_1_smartconnect_0_1_stub.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/e/e/ee5612f3004935d6/design_1_smartconnect_0_1_stub.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.vhdl
|
||
|
|
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_smartconnect_0_1, cache-ID = ee5612f3004935d6; cache size = 6020.297 MB.
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
||
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
launch_runs design_1_ccsds122_datamover_0_0_synth_1 -jobs 24
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds122_datamover_0_0
|
||
|
|
[Tue Jul 7 16:46:59 2026] Launched design_1_ccsds122_datamover_0_0_synth_1...
|
||
|
|
Run output will be captured here: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ccsds122_datamover_0_0_synth_1/runme.log
|
||
|
|
export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
reset_run synth_1_copy_1
|
||
|
|
INFO: [Project 1-1161] Replacing file C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/utils_1/imports/synth_1/design_1_wrapper.dcp with file C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1_copy_1/design_1_wrapper.dcp
|
||
|
|
WARNING: [Vivado 12-1017] Problems encountered:
|
||
|
|
1. Failed to delete one or more files in run directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1_copy_1
|
||
|
|
|
||
|
|
launch_runs impl_2 -to_step write_bitstream -jobs 24
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds122_datamover_0_0
|
||
|
|
[Tue Jul 7 16:47:25 2026] Launched design_1_ccsds122_datamover_0_0_synth_1, synth_1_copy_1...
|
||
|
|
Run output will be captured here:
|
||
|
|
design_1_ccsds122_datamover_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ccsds122_datamover_0_0_synth_1/runme.log
|
||
|
|
synth_1_copy_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1_copy_1/runme.log
|
||
|
|
[Tue Jul 7 16:47:25 2026] Launched impl_2...
|
||
|
|
Run output will be captured here: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/impl_2/runme.log
|
||
|
|
update_ip_catalog -rebuild -scan_changes
|
||
|
|
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||
|
|
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/proj/FPGA_DESIGN_IP'.
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
upgrade_ip -vlnv xilinx.com:user:ccsds122_datamover:1.0 [get_ips design_1_ccsds122_datamover_0_0] -log ip_upgrade.log
|
||
|
|
Upgrading 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd'
|
||
|
|
INFO: [IP_Flow 19-3420] Updated design_1_ccsds122_datamover_0_0 to use current project options
|
||
|
|
Wrote : <C:\proj\xc7v_ccsds122_datamover_uart\ccsds122_storage.srcs\sources_1\bd\design_1\design_1.bd>
|
||
|
|
INFO: [Coretcl 2-1525] Wrote upgrade log to 'C:/proj/xc7v_ccsds122_datamover_uart/ip_upgrade.log'.
|
||
|
|
export_ip_user_files -of_objects [get_ips design_1_ccsds122_datamover_0_0] -no_script -sync -force -quiet
|
||
|
|
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_1: SmartConnect design_1_smartconnect_0_1 is in High-performance Mode.
|
||
|
|
xit::source_ipfile: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 8305.875 ; gain = 0.000
|
||
|
|
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ddr4_0/C0_DDR4_S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
||
|
|
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ddr4_0/C0_DDR4_S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
||
|
|
Wrote : <C:\proj\xc7v_ccsds122_datamover_uart\ccsds122_storage.srcs\sources_1\bd\design_1\design_1.bd>
|
||
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
|
||
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/sim/design_1.v
|
||
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
|
||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block ccsds122_datamover_0 .
|
||
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/hw_handoff/design_1_smartconnect_0_1.hwh
|
||
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/synth/design_1_smartconnect_0_1.hwdef
|
||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block smartconnect_0 .
|
||
|
|
WARNING: [IP_Flow 19-640] IP 'design_1_ccsds_uart_axi_0_0' does not support specified targets: Implementation. Running all supported targets by default.
|
||
|
|
WARNING: [IP_Flow 19-640] IP 'design_1_ccsds_uart_axi_0_0' does not support specified targets: Implementation. Running all supported targets by default.
|
||
|
|
INFO: [BD 41-1637] Generated targets are already up-to-date for block design 'bd_45eb' - hence not re-generating.
|
||
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh
|
||
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.hwdef
|
||
|
|
generate_target: Time (s): cpu = 00:00:39 ; elapsed = 00:00:43 . Memory (MB): peak = 8305.875 ; gain = 0.000
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_ccsds122_datamover_0_0] }
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds122_datamover_0_0
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_smartconnect_0_1
|
||
|
|
INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry ee5612f3004935d6 to dir: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/e/e/ee5612f3004935d6/design_1_smartconnect_0_1.dcp to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1.dcp.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1.dcp
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/e/e/ee5612f3004935d6/design_1_smartconnect_0_1_sim_netlist.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/e/e/ee5612f3004935d6/design_1_smartconnect_0_1_sim_netlist.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.vhdl
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/e/e/ee5612f3004935d6/design_1_smartconnect_0_1_stub.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/e/e/ee5612f3004935d6/design_1_smartconnect_0_1_stub.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.vhdl
|
||
|
|
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_smartconnect_0_1, cache-ID = ee5612f3004935d6; cache size = 6281.061 MB.
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
||
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
launch_runs design_1_ccsds122_datamover_0_0_synth_1 -jobs 24
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds122_datamover_0_0
|
||
|
|
[Wed Jul 8 00:47:40 2026] Launched design_1_ccsds122_datamover_0_0_synth_1...
|
||
|
|
Run output will be captured here: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ccsds122_datamover_0_0_synth_1/runme.log
|
||
|
|
export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
reset_run synth_1_copy_1
|
||
|
|
INFO: [Project 1-1161] Replacing file C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/utils_1/imports/synth_1/design_1_wrapper.dcp with file C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1_copy_1/design_1_wrapper.dcp
|
||
|
|
WARNING: [Vivado 12-1017] Problems encountered:
|
||
|
|
1. Failed to delete one or more files in run directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1_copy_1
|
||
|
|
|
||
|
|
launch_runs impl_2 -to_step write_bitstream -jobs 24
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds122_datamover_0_0
|
||
|
|
[Wed Jul 8 00:48:55 2026] Launched design_1_ccsds122_datamover_0_0_synth_1, synth_1_copy_1...
|
||
|
|
Run output will be captured here:
|
||
|
|
design_1_ccsds122_datamover_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ccsds122_datamover_0_0_synth_1/runme.log
|
||
|
|
synth_1_copy_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1_copy_1/runme.log
|
||
|
|
[Wed Jul 8 00:48:55 2026] Launched impl_2...
|
||
|
|
Run output will be captured here: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/impl_2/runme.log
|
||
|
|
WARNING: [IP_Flow 19-4318] IP-XACT file does not exist: c:/proj/FPGA_DESIGN_IP/ccsds_uart_axi/component.xml. It will be created.
|
||
|
|
update_ip_catalog -rebuild -scan_changes
|
||
|
|
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||
|
|
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/proj/FPGA_DESIGN_IP'.
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
upgrade_ip -vlnv xilinx.com:user:ccsds_uart_axi:1.0 [get_ips design_1_ccsds_uart_axi_0_0] -log ip_upgrade.log
|
||
|
|
Upgrading 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd'
|
||
|
|
INFO: [IP_Flow 19-3420] Updated design_1_ccsds_uart_axi_0_0 to use current project options
|
||
|
|
Wrote : <C:\proj\xc7v_ccsds122_datamover_uart\ccsds122_storage.srcs\sources_1\bd\design_1\design_1.bd>
|
||
|
|
Wrote : <C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
|
||
|
|
INFO: [Coretcl 2-1525] Wrote upgrade log to 'C:/proj/xc7v_ccsds122_datamover_uart/ip_upgrade.log'.
|
||
|
|
export_ip_user_files -of_objects [get_ips design_1_ccsds_uart_axi_0_0] -no_script -sync -force -quiet
|
||
|
|
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_1: SmartConnect design_1_smartconnect_0_1 is in High-performance Mode.
|
||
|
|
xit::source_ipfile: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 8305.875 ; gain = 0.000
|
||
|
|
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ddr4_0/C0_DDR4_S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
||
|
|
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ddr4_0/C0_DDR4_S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
||
|
|
Wrote : <C:\proj\xc7v_ccsds122_datamover_uart\ccsds122_storage.srcs\sources_1\bd\design_1\design_1.bd>
|
||
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
|
||
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/sim/design_1.v
|
||
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
|
||
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/hw_handoff/design_1_smartconnect_0_1.hwh
|
||
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/synth/design_1_smartconnect_0_1.hwdef
|
||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block smartconnect_0 .
|
||
|
|
WARNING: [IP_Flow 19-640] IP 'design_1_ccsds_uart_axi_0_0' does not support specified targets: Implementation. Running all supported targets by default.
|
||
|
|
WARNING: [IP_Flow 19-640] IP 'design_1_ccsds_uart_axi_0_0' does not support specified targets: Implementation. Running all supported targets by default.
|
||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block ccsds_uart_axi_0 .
|
||
|
|
INFO: [BD 41-1637] Generated targets are already up-to-date for block design 'bd_45eb' - hence not re-generating.
|
||
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh
|
||
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.hwdef
|
||
|
|
generate_target: Time (s): cpu = 00:00:31 ; elapsed = 00:00:39 . Memory (MB): peak = 8305.875 ; gain = 0.000
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_smartconnect_0_1
|
||
|
|
INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry ee5612f3004935d6 to dir: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/e/e/ee5612f3004935d6/design_1_smartconnect_0_1.dcp to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1.dcp.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1.dcp
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/e/e/ee5612f3004935d6/design_1_smartconnect_0_1_sim_netlist.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/e/e/ee5612f3004935d6/design_1_smartconnect_0_1_sim_netlist.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.vhdl
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/e/e/ee5612f3004935d6/design_1_smartconnect_0_1_stub.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/e/e/ee5612f3004935d6/design_1_smartconnect_0_1_stub.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.vhdl
|
||
|
|
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_smartconnect_0_1, cache-ID = ee5612f3004935d6; cache size = 6541.837 MB.
|
||
|
|
config_ip_cache: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 8305.875 ; gain = 0.000
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_ccsds_uart_axi_0_0] }
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds_uart_axi_0_0
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
||
|
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create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
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launch_runs design_1_ccsds_uart_axi_0_0_synth_1 -jobs 24
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INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds_uart_axi_0_0
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[Wed Jul 8 15:22:12 2026] Launched design_1_ccsds_uart_axi_0_0_synth_1...
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Run output will be captured here: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ccsds_uart_axi_0_0_synth_1/runme.log
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export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
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report_ip_status -name ip_status
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reset_run synth_1_copy_1
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INFO: [Project 1-1161] Replacing file C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/utils_1/imports/synth_1/design_1_wrapper.dcp with file C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1_copy_1/design_1_wrapper.dcp
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launch_runs impl_2 -to_step write_bitstream -jobs 24
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[Wed Jul 8 15:25:01 2026] Launched synth_1_copy_1...
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||
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Run output will be captured here: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1_copy_1/runme.log
|
||
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[Wed Jul 8 15:25:01 2026] Launched impl_2...
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||
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Run output will be captured here: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/impl_2/runme.log
|
||
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exit
|
||
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INFO: [Common 17-206] Exiting Vivado at Wed Jul 8 17:20:41 2026...
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