1601 lines
377 KiB
Plaintext
1601 lines
377 KiB
Plaintext
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*** Running vivado
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with args -log design_1_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source design_1_wrapper.tcl -notrace
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****** Vivado v2023.2 (64-bit)
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**** SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023
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**** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
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**** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
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** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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source design_1_wrapper.tcl -notrace
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create_project: Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 582.895 ; gain = 181.500
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INFO: [IP_Flow 19-234] Refreshing IP repositories
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INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/proj/FPGA_DESIGN_IP'.
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INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2023.2/data/ip'.
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WARNING: [filemgmt 56-443] The ECC Algorithm string is empty. Setting the Memory Map to default ECC value to ECC_NONE.
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WARNING: [filemgmt 56-443] The ECC Algorithm string is empty. Setting the Memory Map to default ECC value to ECC_NONE.
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add_files: Time (s): cpu = 00:00:04 ; elapsed = 00:00:11 . Memory (MB): peak = 681.578 ; gain = 94.707
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Command: link_design -top design_1_wrapper -part xcku5p-ffvb676-2-i
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Design is defaulting to srcset: sources_1
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Design is defaulting to constrset: constrs_1
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INFO: [Device 21-403] Loading part xcku5p-ffvb676-2-i
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INFO: [Project 1-454] Reading design checkpoint 'c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_axil_slave_0_0/design_1_ccsds122_axil_slave_0_0.dcp' for cell 'design_1_i/ccsds122_axil_slave_0'
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INFO: [Project 1-454] Reading design checkpoint 'c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/design_1_ccsds122_datamover_0_0.dcp' for cell 'design_1_i/ccsds122_datamover_0'
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INFO: [Project 1-454] Reading design checkpoint 'c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/design_1_ccsds_uart_axi_0_0.dcp' for cell 'design_1_i/ccsds_uart_axi_0'
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INFO: [Project 1-454] Reading design checkpoint 'c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/design_1_ddr4_0_0.dcp' for cell 'design_1_i/ddr4_0'
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INFO: [Project 1-454] Reading design checkpoint 'c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0.dcp' for cell 'design_1_i/proc_sys_reset_0'
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INFO: [Project 1-454] Reading design checkpoint 'c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1.dcp' for cell 'design_1_i/proc_sys_reset_1'
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INFO: [Project 1-454] Reading design checkpoint 'c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1.dcp' for cell 'design_1_i/smartconnect_0'
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INFO: [Project 1-454] Reading design checkpoint 'c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_4/design_1_util_vector_logic_0_4.dcp' for cell 'design_1_i/util_vector_logic_0'
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Netlist sorting complete. Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2374.938 ; gain = 48.949
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INFO: [Netlist 29-17] Analyzing 6250 Unisim elements for replacement
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INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
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INFO: [Project 1-479] Netlist was created with Vivado 2023.2
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INFO: [Project 1-570] Preparing netlist for logic optimization
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INFO: [Chipscope 16-324] Core: design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_bubble_removal/u_ila_2 UUID: a2690489-e1f2-5bdd-9437-e5bd8b343bbc
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INFO: [Chipscope 16-324] Core: design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl/u_ila_1 UUID: 9c1f4e79-feb5-532b-8648-e7237e71eda8
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INFO: [Chipscope 16-324] Core: design_1_i/ccsds_uart_axi_0/inst/u_core/u_vio_soft_rst UUID: 62b2038d-2768-5030-a5ac-9430fcab7cee
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INFO: [Chipscope 16-324] Core: design_1_i/ddr4_0 UUID: 5055ccf3-ab28-5f28-a888-99587c896c7c
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Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/ila_2/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_bubble_removal/u_ila_2/inst'
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Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/ila_2/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_bubble_removal/u_ila_2/inst'
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Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/ila_2/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_bubble_removal/u_ila_2/inst'
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Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/ila_2/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_bubble_removal/u_ila_2/inst'
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Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/fifo_generator_0/fifo_generator_0.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_bubble_removal/u_pack_fifo/U0'
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Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/fifo_generator_0/fifo_generator_0.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_bubble_removal/u_pack_fifo/U0'
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Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/axi_datamover_0/axi_datamover_0.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_datamover/U0'
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Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/axi_datamover_0/axi_datamover_0.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_datamover/U0'
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Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl/u_ila_1/inst'
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Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl/u_ila_1/inst'
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Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl/u_ila_1/inst'
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Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl/u_ila_1/inst'
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Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_1/bd_886d_psr0_0_board.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr0/U0'
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Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_1/bd_886d_psr0_0_board.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr0/U0'
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Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_1/bd_886d_psr0_0.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr0/U0'
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Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_1/bd_886d_psr0_0.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr0/U0'
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Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_2/bd_886d_psr_aclk_0_board.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
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Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_2/bd_886d_psr_aclk_0_board.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
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Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_2/bd_886d_psr_aclk_0.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
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Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_2/bd_886d_psr_aclk_0.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
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Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_3/bd_886d_psr_aclk1_0_board.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk1/U0'
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Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_3/bd_886d_psr_aclk1_0_board.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk1/U0'
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Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_3/bd_886d_psr_aclk1_0.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk1/U0'
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Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_3/bd_886d_psr_aclk1_0.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk1/U0'
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Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s00_nodes/s00_ar_node/inst'
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:49]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:52]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:55]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:59]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:63]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:66]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:70]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:73]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:76]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:79]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:82]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:85]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:88]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:91]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:94]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:97]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:100]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:104]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:107]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:110]
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WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:113]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:116]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:119]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-13' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:122]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:125]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:128]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-13' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:131]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:134]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:137]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:140]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:143]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:146]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:149]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:152]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:155]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:161]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:164]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:167]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:171]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:174]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:178]
|
|||
|
|
Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s00_nodes/s00_ar_node/inst'
|
|||
|
|
Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst'
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:49]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:52]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:55]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:59]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:63]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:66]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:70]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:73]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:76]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:79]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:82]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:85]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:88]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:91]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:94]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:97]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:100]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:104]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:107]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:110]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:113]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:116]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:119]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-13' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:122]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:125]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:128]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-13' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:131]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:134]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:137]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:140]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:143]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:146]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:149]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:152]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:155]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:158]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:161]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:164]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:167]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:171]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:174]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:178]
|
|||
|
|
Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst'
|
|||
|
|
Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst'
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:49]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:52]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:55]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:59]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:63]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:66]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:70]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:73]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:76]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:79]
|
|||
|
|
INFO: [Common 17-14] Message 'Vivado 12-180' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:82]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:82]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:85]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:88]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:91]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:94]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:97]
|
|||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:100]
|
|||
|
|
INFO: [Common 17-14] Message 'Vivado_Tcl 4-921' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:100]
|
|||
|
|
Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst'
|
|||
|
|
Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_20/bd_886d_swn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_20/bd_886d_swn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst'
|
|||
|
|
Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_21/bd_886d_sbn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_21/bd_886d_sbn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst'
|
|||
|
|
Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_26/bd_886d_sarn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_ar_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_26/bd_886d_sarn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_ar_node/inst'
|
|||
|
|
Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_27/bd_886d_srn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_r_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_27/bd_886d_srn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_r_node/inst'
|
|||
|
|
Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_28/bd_886d_sawn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_aw_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_28/bd_886d_sawn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_aw_node/inst'
|
|||
|
|
Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_29/bd_886d_swn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_w_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_29/bd_886d_swn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_w_node/inst'
|
|||
|
|
Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_30/bd_886d_sbn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_b_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_30/bd_886d_sbn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_b_node/inst'
|
|||
|
|
Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_32/bd_886d_m00arn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_32/bd_886d_m00arn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst'
|
|||
|
|
Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_33/bd_886d_m00rn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_33/bd_886d_m00rn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst'
|
|||
|
|
Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_34/bd_886d_m00awn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_34/bd_886d_m00awn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst'
|
|||
|
|
Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_35/bd_886d_m00wn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_35/bd_886d_m00wn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst'
|
|||
|
|
Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_36/bd_886d_m00bn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_36/bd_886d_m00bn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst'
|
|||
|
|
Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/smartconnect.xdc] for cell 'design_1_i/smartconnect_0/inst'
|
|||
|
|
WARNING: [Vivado_Tcl 4-919] Waiver ID 'CDC-1' -from list should not be empty. [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/smartconnect.xdc:1]
|
|||
|
|
Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/smartconnect.xdc] for cell 'design_1_i/smartconnect_0/inst'
|
|||
|
|
Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0_board.xdc] for cell 'design_1_i/proc_sys_reset_0/U0'
|
|||
|
|
Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0_board.xdc] for cell 'design_1_i/proc_sys_reset_0/U0'
|
|||
|
|
Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0.xdc] for cell 'design_1_i/proc_sys_reset_0/U0'
|
|||
|
|
Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0.xdc] for cell 'design_1_i/proc_sys_reset_0/U0'
|
|||
|
|
Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/src/vio_0/vio_0.xdc] for cell 'design_1_i/ccsds_uart_axi_0/inst/u_core/u_vio_soft_rst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/src/vio_0/vio_0.xdc] for cell 'design_1_i/ccsds_uart_axi_0/inst/u_core/u_vio_soft_rst'
|
|||
|
|
Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_0/bd_45eb_microblaze_I_0.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0'
|
|||
|
|
Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_0/bd_45eb_microblaze_I_0.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0'
|
|||
|
|
Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_1/bd_45eb_rst_0_0_board.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0'
|
|||
|
|
Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_1/bd_45eb_rst_0_0_board.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0'
|
|||
|
|
Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_1/bd_45eb_rst_0_0.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0'
|
|||
|
|
Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_1/bd_45eb_rst_0_0.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0'
|
|||
|
|
Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_2/bd_45eb_ilmb_0.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb/U0'
|
|||
|
|
Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_2/bd_45eb_ilmb_0.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb/U0'
|
|||
|
|
Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_3/bd_45eb_dlmb_0.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/dlmb/U0'
|
|||
|
|
Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_3/bd_45eb_dlmb_0.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/dlmb/U0'
|
|||
|
|
Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_10/bd_45eb_iomodule_0_0_board.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0'
|
|||
|
|
Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_10/bd_45eb_iomodule_0_0_board.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0'
|
|||
|
|
Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/ip_0/design_1_ddr4_0_0_microblaze_mcs_board.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/ip_0/design_1_ddr4_0_0_microblaze_mcs_board.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst'
|
|||
|
|
Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/par/design_1_ddr4_0_0.xdc] for cell 'design_1_i/ddr4_0/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/par/design_1_ddr4_0_0.xdc] for cell 'design_1_i/ddr4_0/inst'
|
|||
|
|
Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1_board.xdc] for cell 'design_1_i/proc_sys_reset_1/U0'
|
|||
|
|
Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1_board.xdc] for cell 'design_1_i/proc_sys_reset_1/U0'
|
|||
|
|
Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1.xdc] for cell 'design_1_i/proc_sys_reset_1/U0'
|
|||
|
|
Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1.xdc] for cell 'design_1_i/proc_sys_reset_1/U0'
|
|||
|
|
Parsing XDC File [C:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.srcs/constrs_1/new/ccsds122_storage.xdc]
|
|||
|
|
Finished Parsing XDC File [C:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.srcs/constrs_1/new/ccsds122_storage.xdc]
|
|||
|
|
Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/axi_datamover_0/axi_datamover_0_clocks.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_datamover/U0'
|
|||
|
|
Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/axi_datamover_0/axi_datamover_0_clocks.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_datamover/U0'
|
|||
|
|
Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/design_1_ddr4_0_0_board.xdc] for cell 'design_1_i/ddr4_0/inst'
|
|||
|
|
Finished Parsing XDC File [c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/design_1_ddr4_0_0_board.xdc] for cell 'design_1_i/ddr4_0/inst'
|
|||
|
|
INFO: [Project 1-1714] 284 XPM XDC files have been applied to the design.
|
|||
|
|
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
|||
|
|
Generating merged BMM file for the design top 'design_1_wrapper'...
|
|||
|
|
INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/sw/calibration_0/Debug/calibration_ddr.elf
|
|||
|
|
INFO: [Project 1-1687] 641 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design.
|
|||
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.056 . Memory (MB): peak = 4005.875 ; gain = 0.000
|
|||
|
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
|||
|
|
A total of 1794 instances were transformed.
|
|||
|
|
CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 748 instances
|
|||
|
|
DSP48E1 => DSP48E2 (DSP_ALU, DSP_A_B_DATA, DSP_C_DATA, DSP_MULTIPLIER, DSP_M_DATA, DSP_OUTPUT, DSP_PREADD, DSP_PREADD_DATA): 3 instances
|
|||
|
|
IBUF => IBUF (IBUFCTRL, INBUF): 2 instances
|
|||
|
|
IBUFDS => IBUFDS (DIFFINBUF, IBUFCTRL): 1 instance
|
|||
|
|
IOBUFDS => IOBUFDS (DIFFINBUF, IBUFCTRL, INV, OBUFT(x2)): 4 instances
|
|||
|
|
IOBUFE3 => IOBUFE3 (IBUFCTRL, INBUF, OBUFT_DCIEN): 36 instances
|
|||
|
|
LUT6_2 => LUT6_2 (LUT5, LUT6): 31 instances
|
|||
|
|
OBUFDS => OBUFDS_DUAL_BUF (INV, OBUF(x2)): 1 instance
|
|||
|
|
RAM16X1D => RAM32X1D (RAMD32(x2)): 8 instances
|
|||
|
|
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 120 instances
|
|||
|
|
RAM32M16 => RAM32M16 (RAMD32(x14), RAMS32(x2)): 838 instances
|
|||
|
|
RAM32X1D => RAM32X1D (RAMD32(x2)): 2 instances
|
|||
|
|
|
|||
|
|
ϵͳ<EFBFBD>Ҳ<EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>·<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
|
27 Infos, 103 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
|||
|
|
link_design completed successfully
|
|||
|
|
link_design: Time (s): cpu = 00:01:26 ; elapsed = 00:01:33 . Memory (MB): peak = 4005.875 ; gain = 3324.297
|
|||
|
|
Command: opt_design
|
|||
|
|
Attempting to get a license for feature 'Implementation' and/or device 'xcku5p'
|
|||
|
|
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xcku5p'
|
|||
|
|
Running DRC as a precondition to command opt_design
|
|||
|
|
|
|||
|
|
Starting DRC Task
|
|||
|
|
INFO: [DRC 23-27] Running DRC with 2 threads
|
|||
|
|
INFO: [Project 1-461] DRC finished with 0 Errors
|
|||
|
|
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 4005.875 ; gain = 0.000
|
|||
|
|
|
|||
|
|
Starting Cache Timing Information Task
|
|||
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|||
|
|
Ending Cache Timing Information Task | Checksum: 1ab374eb3
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 4005.875 ; gain = 0.000
|
|||
|
|
|
|||
|
|
Starting Logic Optimization Task
|
|||
|
|
|
|||
|
|
Phase 1 Initialization
|
|||
|
|
|
|||
|
|
Phase 1.1 Core Generation And Design Setup
|
|||
|
|
|
|||
|
|
Phase 1.1.1 Generate And Synthesize MIG Cores
|
|||
|
|
INFO: [Mig 66-454] Using cached IP synthesis design for IP xilinx.com:ip:ddr4_phy:2.2, cache-ID = 0ec65e6c900fae4b.
|
|||
|
|
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.161 . Memory (MB): peak = 4299.809 ; gain = 0.000
|
|||
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.064 . Memory (MB): peak = 4299.809 ; gain = 0.000
|
|||
|
|
Phase 1.1.1 Generate And Synthesize MIG Cores | Checksum: 13a437bb8
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 4299.809 ; gain = 41.777
|
|||
|
|
|
|||
|
|
Phase 1.1.2 Generate And Synthesize Debug Cores
|
|||
|
|
INFO: [Chipscope 16-329] Generating Script for core instance : dbg_hub
|
|||
|
|
INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:xsdbm:3.0 for cell dbg_hub_CV.
|
|||
|
|
INFO: [Chipscope 16-469] Using cached IP synthesis design for IP xilinx.com:ip:xsdbm:3.0, cache-ID = 9f101eeeaff9680a.
|
|||
|
|
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.162 . Memory (MB): peak = 4299.809 ; gain = 0.000
|
|||
|
|
get_clocks: Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 4337.750 ; gain = 37.941
|
|||
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.140 . Memory (MB): peak = 4341.027 ; gain = 2.984
|
|||
|
|
Phase 1.1.2 Generate And Synthesize Debug Cores | Checksum: 18c8ac51e
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:34 ; elapsed = 00:00:46 . Memory (MB): peak = 4341.031 ; gain = 83.000
|
|||
|
|
Phase 1.1 Core Generation And Design Setup | Checksum: 18c8ac51e
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:34 ; elapsed = 00:00:47 . Memory (MB): peak = 4341.035 ; gain = 83.004
|
|||
|
|
|
|||
|
|
Phase 1.2 Setup Constraints And Sort Netlist
|
|||
|
|
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 18c8ac51e
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:34 ; elapsed = 00:00:47 . Memory (MB): peak = 4341.051 ; gain = 83.020
|
|||
|
|
Phase 1 Initialization | Checksum: 18c8ac51e
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:34 ; elapsed = 00:00:47 . Memory (MB): peak = 4341.051 ; gain = 83.020
|
|||
|
|
|
|||
|
|
Phase 2 Timer Update And Timing Data Collection
|
|||
|
|
|
|||
|
|
Phase 2.1 Timer Update
|
|||
|
|
Phase 2.1 Timer Update | Checksum: 18c8ac51e
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:40 ; elapsed = 00:00:51 . Memory (MB): peak = 4741.902 ; gain = 483.871
|
|||
|
|
|
|||
|
|
Phase 2.2 Timing Data Collection
|
|||
|
|
Phase 2.2 Timing Data Collection | Checksum: 18c8ac51e
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:41 ; elapsed = 00:00:51 . Memory (MB): peak = 4741.902 ; gain = 483.871
|
|||
|
|
Phase 2 Timer Update And Timing Data Collection | Checksum: 18c8ac51e
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:41 ; elapsed = 00:00:51 . Memory (MB): peak = 4741.902 ; gain = 483.871
|
|||
|
|
|
|||
|
|
Phase 3 Retarget
|
|||
|
|
INFO: [Opt 31-1566] Pulled 149 inverters resulting in an inversion of 2220 pins
|
|||
|
|
INFO: [Opt 31-138] Pushed 115 inverter(s) to 20380 load pin(s).
|
|||
|
|
INFO: [Opt 31-49] Retargeted 0 cell(s).
|
|||
|
|
Phase 3 Retarget | Checksum: 1e078bf4d
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:45 ; elapsed = 00:00:55 . Memory (MB): peak = 4741.902 ; gain = 483.871
|
|||
|
|
Retarget | Checksum: 1e078bf4d
|
|||
|
|
INFO: [Opt 31-389] Phase Retarget created 161 cells and removed 539 cells
|
|||
|
|
INFO: [Opt 31-1021] In phase Retarget, 225 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
|
|||
|
|
|
|||
|
|
Phase 4 Constant propagation
|
|||
|
|
INFO: [Opt 31-138] Pushed 13 inverter(s) to 33 load pin(s).
|
|||
|
|
Phase 4 Constant propagation | Checksum: 1bd2544dc
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:47 ; elapsed = 00:00:57 . Memory (MB): peak = 4741.902 ; gain = 483.871
|
|||
|
|
Constant propagation | Checksum: 1bd2544dc
|
|||
|
|
INFO: [Opt 31-389] Phase Constant propagation created 1461 cells and removed 4377 cells
|
|||
|
|
INFO: [Opt 31-1021] In phase Constant propagation, 260 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
|
|||
|
|
|
|||
|
|
Phase 5 Sweep
|
|||
|
|
Phase 5 Sweep | Checksum: 1f68347be
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:51 ; elapsed = 00:01:02 . Memory (MB): peak = 4741.902 ; gain = 483.871
|
|||
|
|
Sweep | Checksum: 1f68347be
|
|||
|
|
INFO: [Opt 31-389] Phase Sweep created 1 cells and removed 1122 cells
|
|||
|
|
INFO: [Opt 31-1021] In phase Sweep, 4706 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
|
|||
|
|
|
|||
|
|
Phase 6 BUFG optimization
|
|||
|
|
INFO: [Opt 31-1077] Phase BUFG optimization inserted 0 global clock buffer(s) for CLOCK_LOW_FANOUT.
|
|||
|
|
INFO: [Opt 31-129] Inserted BUFG to drive high-fanout reset|set|enable net. BUFG cell: design_1_i/proc_sys_reset_0/U0/peripheral_aresetn[0]_BUFG_inst, Net: design_1_i/proc_sys_reset_0/U0/peripheral_aresetn[0]
|
|||
|
|
Phase 6 BUFG optimization | Checksum: 28ffe0b34
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:55 ; elapsed = 00:01:04 . Memory (MB): peak = 4741.902 ; gain = 483.871
|
|||
|
|
BUFG optimization | Checksum: 28ffe0b34
|
|||
|
|
INFO: [Opt 31-662] Phase BUFG optimization created 2 cells of which 1 are BUFGs and removed 0 cells.
|
|||
|
|
|
|||
|
|
Phase 7 Shift Register Optimization
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][100]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][101]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][102]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][103]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][104]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][105]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][106]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][107]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][108]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][109]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][110]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][111]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][112]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][113]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][114]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][115]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][116]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][117]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][118]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][119]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][120]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][121]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][122]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][123]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][124]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][125]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][126]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][127]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][128]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][129]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][130]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][131]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][132]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][133]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][134]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][135]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][136]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][137]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][138]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][139]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][140]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][141]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][142]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][143]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][144]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][145]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][146]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][147]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][148]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][149]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][150]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][151]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][152]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][153]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][154]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][155]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][156]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][157]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][158]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][159]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][160]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][161]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][162]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][163]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][164]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][165]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][166]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][167]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][168]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][169]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][170]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][171]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][172]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][173]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][174]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][175]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][176]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][177]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][178]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][179]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][180]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][181]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][182]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][183]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][184]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][185]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][186]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][187]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][188]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][189]_srl32 due to none static srl address bits
|
|||
|
|
WARNING: [Opt 31-1131] Can not pull register out from design_1_i/ddr4_0/inst/u_ddr_axi/axi_r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 due to none static srl address bits
|
|||
|
|
INFO: [Common 17-14] Message 'Opt 31-1131' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|||
|
|
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
|
|||
|
|
Phase 7 Shift Register Optimization | Checksum: 28ffe0b34
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:55 ; elapsed = 00:01:04 . Memory (MB): peak = 4741.902 ; gain = 483.871
|
|||
|
|
Shift Register Optimization | Checksum: 28ffe0b34
|
|||
|
|
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
|
|||
|
|
|
|||
|
|
Phase 8 Post Processing Netlist
|
|||
|
|
INFO: [Opt 31-1566] Pulled 2 inverters resulting in an inversion of 4 pins
|
|||
|
|
Phase 8 Post Processing Netlist | Checksum: 1b6c17bbe
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:56 ; elapsed = 00:01:05 . Memory (MB): peak = 4741.902 ; gain = 483.871
|
|||
|
|
Post Processing Netlist | Checksum: 1b6c17bbe
|
|||
|
|
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 2 cells
|
|||
|
|
INFO: [Opt 31-1021] In phase Post Processing Netlist, 299 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
|
|||
|
|
|
|||
|
|
Phase 9 Finalization
|
|||
|
|
|
|||
|
|
Phase 9.1 Finalizing Design Cores and Updating Shapes
|
|||
|
|
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 164d0fdd9
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:07 ; elapsed = 00:01:16 . Memory (MB): peak = 4741.902 ; gain = 483.871
|
|||
|
|
|
|||
|
|
Phase 9.2 Verifying Netlist Connectivity
|
|||
|
|
|
|||
|
|
Starting Connectivity Check Task
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.376 . Memory (MB): peak = 4741.902 ; gain = 0.000
|
|||
|
|
Phase 9.2 Verifying Netlist Connectivity | Checksum: 164d0fdd9
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:07 ; elapsed = 00:01:16 . Memory (MB): peak = 4741.902 ; gain = 483.871
|
|||
|
|
Phase 9 Finalization | Checksum: 164d0fdd9
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:07 ; elapsed = 00:01:16 . Memory (MB): peak = 4741.902 ; gain = 483.871
|
|||
|
|
Opt_design Change Summary
|
|||
|
|
=========================
|
|||
|
|
|
|||
|
|
|
|||
|
|
-------------------------------------------------------------------------------------------------------------------------
|
|||
|
|
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
|
|||
|
|
-------------------------------------------------------------------------------------------------------------------------
|
|||
|
|
| Retarget | 161 | 539 | 225 |
|
|||
|
|
| Constant propagation | 1461 | 4377 | 260 |
|
|||
|
|
| Sweep | 1 | 1122 | 4706 |
|
|||
|
|
| BUFG optimization | 2 | 0 | 0 |
|
|||
|
|
| Shift Register Optimization | 0 | 0 | 0 |
|
|||
|
|
| Post Processing Netlist | 0 | 2 | 299 |
|
|||
|
|
-------------------------------------------------------------------------------------------------------------------------
|
|||
|
|
|
|||
|
|
|
|||
|
|
Ending Logic Optimization Task | Checksum: 164d0fdd9
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:07 ; elapsed = 00:01:16 . Memory (MB): peak = 4741.902 ; gain = 483.871
|
|||
|
|
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
|
|||
|
|
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.162 . Memory (MB): peak = 4741.902 ; gain = 0.000
|
|||
|
|
|
|||
|
|
Starting Power Optimization Task
|
|||
|
|
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
|
|||
|
|
INFO: [Power 33-23] Power model is not available for xiphy_riu_or
|
|||
|
|
INFO: [Power 33-23] Power model is not available for genVref.u_hpio_vref
|
|||
|
|
INFO: [Pwropt 34-9] Applying IDT optimizations ...
|
|||
|
|
INFO: [Pwropt 34-10] Applying ODC optimizations ...
|
|||
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|||
|
|
Running Vector-less Activity Propagation...
|
|||
|
|
|
|||
|
|
Finished Running Vector-less Activity Propagation
|
|||
|
|
|
|||
|
|
|
|||
|
|
Starting PowerOpt Patch Enables Task
|
|||
|
|
INFO: [Pwropt 34-162] WRITE_MODE attribute of 41 BRAM(s) out of a total of 570 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
|
|||
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|||
|
|
INFO: [Pwropt 34-201] Structural ODC has moved 213 WE to EN ports
|
|||
|
|
Number of BRAM Ports augmented: 46 newly gated: 367 Total Ports: 1140
|
|||
|
|
Ending PowerOpt Patch Enables Task | Checksum: 2397d22e3
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 6836.648 ; gain = 0.000
|
|||
|
|
Ending Power Optimization Task | Checksum: 2397d22e3
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:02:31 ; elapsed = 00:01:45 . Memory (MB): peak = 6836.648 ; gain = 2094.746
|
|||
|
|
|
|||
|
|
Starting Final Cleanup Task
|
|||
|
|
|
|||
|
|
Starting Logic Optimization Task
|
|||
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|||
|
|
INFO: [Opt 31-1077] Phase BUFG optimization inserted 0 global clock buffer(s) for CLOCK_LOW_FANOUT.
|
|||
|
|
Ending Logic Optimization Task | Checksum: 16fdc046e
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:26 ; elapsed = 00:00:19 . Memory (MB): peak = 6836.648 ; gain = 0.000
|
|||
|
|
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
|
|||
|
|
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.160 . Memory (MB): peak = 6836.648 ; gain = 0.000
|
|||
|
|
Ending Final Cleanup Task | Checksum: 16fdc046e
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:28 ; elapsed = 00:00:21 . Memory (MB): peak = 6836.648 ; gain = 0.000
|
|||
|
|
|
|||
|
|
Starting Netlist Obfuscation Task
|
|||
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.057 . Memory (MB): peak = 6836.648 ; gain = 0.000
|
|||
|
|
Ending Netlist Obfuscation Task | Checksum: 16fdc046e
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.081 . Memory (MB): peak = 6836.648 ; gain = 0.000
|
|||
|
|
INFO: [Common 17-83] Releasing license: Implementation
|
|||
|
|
79 Infos, 278 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
|||
|
|
opt_design completed successfully
|
|||
|
|
opt_design: Time (s): cpu = 00:04:21 ; elapsed = 00:03:34 . Memory (MB): peak = 6836.648 ; gain = 2830.773
|
|||
|
|
INFO: [runtcl-4] Executing : report_drc -file design_1_wrapper_drc_opted.rpt -pb design_1_wrapper_drc_opted.pb -rpx design_1_wrapper_drc_opted.rpx
|
|||
|
|
Command: report_drc -file design_1_wrapper_drc_opted.rpt -pb design_1_wrapper_drc_opted.pb -rpx design_1_wrapper_drc_opted.rpx
|
|||
|
|
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
|||
|
|
INFO: [DRC 23-27] Running DRC with 2 threads
|
|||
|
|
INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.runs/impl_2/design_1_wrapper_drc_opted.rpt.
|
|||
|
|
report_drc completed successfully
|
|||
|
|
report_drc: Time (s): cpu = 00:00:15 ; elapsed = 00:00:09 . Memory (MB): peak = 6836.648 ; gain = 0.000
|
|||
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|||
|
|
INFO: [Timing 38-480] Writing timing data to binary archive.
|
|||
|
|
Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.042 . Memory (MB): peak = 6836.648 ; gain = 0.000
|
|||
|
|
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6836.648 ; gain = 0.000
|
|||
|
|
Writing XDEF routing.
|
|||
|
|
Writing XDEF routing logical nets.
|
|||
|
|
Writing XDEF routing special nets.
|
|||
|
|
Wrote RouteStorage: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.429 . Memory (MB): peak = 6836.648 ; gain = 0.000
|
|||
|
|
Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 6836.648 ; gain = 0.000
|
|||
|
|
Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 6836.648 ; gain = 0.000
|
|||
|
|
Write Physdb Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.500 . Memory (MB): peak = 6836.648 ; gain = 0.000
|
|||
|
|
Write ShapeDB Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.509 . Memory (MB): peak = 6836.648 ; gain = 0.000
|
|||
|
|
INFO: [Common 17-1381] The checkpoint 'C:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.runs/impl_2/design_1_wrapper_opt.dcp' has been generated.
|
|||
|
|
write_checkpoint: Time (s): cpu = 00:00:40 ; elapsed = 00:00:29 . Memory (MB): peak = 6836.648 ; gain = 0.000
|
|||
|
|
INFO: [Chipscope 16-240] Debug cores have already been implemented
|
|||
|
|
Command: place_design
|
|||
|
|
Attempting to get a license for feature 'Implementation' and/or device 'xcku5p'
|
|||
|
|
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xcku5p'
|
|||
|
|
INFO: [Common 17-83] Releasing license: Implementation
|
|||
|
|
INFO: [DRC 23-27] Running DRC with 2 threads
|
|||
|
|
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
|||
|
|
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
|||
|
|
Running DRC as a precondition to command place_design
|
|||
|
|
INFO: [DRC 23-27] Running DRC with 2 threads
|
|||
|
|
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
|||
|
|
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
|||
|
|
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
|
|||
|
|
|
|||
|
|
Starting Placer Task
|
|||
|
|
|
|||
|
|
Phase 1 Placer Initialization
|
|||
|
|
|
|||
|
|
Phase 1.1 Placer Initialization Netlist Sorting
|
|||
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 6836.648 ; gain = 0.000
|
|||
|
|
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 118158a1d
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.111 . Memory (MB): peak = 6836.648 ; gain = 0.000
|
|||
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.061 . Memory (MB): peak = 6836.648 ; gain = 0.000
|
|||
|
|
|
|||
|
|
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
|
|||
|
|
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1240516b6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:24 ; elapsed = 00:00:22 . Memory (MB): peak = 6836.648 ; gain = 0.000
|
|||
|
|
|
|||
|
|
Phase 1.3 Build Placer Netlist Model
|
|||
|
|
Phase 1.3 Build Placer Netlist Model | Checksum: 197faa27e
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:17 ; elapsed = 00:01:02 . Memory (MB): peak = 7074.906 ; gain = 238.258
|
|||
|
|
|
|||
|
|
Phase 1.4 Constrain Clocks/Macros
|
|||
|
|
MIG CONSTR ADDED 1
|
|||
|
|
MIG Constraint : added 1
|
|||
|
|
Phase 1.4 Constrain Clocks/Macros | Checksum: 197faa27e
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:17 ; elapsed = 00:01:02 . Memory (MB): peak = 7074.906 ; gain = 238.258
|
|||
|
|
Phase 1 Placer Initialization | Checksum: 197faa27e
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:17 ; elapsed = 00:01:03 . Memory (MB): peak = 7074.906 ; gain = 238.258
|
|||
|
|
|
|||
|
|
Phase 2 Global Placement
|
|||
|
|
|
|||
|
|
Phase 2.1 Floorplanning
|
|||
|
|
|
|||
|
|
Phase 2.1.1 Partition Driven Placement
|
|||
|
|
|
|||
|
|
Phase 2.1.1.1 PBP: Partition Driven Placement
|
|||
|
|
Phase 2.1.1.1 PBP: Partition Driven Placement | Checksum: 1fb8f86c1
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:03:36 ; elapsed = 00:02:31 . Memory (MB): peak = 7074.906 ; gain = 238.258
|
|||
|
|
|
|||
|
|
Phase 2.1.1.2 PBP: Clock Region Placement
|
|||
|
|
INFO: [Place 30-3162] Check ILP status : ILP-based clock placer completed successfully.
|
|||
|
|
Phase 2.1.1.2 PBP: Clock Region Placement | Checksum: 1cb682591
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:03:41 ; elapsed = 00:02:35 . Memory (MB): peak = 7074.906 ; gain = 238.258
|
|||
|
|
|
|||
|
|
Phase 2.1.1.3 PBP: Discrete Incremental
|
|||
|
|
Phase 2.1.1.3 PBP: Discrete Incremental | Checksum: 1bf0845dc
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:03:41 ; elapsed = 00:02:36 . Memory (MB): peak = 7074.906 ; gain = 238.258
|
|||
|
|
|
|||
|
|
Phase 2.1.1.4 PBP: Compute Congestion
|
|||
|
|
Phase 2.1.1.4 PBP: Compute Congestion | Checksum: 1bf0845dc
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:03:58 ; elapsed = 00:02:45 . Memory (MB): peak = 7074.906 ; gain = 238.258
|
|||
|
|
|
|||
|
|
Phase 2.1.1.5 PBP: Macro Placement
|
|||
|
|
Phase 2.1.1.5 PBP: Macro Placement | Checksum: 12a877d22
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:04:00 ; elapsed = 00:02:47 . Memory (MB): peak = 7074.906 ; gain = 238.258
|
|||
|
|
|
|||
|
|
Phase 2.1.1.6 PBP: UpdateTiming
|
|||
|
|
Phase 2.1.1.6 PBP: UpdateTiming | Checksum: 15a53a0e8
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:04:13 ; elapsed = 00:02:56 . Memory (MB): peak = 7074.906 ; gain = 238.258
|
|||
|
|
|
|||
|
|
Phase 2.1.1.7 PBP: Add part constraints
|
|||
|
|
Phase 2.1.1.7 PBP: Add part constraints | Checksum: 15a53a0e8
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:04:13 ; elapsed = 00:02:56 . Memory (MB): peak = 7074.906 ; gain = 238.258
|
|||
|
|
Phase 2.1.1 Partition Driven Placement | Checksum: 15a53a0e8
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:04:13 ; elapsed = 00:02:56 . Memory (MB): peak = 7074.906 ; gain = 238.258
|
|||
|
|
Phase 2.1 Floorplanning | Checksum: b5c200ce
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:04:14 ; elapsed = 00:02:56 . Memory (MB): peak = 7074.906 ; gain = 238.258
|
|||
|
|
|
|||
|
|
Phase 2.2 Update Timing before SLR Path Opt
|
|||
|
|
Phase 2.2 Update Timing before SLR Path Opt | Checksum: b5c200ce
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:04:14 ; elapsed = 00:02:57 . Memory (MB): peak = 7074.906 ; gain = 238.258
|
|||
|
|
|
|||
|
|
Phase 2.3 Post-Processing in Floorplanning
|
|||
|
|
Phase 2.3 Post-Processing in Floorplanning | Checksum: b5c200ce
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:04:15 ; elapsed = 00:02:57 . Memory (MB): peak = 7074.906 ; gain = 238.258
|
|||
|
|
|
|||
|
|
Phase 2.4 Global Placement Core
|
|||
|
|
|
|||
|
|
Phase 2.4.1 UpdateTiming Before Physical Synthesis
|
|||
|
|
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: c0065303
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:07:53 ; elapsed = 00:05:17 . Memory (MB): peak = 7271.355 ; gain = 434.707
|
|||
|
|
|
|||
|
|
Phase 2.4.2 Physical Synthesis In Placer
|
|||
|
|
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 11432 LUT instances to create LUTNM shape
|
|||
|
|
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
|
|||
|
|
INFO: [Physopt 32-1138] End 1 Pass. Optimized 4695 nets or LUTs. Breaked 0 LUT, combined 4695 existing LUTs and moved 0 existing LUT
|
|||
|
|
Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.057 . Memory (MB): peak = 7271.355 ; gain = 0.000
|
|||
|
|
INFO: [Physopt 32-712] Optimization is not feasible on net flaw_image_bytes[31] due to MARK_DEBUG attribute.
|
|||
|
|
INFO: [Physopt 32-1030] Pass 1. Identified 135 candidate driver sets for equivalent driver rewiring.
|
|||
|
|
INFO: [Physopt 32-661] Optimized 101 nets. Re-placed 387 instances.
|
|||
|
|
INFO: [Physopt 32-775] End 1 Pass. Optimized 101 nets or cells. Created 0 new cell, deleted 7 existing cells and moved 387 existing cells
|
|||
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.787 . Memory (MB): peak = 7271.355 ; gain = 0.000
|
|||
|
|
INFO: [Physopt 32-1132] Very high fanout net 'design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l0/u_level/u_v_stage/out_fifo_bank0_q_reg_0_7_0_1_i_6__1_n_0' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 1024 to 65 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 65.
|
|||
|
|
INFO: [Physopt 32-1132] Very high fanout net 'design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l0/u_level/u_v_stage/out_fifo_bank0_q_reg_0_7_0_1_i_7__1_n_0' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 1024 to 65 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 65.
|
|||
|
|
INFO: [Physopt 32-1132] Very high fanout net 'design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l0/u_level/u_v_stage/out_fifo_bank0_q_reg_0_7_0_1_i_8__1_n_0' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 1024 to 65 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 65.
|
|||
|
|
INFO: [Physopt 32-1132] Very high fanout net 'design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l0/u_level/u_v_stage/out_fifo_bank0_q_reg_0_7_32_33_i_3__1_n_0' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 2048 to 129 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 129.
|
|||
|
|
INFO: [Physopt 32-1132] Very high fanout net 'design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l0/u_level/u_v_stage/out_fifo_bank0_q_reg_0_7_32_33_i_4__1_n_0' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 2048 to 129 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 129.
|
|||
|
|
INFO: [Physopt 32-1132] Very high fanout net 'design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l0/u_level/u_v_stage/out_fifo_bank0_q_reg_0_7_32_33_i_5_n_0' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 2048 to 129 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 129.
|
|||
|
|
INFO: [Physopt 32-1132] Very high fanout net 'design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l1/u_v_stage/p_2_in[2]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 2048 to 129 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 129.
|
|||
|
|
INFO: [Physopt 32-1132] Very high fanout net 'design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l1/i___829_rep_n_0' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 1024 to 65 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 65.
|
|||
|
|
INFO: [Physopt 32-1132] Very high fanout net 'design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l1/u_v_stage/p_2_in[1]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 2048 to 129 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 129.
|
|||
|
|
INFO: [Physopt 32-1132] Very high fanout net 'design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l1/i___831_rep_n_0' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 1024 to 65 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 65.
|
|||
|
|
INFO: [Physopt 32-1132] Very high fanout net 'design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l1/u_level/u_v_stage/p_2_in_0[0]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 2048 to 129 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 129.
|
|||
|
|
INFO: [Physopt 32-1132] Very high fanout net 'design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l1/u_level/u_v_stage/out_fifo_bank0_q_reg_0_7_64_65_i_6_n_0' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 1024 to 65 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 65.
|
|||
|
|
INFO: [Physopt 32-1132] Very high fanout net 'design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l2/u_v_stage/p_2_in[2]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 2048 to 129 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 129.
|
|||
|
|
INFO: [Physopt 32-1132] Very high fanout net 'design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l2/u_v_stage/p_2_in[1]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 2048 to 129 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 129.
|
|||
|
|
INFO: [Physopt 32-1132] Very high fanout net 'design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l2/u_v_stage/p_2_in[0]' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 2048 to 129 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 129.
|
|||
|
|
INFO: [Physopt 32-1132] Very high fanout net 'design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l2/u_v_stage/out_fifo_bank0_q_reg_0_7_64_65_i_6__1_n_0' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 1024 to 65 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 65.
|
|||
|
|
INFO: [Physopt 32-1132] Very high fanout net 'design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l2/u_v_stage/out_fifo_bank0_q_reg_0_7_64_65_i_7__1_n_0' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 1024 to 65 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 65.
|
|||
|
|
INFO: [Physopt 32-1132] Very high fanout net 'design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l2/u_v_stage/out_fifo_bank0_q_reg_0_7_64_65_i_8__0_n_0' is not considered as a candidate in VHFN optimzation. The fanout considered for this optimization is changed from 1024 to 65 due to a timing constraint that prevent optimization on all of the loads. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 65.
|
|||
|
|
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
|
|||
|
|
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
|
|||
|
|
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed.
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
|
|||
|
|
INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
|
|||
|
|
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
|
|||
|
|
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
|||
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.055 . Memory (MB): peak = 7271.355 ; gain = 0.000
|
|||
|
|
|
|||
|
|
Summary of Physical Synthesis Optimizations
|
|||
|
|
============================================
|
|||
|
|
|
|||
|
|
|
|||
|
|
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|
|||
|
|
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
|
|||
|
|
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|
|||
|
|
| LUT Combining | 0 | 4695 | 4695 | 0 | 1 | 00:00:04 |
|
|||
|
|
| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
|||
|
|
| Equivalent Driver Rewiring | 0 | 7 | 101 | 1 | 1 | 00:00:06 |
|
|||
|
|
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:01 |
|
|||
|
|
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
|||
|
|
| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
|||
|
|
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
|||
|
|
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
|||
|
|
| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
|||
|
|
| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
|||
|
|
| Total | 0 | 4702 | 4796 | 1 | 5 | 00:00:11 |
|
|||
|
|
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|
|||
|
|
|
|||
|
|
|
|||
|
|
Phase 2.4.2 Physical Synthesis In Placer | Checksum: cb37348c
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:08:18 ; elapsed = 00:05:39 . Memory (MB): peak = 7271.355 ; gain = 434.707
|
|||
|
|
Phase 2.4 Global Placement Core | Checksum: 12c18ad18
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:09:08 ; elapsed = 00:06:11 . Memory (MB): peak = 7271.355 ; gain = 434.707
|
|||
|
|
Phase 2 Global Placement | Checksum: 12c18ad18
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:09:08 ; elapsed = 00:06:11 . Memory (MB): peak = 7271.355 ; gain = 434.707
|
|||
|
|
|
|||
|
|
Phase 3 Detail Placement
|
|||
|
|
|
|||
|
|
Phase 3.1 Commit Multi Column Macros
|
|||
|
|
Phase 3.1 Commit Multi Column Macros | Checksum: 1e1d5d49c
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:09:36 ; elapsed = 00:06:27 . Memory (MB): peak = 7271.355 ; gain = 434.707
|
|||
|
|
|
|||
|
|
Phase 3.2 Commit Most Macros & LUTRAMs
|
|||
|
|
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 171a82754
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:09:50 ; elapsed = 00:06:39 . Memory (MB): peak = 7271.355 ; gain = 434.707
|
|||
|
|
|
|||
|
|
Phase 3.3 Small Shape DP
|
|||
|
|
|
|||
|
|
Phase 3.3.1 Small Shape Clustering
|
|||
|
|
Phase 3.3.1 Small Shape Clustering | Checksum: 1a5bc2b51
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:10:29 ; elapsed = 00:07:02 . Memory (MB): peak = 7271.355 ; gain = 434.707
|
|||
|
|
|
|||
|
|
Phase 3.3.2 Slice Area Swap
|
|||
|
|
|
|||
|
|
Phase 3.3.2.1 Slice Area Swap Initial
|
|||
|
|
Phase 3.3.2.1 Slice Area Swap Initial | Checksum: 15ea95659
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:10:57 ; elapsed = 00:07:25 . Memory (MB): peak = 7271.355 ; gain = 434.707
|
|||
|
|
Phase 3.3.2 Slice Area Swap | Checksum: 15ea95659
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:10:57 ; elapsed = 00:07:25 . Memory (MB): peak = 7271.355 ; gain = 434.707
|
|||
|
|
Phase 3.3 Small Shape DP | Checksum: 24569a89a
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:12:05 ; elapsed = 00:08:02 . Memory (MB): peak = 7271.355 ; gain = 434.707
|
|||
|
|
|
|||
|
|
Phase 3.4 Re-assign LUT pins
|
|||
|
|
Phase 3.4 Re-assign LUT pins | Checksum: 1b04230f8
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:12:12 ; elapsed = 00:08:10 . Memory (MB): peak = 7271.355 ; gain = 434.707
|
|||
|
|
|
|||
|
|
Phase 3.5 Pipeline Register Optimization
|
|||
|
|
Phase 3.5 Pipeline Register Optimization | Checksum: 1ff5f3ada
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:12:14 ; elapsed = 00:08:11 . Memory (MB): peak = 7271.355 ; gain = 434.707
|
|||
|
|
Phase 3 Detail Placement | Checksum: 1ff5f3ada
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:12:15 ; elapsed = 00:08:12 . Memory (MB): peak = 7271.355 ; gain = 434.707
|
|||
|
|
|
|||
|
|
Phase 4 Post Placement Optimization and Clean-Up
|
|||
|
|
|
|||
|
|
Phase 4.1 Post Commit Optimization
|
|||
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|||
|
|
|
|||
|
|
Phase 4.1.1 Post Placement Optimization
|
|||
|
|
Post Placement Optimization Initialization | Checksum: 1e4491bc6
|
|||
|
|
|
|||
|
|
Phase 4.1.1.1 BUFG Insertion
|
|||
|
|
|
|||
|
|
Starting Physical Synthesis Task
|
|||
|
|
|
|||
|
|
Phase 1 Physical Synthesis Initialization
|
|||
|
|
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 2 CPUs
|
|||
|
|
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=1.612 | TNS=0.000 |
|
|||
|
|
Phase 1 Physical Synthesis Initialization | Checksum: 1c9f00ee1
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 7708.016 ; gain = 245.625
|
|||
|
|
INFO: [Place 46-35] Processed net design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[0].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_scan/rst_n_0[0], inserted BUFG to drive 1351 loads.
|
|||
|
|
INFO: [Place 46-35] Processed net design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[10].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_scan/rst_n_0[0], inserted BUFG to drive 1351 loads.
|
|||
|
|
INFO: [Place 46-35] Processed net design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[11].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_scan/rst_n_0[0], inserted BUFG to drive 1351 loads.
|
|||
|
|
INFO: [Place 46-35] Processed net design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[12].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_scan/rst_n_0[0], inserted BUFG to drive 1351 loads.
|
|||
|
|
INFO: [Place 46-35] Processed net design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[13].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_scan/rst_n_0[0], inserted BUFG to drive 1351 loads.
|
|||
|
|
INFO: [Place 46-35] Processed net design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[14].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_scan/rst_n_0[0], inserted BUFG to drive 1351 loads.
|
|||
|
|
INFO: [Place 46-35] Processed net design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[15].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_scan/rst_n_0[0], inserted BUFG to drive 1351 loads.
|
|||
|
|
INFO: [Place 46-35] Processed net design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[16].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_scan/rst_n_0[0], inserted BUFG to drive 1351 loads.
|
|||
|
|
INFO: [Place 46-35] Processed net design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[17].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_scan/rst_n_0[0], inserted BUFG to drive 1351 loads.
|
|||
|
|
INFO: [Place 46-35] Processed net design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[18].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_scan/rst_n_0[0], inserted BUFG to drive 1351 loads.
|
|||
|
|
INFO: [Place 46-35] Processed net design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[19].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_scan/rst_n_0[0], inserted BUFG to drive 1351 loads.
|
|||
|
|
INFO: [Place 46-35] Processed net design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[1].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_scan/rst_n_0[0], inserted BUFG to drive 1351 loads.
|
|||
|
|
INFO: [Place 46-35] Processed net design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[20].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_scan/rst_n_0[0], inserted BUFG to drive 1351 loads.
|
|||
|
|
INFO: [Place 46-35] Processed net design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[21].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_scan/rst_n_0[0], inserted BUFG to drive 1351 loads.
|
|||
|
|
INFO: [Place 46-35] Processed net design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[22].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_scan/rst_n_0[0], inserted BUFG to drive 1351 loads.
|
|||
|
|
INFO: [Place 46-35] Processed net design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[23].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_scan/rst_n_0[0], inserted BUFG to drive 1351 loads.
|
|||
|
|
INFO: [Place 46-35] Processed net design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[2].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_scan/rst_n_0[0], inserted BUFG to drive 1351 loads.
|
|||
|
|
INFO: [Place 46-35] Processed net design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[3].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_scan/rst_n_0[0], inserted BUFG to drive 1351 loads.
|
|||
|
|
INFO: [Place 46-35] Processed net design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[4].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_scan/rst_n_0[0], inserted BUFG to drive 1351 loads.
|
|||
|
|
INFO: [Place 46-35] Processed net design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[5].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_scan/rst_n_0[0], inserted BUFG to drive 1351 loads.
|
|||
|
|
INFO: [Place 46-35] Processed net design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[6].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_scan/rst_n_0[0], inserted BUFG to drive 1351 loads.
|
|||
|
|
INFO: [Place 46-35] Processed net design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[7].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_scan/rst_n_0[0], inserted BUFG to drive 1351 loads.
|
|||
|
|
INFO: [Place 46-35] Processed net design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[8].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_scan/rst_n_0[0], inserted BUFG to drive 1351 loads.
|
|||
|
|
INFO: [Place 46-35] Processed net design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[9].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_scan/rst_n_0[0], inserted BUFG to drive 1351 loads.
|
|||
|
|
INFO: [Place 46-56] BUFG insertion identified 24 candidate nets. Inserted BUFG: 24, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
|
|||
|
|
Ending Physical Synthesis Task | Checksum: 109e8f49c
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:00:19 ; elapsed = 00:00:16 . Memory (MB): peak = 7747.363 ; gain = 284.973
|
|||
|
|
Phase 4.1.1.1 BUFG Insertion | Checksum: 121964667
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:13:55 ; elapsed = 00:09:23 . Memory (MB): peak = 7747.363 ; gain = 910.715
|
|||
|
|
|
|||
|
|
Phase 4.1.1.2 Post Placement Timing Optimization
|
|||
|
|
INFO: [Place 30-746] Post Placement Timing Summary WNS=1.612. For the most accurate timing information please run report_timing.
|
|||
|
|
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1e4caf046
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:13:57 ; elapsed = 00:09:25 . Memory (MB): peak = 7747.363 ; gain = 910.715
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:13:57 ; elapsed = 00:09:25 . Memory (MB): peak = 7747.363 ; gain = 910.715
|
|||
|
|
Phase 4.1 Post Commit Optimization | Checksum: 1e4caf046
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:13:58 ; elapsed = 00:09:26 . Memory (MB): peak = 7747.363 ; gain = 910.715
|
|||
|
|
Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.679 . Memory (MB): peak = 7807.598 ; gain = 0.000
|
|||
|
|
|
|||
|
|
Phase 4.2 Post Placement Cleanup
|
|||
|
|
Phase 4.2 Post Placement Cleanup | Checksum: 230370380
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:14:21 ; elapsed = 00:09:41 . Memory (MB): peak = 7807.598 ; gain = 970.949
|
|||
|
|
|
|||
|
|
Phase 4.3 Placer Reporting
|
|||
|
|
|
|||
|
|
Phase 4.3.1 Print Estimated Congestion
|
|||
|
|
INFO: [Place 30-612] Post-Placement Estimated Congestion
|
|||
|
|
________________________________________________________________________
|
|||
|
|
| | Global Congestion | Long Congestion | Short Congestion |
|
|||
|
|
| Direction | Region Size | Region Size | Region Size |
|
|||
|
|
|___________|___________________|___________________|___________________|
|
|||
|
|
| North| 1x1| 1x1| 4x4|
|
|||
|
|
|___________|___________________|___________________|___________________|
|
|||
|
|
| South| 1x1| 1x1| 2x2|
|
|||
|
|
|___________|___________________|___________________|___________________|
|
|||
|
|
| East| 1x1| 1x1| 4x4|
|
|||
|
|
|___________|___________________|___________________|___________________|
|
|||
|
|
| West| 1x1| 1x1| 4x4|
|
|||
|
|
|___________|___________________|___________________|___________________|
|
|||
|
|
|
|||
|
|
Phase 4.3.1 Print Estimated Congestion | Checksum: 230370380
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:14:22 ; elapsed = 00:09:42 . Memory (MB): peak = 7807.598 ; gain = 970.949
|
|||
|
|
Phase 4.3 Placer Reporting | Checksum: 230370380
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:14:23 ; elapsed = 00:09:43 . Memory (MB): peak = 7807.598 ; gain = 970.949
|
|||
|
|
|
|||
|
|
Phase 4.4 Final Placement Cleanup
|
|||
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.062 . Memory (MB): peak = 7807.598 ; gain = 0.000
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:14:23 ; elapsed = 00:09:43 . Memory (MB): peak = 7807.598 ; gain = 970.949
|
|||
|
|
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2aabef754
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:14:24 ; elapsed = 00:09:44 . Memory (MB): peak = 7807.598 ; gain = 970.949
|
|||
|
|
Ending Placer Task | Checksum: 1cad1057f
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:14:25 ; elapsed = 00:09:45 . Memory (MB): peak = 7807.598 ; gain = 970.949
|
|||
|
|
162 Infos, 278 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
|||
|
|
place_design completed successfully
|
|||
|
|
place_design: Time (s): cpu = 00:14:34 ; elapsed = 00:09:51 . Memory (MB): peak = 7807.598 ; gain = 970.949
|
|||
|
|
INFO: [runtcl-4] Executing : report_io -file design_1_wrapper_io_placed.rpt
|
|||
|
|
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.113 . Memory (MB): peak = 7807.598 ; gain = 0.000
|
|||
|
|
INFO: [runtcl-4] Executing : report_utilization -file design_1_wrapper_utilization_placed.rpt -pb design_1_wrapper_utilization_placed.pb
|
|||
|
|
INFO: [runtcl-4] Executing : report_control_sets -verbose -file design_1_wrapper_control_sets_placed.rpt
|
|||
|
|
report_control_sets: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.513 . Memory (MB): peak = 7807.598 ; gain = 0.000
|
|||
|
|
INFO: [Timing 38-480] Writing timing data to binary archive.
|
|||
|
|
Write ShapeDB Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.739 . Memory (MB): peak = 7807.598 ; gain = 0.000
|
|||
|
|
Wrote PlaceDB: Time (s): cpu = 00:00:30 ; elapsed = 00:00:10 . Memory (MB): peak = 7807.598 ; gain = 0.000
|
|||
|
|
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 7807.598 ; gain = 0.000
|
|||
|
|
Writing XDEF routing.
|
|||
|
|
Writing XDEF routing logical nets.
|
|||
|
|
Writing XDEF routing special nets.
|
|||
|
|
Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.365 . Memory (MB): peak = 7807.598 ; gain = 0.000
|
|||
|
|
Wrote Netlist Cache: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.238 . Memory (MB): peak = 7807.598 ; gain = 0.000
|
|||
|
|
Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 7807.598 ; gain = 0.000
|
|||
|
|
Write Physdb Complete: Time (s): cpu = 00:00:31 ; elapsed = 00:00:11 . Memory (MB): peak = 7807.598 ; gain = 0.000
|
|||
|
|
report_design_analysis: Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 7807.598 ; gain = 0.000
|
|||
|
|
INFO: [Common 17-1381] The checkpoint 'C:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.runs/impl_2/design_1_wrapper_placed.dcp' has been generated.
|
|||
|
|
write_checkpoint: Time (s): cpu = 00:01:02 ; elapsed = 00:00:42 . Memory (MB): peak = 7807.598 ; gain = 0.000
|
|||
|
|
Command: phys_opt_design
|
|||
|
|
Attempting to get a license for feature 'Implementation' and/or device 'xcku5p'
|
|||
|
|
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xcku5p'
|
|||
|
|
|
|||
|
|
Starting Initial Update Timing Task
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:01 ; elapsed = 00:00:36 . Memory (MB): peak = 8171.465 ; gain = 363.867
|
|||
|
|
INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations.
|
|||
|
|
INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
|
|||
|
|
INFO: [Common 17-83] Releasing license: Implementation
|
|||
|
|
171 Infos, 278 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
|||
|
|
phys_opt_design completed successfully
|
|||
|
|
phys_opt_design: Time (s): cpu = 00:01:02 ; elapsed = 00:00:37 . Memory (MB): peak = 8171.465 ; gain = 363.867
|
|||
|
|
INFO: [Timing 38-480] Writing timing data to binary archive.
|
|||
|
|
Write ShapeDB Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.715 . Memory (MB): peak = 8238.012 ; gain = 52.633
|
|||
|
|
Wrote PlaceDB: Time (s): cpu = 00:00:30 ; elapsed = 00:00:10 . Memory (MB): peak = 8242.312 ; gain = 56.934
|
|||
|
|
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 8242.312 ; gain = 0.000
|
|||
|
|
Writing XDEF routing.
|
|||
|
|
Writing XDEF routing logical nets.
|
|||
|
|
Writing XDEF routing special nets.
|
|||
|
|
Wrote RouteStorage: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.362 . Memory (MB): peak = 8242.312 ; gain = 0.000
|
|||
|
|
Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.231 . Memory (MB): peak = 8242.312 ; gain = 0.000
|
|||
|
|
Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 8242.312 ; gain = 0.000
|
|||
|
|
Write Physdb Complete: Time (s): cpu = 00:00:32 ; elapsed = 00:00:11 . Memory (MB): peak = 8242.312 ; gain = 56.934
|
|||
|
|
INFO: [Common 17-1381] The checkpoint 'C:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.runs/impl_2/design_1_wrapper_physopt.dcp' has been generated.
|
|||
|
|
write_checkpoint: Time (s): cpu = 00:00:47 ; elapsed = 00:00:28 . Memory (MB): peak = 8242.312 ; gain = 70.848
|
|||
|
|
Command: route_design
|
|||
|
|
Attempting to get a license for feature 'Implementation' and/or device 'xcku5p'
|
|||
|
|
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xcku5p'
|
|||
|
|
Running DRC as a precondition to command route_design
|
|||
|
|
INFO: [DRC 23-27] Running DRC with 2 threads
|
|||
|
|
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
|||
|
|
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
|||
|
|
|
|||
|
|
|
|||
|
|
Starting Routing Task
|
|||
|
|
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
|
|||
|
|
|
|||
|
|
Phase 1 Build RT Design
|
|||
|
|
Checksum: PlaceDB: c86b647c ConstDB: 0 ShapeSum: b6f98dc9 RouteDB: 4b6c133a
|
|||
|
|
Nodegraph reading from file. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.669 . Memory (MB): peak = 8390.047 ; gain = 0.000
|
|||
|
|
Post Restoration Checksum: NetGraph: 18d0cb62 | NumContArr: 2fbbfbad | Constraints: ece39259 | Timing: c2a8fa9d
|
|||
|
|
Phase 1 Build RT Design | Checksum: 1f8195405
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:06 ; elapsed = 00:00:30 . Memory (MB): peak = 8468.668 ; gain = 78.621
|
|||
|
|
|
|||
|
|
Phase 2 Router Initialization
|
|||
|
|
|
|||
|
|
Phase 2.1 Fix Topology Constraints
|
|||
|
|
Phase 2.1 Fix Topology Constraints | Checksum: 1f8195405
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:07 ; elapsed = 00:00:30 . Memory (MB): peak = 8468.668 ; gain = 78.621
|
|||
|
|
|
|||
|
|
Phase 2.2 Pre Route Cleanup
|
|||
|
|
Phase 2.2 Pre Route Cleanup | Checksum: 1f8195405
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:08 ; elapsed = 00:00:30 . Memory (MB): peak = 8468.668 ; gain = 78.621
|
|||
|
|
|
|||
|
|
Phase 2.3 Global Clock Net Routing
|
|||
|
|
Number of Nodes with overlaps = 0
|
|||
|
|
Phase 2.3 Global Clock Net Routing | Checksum: 29eab7a0c
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:01:23 ; elapsed = 00:00:40 . Memory (MB): peak = 8468.668 ; gain = 78.621
|
|||
|
|
|
|||
|
|
Phase 2.4 Update Timing
|
|||
|
|
Phase 2.4 Update Timing | Checksum: 2dc942ae4
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:02:19 ; elapsed = 00:01:13 . Memory (MB): peak = 8468.668 ; gain = 78.621
|
|||
|
|
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.870 | TNS=0.000 | WHS=-0.653 | THS=-89.787|
|
|||
|
|
|
|||
|
|
|
|||
|
|
Phase 2.5 Update Timing for Bus Skew
|
|||
|
|
|
|||
|
|
Phase 2.5.1 Update Timing
|
|||
|
|
Phase 2.5.1 Update Timing | Checksum: 300a3568d
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:04:13 ; elapsed = 00:02:24 . Memory (MB): peak = 8468.668 ; gain = 78.621
|
|||
|
|
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.870 | TNS=0.000 | WHS=N/A | THS=N/A |
|
|||
|
|
|
|||
|
|
Phase 2.5 Update Timing for Bus Skew | Checksum: 33b1adf8a
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:04:13 ; elapsed = 00:02:25 . Memory (MB): peak = 8468.668 ; gain = 78.621
|
|||
|
|
|
|||
|
|
Router Utilization Summary
|
|||
|
|
Global Vertical Routing Utilization = 0.00204511 %
|
|||
|
|
Global Horizontal Routing Utilization = 0.00247248 %
|
|||
|
|
Routable Net Status*
|
|||
|
|
*Does not include unroutable nets such as driverless and loadless.
|
|||
|
|
Run report_route_status for detailed report.
|
|||
|
|
Number of Failed Nets = 263091
|
|||
|
|
(Failed Nets is the sum of unrouted and partially routed nets)
|
|||
|
|
Number of Unrouted Nets = 216611
|
|||
|
|
Number of Partially Routed Nets = 46480
|
|||
|
|
Number of Node Overlaps = 8
|
|||
|
|
|
|||
|
|
Phase 2 Router Initialization | Checksum: 2c7d7878b
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:04:20 ; elapsed = 00:02:27 . Memory (MB): peak = 8468.668 ; gain = 78.621
|
|||
|
|
|
|||
|
|
Phase 3 Initial Routing
|
|||
|
|
|
|||
|
|
Phase 3.1 Global Routing
|
|||
|
|
Phase 3.1 Global Routing | Checksum: 2c7d7878b
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:04:21 ; elapsed = 00:02:27 . Memory (MB): peak = 8468.668 ; gain = 78.621
|
|||
|
|
|
|||
|
|
Phase 3.2 Initial Net Routing
|
|||
|
|
Phase 3.2 Initial Net Routing | Checksum: 25d2e35c0
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:05:21 ; elapsed = 00:02:57 . Memory (MB): peak = 8468.668 ; gain = 78.621
|
|||
|
|
Phase 3 Initial Routing | Checksum: 1e1e6e11f
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:05:25 ; elapsed = 00:02:58 . Memory (MB): peak = 8468.668 ; gain = 78.621
|
|||
|
|
|
|||
|
|
Phase 4 Rip-up And Reroute
|
|||
|
|
|
|||
|
|
Phase 4.1 Global Iteration 0
|
|||
|
|
INFO: [Route 35-443] CLB routing congestion detected. Several CLBs have high routing utilization, which can impact timing closure. Congested CLBs and Nets are dumped in: iter_4_CongestedCLBsAndNets.txt
|
|||
|
|
Number of Nodes with overlaps = 60175
|
|||
|
|
Number of Nodes with overlaps = 4652
|
|||
|
|
Number of Nodes with overlaps = 389
|
|||
|
|
Number of Nodes with overlaps = 29
|
|||
|
|
INFO: [Route 35-443] CLB routing congestion detected. Several CLBs have high routing utilization, which can impact timing closure. Congested CLBs and Nets are dumped in: iter_24_CongestedCLBsAndNets.txt
|
|||
|
|
Number of Nodes with overlaps = 8
|
|||
|
|
Number of Nodes with overlaps = 2
|
|||
|
|
Number of Nodes with overlaps = 0
|
|||
|
|
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.611 | TNS=0.000 | WHS=-0.019 | THS=-0.092 |
|
|||
|
|
|
|||
|
|
Phase 4.1 Global Iteration 0 | Checksum: 1b799399a
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:11:56 ; elapsed = 00:05:54 . Memory (MB): peak = 8794.516 ; gain = 404.469
|
|||
|
|
|
|||
|
|
Phase 4.2 Global Iteration 1
|
|||
|
|
Number of Nodes with overlaps = 2
|
|||
|
|
Number of Nodes with overlaps = 0
|
|||
|
|
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.611 | TNS=0.000 | WHS=N/A | THS=N/A |
|
|||
|
|
|
|||
|
|
Phase 4.2 Global Iteration 1 | Checksum: 266334211
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:12:24 ; elapsed = 00:06:08 . Memory (MB): peak = 8794.516 ; gain = 404.469
|
|||
|
|
Phase 4 Rip-up And Reroute | Checksum: 266334211
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:12:24 ; elapsed = 00:06:08 . Memory (MB): peak = 8794.516 ; gain = 404.469
|
|||
|
|
|
|||
|
|
Phase 5 Delay and Skew Optimization
|
|||
|
|
|
|||
|
|
Phase 5.1 Delay CleanUp
|
|||
|
|
|
|||
|
|
Phase 5.1.1 Update Timing
|
|||
|
|
Phase 5.1.1 Update Timing | Checksum: 2b3cea1b6
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:13:45 ; elapsed = 00:07:08 . Memory (MB): peak = 8794.516 ; gain = 404.469
|
|||
|
|
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.611 | TNS=0.000 | WHS=0.010 | THS=0.000 |
|
|||
|
|
|
|||
|
|
|
|||
|
|
Phase 5.1.2 Update Timing
|
|||
|
|
Phase 5.1.2 Update Timing | Checksum: 26ea54ce3
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:14:14 ; elapsed = 00:07:26 . Memory (MB): peak = 8794.516 ; gain = 404.469
|
|||
|
|
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.611 | TNS=0.000 | WHS=0.010 | THS=0.000 |
|
|||
|
|
|
|||
|
|
Phase 5.1 Delay CleanUp | Checksum: 31608e0da
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:14:15 ; elapsed = 00:07:27 . Memory (MB): peak = 8794.516 ; gain = 404.469
|
|||
|
|
|
|||
|
|
Phase 5.2 Clock Skew Optimization
|
|||
|
|
Phase 5.2 Clock Skew Optimization | Checksum: 31608e0da
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:14:16 ; elapsed = 00:07:27 . Memory (MB): peak = 8794.516 ; gain = 404.469
|
|||
|
|
Phase 5 Delay and Skew Optimization | Checksum: 31608e0da
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:14:17 ; elapsed = 00:07:27 . Memory (MB): peak = 8794.516 ; gain = 404.469
|
|||
|
|
|
|||
|
|
Phase 6 Post Hold Fix
|
|||
|
|
|
|||
|
|
Phase 6.1 Hold Fix Iter
|
|||
|
|
|
|||
|
|
Phase 6.1.1 Update Timing
|
|||
|
|
Phase 6.1.1 Update Timing | Checksum: 2355862e9
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:14:47 ; elapsed = 00:07:45 . Memory (MB): peak = 8794.516 ; gain = 404.469
|
|||
|
|
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.611 | TNS=0.000 | WHS=0.010 | THS=0.000 |
|
|||
|
|
|
|||
|
|
Phase 6.1 Hold Fix Iter | Checksum: 21f39c202
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:14:48 ; elapsed = 00:07:45 . Memory (MB): peak = 8794.516 ; gain = 404.469
|
|||
|
|
Phase 6 Post Hold Fix | Checksum: 21f39c202
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:14:49 ; elapsed = 00:07:45 . Memory (MB): peak = 8794.516 ; gain = 404.469
|
|||
|
|
|
|||
|
|
Phase 7 Route finalize
|
|||
|
|
|
|||
|
|
Router Utilization Summary
|
|||
|
|
Global Vertical Routing Utilization = 17.0965 %
|
|||
|
|
Global Horizontal Routing Utilization = 18.6309 %
|
|||
|
|
Routable Net Status*
|
|||
|
|
*Does not include unroutable nets such as driverless and loadless.
|
|||
|
|
Run report_route_status for detailed report.
|
|||
|
|
Number of Failed Nets = 0
|
|||
|
|
(Failed Nets is the sum of unrouted and partially routed nets)
|
|||
|
|
Number of Unrouted Nets = 0
|
|||
|
|
Number of Partially Routed Nets = 0
|
|||
|
|
Number of Node Overlaps = 0
|
|||
|
|
|
|||
|
|
Phase 7 Route finalize | Checksum: 21f39c202
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:14:52 ; elapsed = 00:07:46 . Memory (MB): peak = 8794.516 ; gain = 404.469
|
|||
|
|
|
|||
|
|
Phase 8 Verifying routed nets
|
|||
|
|
|
|||
|
|
Verification completed successfully
|
|||
|
|
Phase 8 Verifying routed nets | Checksum: 21f39c202
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:14:53 ; elapsed = 00:07:46 . Memory (MB): peak = 8794.516 ; gain = 404.469
|
|||
|
|
|
|||
|
|
Phase 9 Depositing Routes
|
|||
|
|
Phase 9 Depositing Routes | Checksum: 21f39c202
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:15:08 ; elapsed = 00:07:55 . Memory (MB): peak = 8794.516 ; gain = 404.469
|
|||
|
|
|
|||
|
|
Phase 10 Resolve XTalk
|
|||
|
|
Phase 10 Resolve XTalk | Checksum: 22e5c7280
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:15:10 ; elapsed = 00:07:57 . Memory (MB): peak = 8794.516 ; gain = 404.469
|
|||
|
|
|
|||
|
|
Phase 11 Post Router Timing
|
|||
|
|
|
|||
|
|
Phase 11.1 Update Timing
|
|||
|
|
Phase 11.1 Update Timing | Checksum: 2dd2566cd
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:15:40 ; elapsed = 00:08:15 . Memory (MB): peak = 8794.516 ; gain = 404.469
|
|||
|
|
INFO: [Route 35-57] Estimated Timing Summary | WNS=1.611 | TNS=0.000 | WHS=0.010 | THS=0.000 |
|
|||
|
|
|
|||
|
|
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
|
|||
|
|
Phase 11 Post Router Timing | Checksum: 2dd2566cd
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:15:41 ; elapsed = 00:08:15 . Memory (MB): peak = 8794.516 ; gain = 404.469
|
|||
|
|
INFO: [Route 35-16] Router Completed Successfully
|
|||
|
|
|
|||
|
|
Phase 12 Post-Route Event Processing
|
|||
|
|
Phase 12 Post-Route Event Processing | Checksum: 223060d8b
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:15:47 ; elapsed = 00:08:22 . Memory (MB): peak = 8794.516 ; gain = 404.469
|
|||
|
|
Ending Routing Task | Checksum: 223060d8b
|
|||
|
|
|
|||
|
|
Time (s): cpu = 00:15:52 ; elapsed = 00:08:27 . Memory (MB): peak = 8794.516 ; gain = 404.469
|
|||
|
|
|
|||
|
|
Routing Is Done.
|
|||
|
|
INFO: [Common 17-83] Releasing license: Implementation
|
|||
|
|
191 Infos, 278 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
|||
|
|
route_design completed successfully
|
|||
|
|
route_design: Time (s): cpu = 00:16:09 ; elapsed = 00:08:36 . Memory (MB): peak = 8794.516 ; gain = 552.203
|
|||
|
|
INFO: [runtcl-4] Executing : report_drc -file design_1_wrapper_drc_routed.rpt -pb design_1_wrapper_drc_routed.pb -rpx design_1_wrapper_drc_routed.rpx
|
|||
|
|
Command: report_drc -file design_1_wrapper_drc_routed.rpt -pb design_1_wrapper_drc_routed.pb -rpx design_1_wrapper_drc_routed.rpx
|
|||
|
|
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
|||
|
|
INFO: [DRC 23-27] Running DRC with 2 threads
|
|||
|
|
INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.runs/impl_2/design_1_wrapper_drc_routed.rpt.
|
|||
|
|
report_drc completed successfully
|
|||
|
|
report_drc: Time (s): cpu = 00:00:40 ; elapsed = 00:00:20 . Memory (MB): peak = 8794.516 ; gain = 0.000
|
|||
|
|
INFO: [runtcl-4] Executing : report_methodology -file design_1_wrapper_methodology_drc_routed.rpt -pb design_1_wrapper_methodology_drc_routed.pb -rpx design_1_wrapper_methodology_drc_routed.rpx
|
|||
|
|
Command: report_methodology -file design_1_wrapper_methodology_drc_routed.rpt -pb design_1_wrapper_methodology_drc_routed.pb -rpx design_1_wrapper_methodology_drc_routed.rpx
|
|||
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|||
|
|
INFO: [DRC 23-133] Running Methodology with 2 threads
|
|||
|
|
INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file C:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.runs/impl_2/design_1_wrapper_methodology_drc_routed.rpt.
|
|||
|
|
report_methodology completed successfully
|
|||
|
|
report_methodology: Time (s): cpu = 00:01:40 ; elapsed = 00:00:56 . Memory (MB): peak = 8884.836 ; gain = 90.320
|
|||
|
|
INFO: [runtcl-4] Executing : report_power -file design_1_wrapper_power_routed.rpt -pb design_1_wrapper_power_summary_routed.pb -rpx design_1_wrapper_power_routed.rpx
|
|||
|
|
Command: report_power -file design_1_wrapper_power_routed.rpt -pb design_1_wrapper_power_summary_routed.pb -rpx design_1_wrapper_power_routed.rpx
|
|||
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|||
|
|
Running Vector-less Activity Propagation...
|
|||
|
|
|
|||
|
|
Finished Running Vector-less Activity Propagation
|
|||
|
|
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
|
|||
|
|
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
|
|||
|
|
201 Infos, 279 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
|||
|
|
report_power completed successfully
|
|||
|
|
report_power: Time (s): cpu = 00:01:29 ; elapsed = 00:00:54 . Memory (MB): peak = 9020.867 ; gain = 136.031
|
|||
|
|
INFO: [runtcl-4] Executing : report_route_status -file design_1_wrapper_route_status.rpt -pb design_1_wrapper_route_status.pb
|
|||
|
|
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file design_1_wrapper_timing_summary_routed.rpt -pb design_1_wrapper_timing_summary_routed.pb -rpx design_1_wrapper_timing_summary_routed.rpx -warn_on_violation
|
|||
|
|
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Temperature grade: I, Delay Type: min_max.
|
|||
|
|
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
|||
|
|
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
|
|||
|
|
report_timing_summary: Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 9161.164 ; gain = 140.297
|
|||
|
|
INFO: [runtcl-4] Executing : report_incremental_reuse -file design_1_wrapper_incremental_reuse_routed.rpt
|
|||
|
|
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
|
|||
|
|
INFO: [runtcl-4] Executing : report_clock_utilization -file design_1_wrapper_clock_utilization_routed.rpt
|
|||
|
|
report_clock_utilization: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 9177.691 ; gain = 16.527
|
|||
|
|
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file design_1_wrapper_bus_skew_routed.rpt -pb design_1_wrapper_bus_skew_routed.pb -rpx design_1_wrapper_bus_skew_routed.rpx
|
|||
|
|
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Temperature grade: I, Delay Type: min_max.
|
|||
|
|
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
|||
|
|
INFO: [Timing 38-480] Writing timing data to binary archive.
|
|||
|
|
Write ShapeDB Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.750 . Memory (MB): peak = 9322.336 ; gain = 133.512
|
|||
|
|
Wrote PlaceDB: Time (s): cpu = 00:00:30 ; elapsed = 00:00:10 . Memory (MB): peak = 9327.945 ; gain = 139.121
|
|||
|
|
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 9327.945 ; gain = 0.000
|
|||
|
|
Writing XDEF routing.
|
|||
|
|
Writing XDEF routing logical nets.
|
|||
|
|
Writing XDEF routing special nets.
|
|||
|
|
Wrote RouteStorage: Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 9327.945 ; gain = 0.000
|
|||
|
|
Wrote Netlist Cache: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.266 . Memory (MB): peak = 9327.945 ; gain = 0.000
|
|||
|
|
Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 9327.945 ; gain = 0.000
|
|||
|
|
Write Physdb Complete: Time (s): cpu = 00:00:36 ; elapsed = 00:00:14 . Memory (MB): peak = 9327.945 ; gain = 139.121
|
|||
|
|
INFO: [Common 17-1381] The checkpoint 'C:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.runs/impl_2/design_1_wrapper_routed.dcp' has been generated.
|
|||
|
|
write_checkpoint: Time (s): cpu = 00:00:48 ; elapsed = 00:00:27 . Memory (MB): peak = 9327.945 ; gain = 150.254
|
|||
|
|
WARNING: [Memdata 28-361] Design is having concatenated BRAM controllers(heterogenous memory), this configuration is not supported by Updatemem for current device part. Only the first BRAM controller will be added to .MMI and used by Updatemem to update the bitstream with new data.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block design_1_i/smartconnect_0/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the design_1_i/smartconnect_0/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block design_1_i/smartconnect_0/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the design_1_i/smartconnect_0/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block design_1_i/smartconnect_0/inst/s02_nodes/s02_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the design_1_i/smartconnect_0/inst/s02_nodes/s02_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block design_1_i/smartconnect_0/inst/s02_nodes/s02_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the design_1_i/smartconnect_0/inst/s02_nodes/s02_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block design_1_i/smartconnect_0/inst/s02_nodes/s02_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the design_1_i/smartconnect_0/inst/s02_nodes/s02_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block design_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the design_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block design_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the design_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block design_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the design_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block design_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the design_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block design_1_i/smartconnect_0/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the design_1_i/smartconnect_0/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block design_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_si_handler/gen_si_handler.gen_request_fifos.gen_req_fifo[2].inst_req_fifo/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the design_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_si_handler/gen_si_handler.gen_request_fifos.gen_req_fifo[2].inst_req_fifo/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block design_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_si_handler/gen_si_handler.gen_request_fifos.gen_req_fifo[1].inst_req_fifo/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the design_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_si_handler/gen_si_handler.gen_request_fifos.gen_req_fifo[1].inst_req_fifo/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block design_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the design_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block design_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the design_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block design_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the design_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block design_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the design_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block design_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the design_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block design_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the design_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block design_1_i/ccsds122_datamover_0/inst/u_datamover/U0/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to auto. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the design_1_i/ccsds122_datamover_0/inst/u_datamover/U0/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_datamover/U0/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0/inst/u_datamover>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_datamover/U0/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0/inst/u_datamover>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_segment_reorder/u_meta_bank1/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_segment_reorder/u_meta_bank0/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_segment_reorder/u_data_bank1/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_segment_reorder/u_data_bank0/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l2/u_v_stage/u_dprev_line/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l2/u_v_stage/g_row_bank[5].u_row_bank/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l2/u_v_stage/g_row_bank[4].u_row_bank/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l2/u_v_stage/g_row_bank[3].u_row_bank/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l2/u_v_stage/g_row_bank[2].u_row_bank/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l2/u_v_stage/g_row_bank[1].u_row_bank/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l2/u_v_stage/g_row_bank[0].u_row_bank/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l1/u_level/u_v_stage/u_dprev_line/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l1/u_level/u_v_stage/g_row_bank[5].u_row_bank/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l1/u_level/u_v_stage/g_row_bank[4].u_row_bank/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l1/u_level/u_v_stage/g_row_bank[3].u_row_bank/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l1/u_level/u_v_stage/g_row_bank[2].u_row_bank/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l1/u_level/u_v_stage/g_row_bank[1].u_row_bank/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l1/u_level/u_v_stage/g_row_bank[0].u_row_bank/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l1/u_level/u_ll_row_order/u_row_hold/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l1/u_level/u_ll_row_order/u_row_hold/xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l0/u_level/u_v_stage/u_dprev_line/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l0/u_level/u_v_stage/g_row_bank[5].u_row_bank/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l0/u_level/u_v_stage/g_row_bank[4].u_row_bank/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l0/u_level/u_v_stage/g_row_bank[3].u_row_bank/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l0/u_level/u_v_stage/g_row_bank[2].u_row_bank/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l0/u_level/u_v_stage/g_row_bank[1].u_row_bank/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l0/u_level/u_v_stage/g_row_bank[0].u_row_bank/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-167] Found XPM memory block design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l0/u_level/u_ll_row_order/u_row_hold/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l0/u_level/u_ll_row_order/u_row_hold/xpm_memory_base_inst block.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/u_encoded_reorder/u_segment_byte_ram/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[9].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[9].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[9].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[9].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_symbol_cache/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[9].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_mid/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[9].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_lo/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[9].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_hi/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[9].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_count_cache/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[8].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[8].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[8].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[8].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_symbol_cache/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[8].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_mid/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[8].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_lo/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[8].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_hi/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[8].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_count_cache/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[7].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[7].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[7].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[7].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_symbol_cache/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[7].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_mid/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[7].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_lo/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[7].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_hi/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[7].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_count_cache/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[6].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[6].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[6].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[6].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_symbol_cache/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[6].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_mid/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[6].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_lo/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[6].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_hi/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[6].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_count_cache/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[5].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[5].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[5].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[5].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_symbol_cache/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[5].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_mid/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[5].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_lo/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[5].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_hi/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[5].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_count_cache/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[4].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[4].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[4].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[4].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_symbol_cache/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[4].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_mid/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[4].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_lo/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[4].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_hi/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[4].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_count_cache/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[3].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[3].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[3].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[3].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_symbol_cache/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[3].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_mid/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[3].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_lo/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[3].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_hi/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[3].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_count_cache/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[2].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[2].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[2].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[2].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_symbol_cache/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[2].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_mid/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
|||
|
|
INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[2].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_lo/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
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INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[2].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_hi/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
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INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[2].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_count_cache/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
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INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[23].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
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INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[23].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
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INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[23].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
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INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[23].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_symbol_cache/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
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INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[23].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_mid/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
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INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[23].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_lo/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
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INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[23].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_hi/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
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INFO: [Memdata 28-208] The XPM instance: <design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[23].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_count_cache/u_ram/xpm_memory_base_inst> is part of IP: <design_1_i/ccsds122_datamover_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
|
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INFO: [Common 17-14] Message 'Memdata 28-208' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
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Command: write_bitstream -force design_1_wrapper.bit -bin_file
|
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Attempting to get a license for feature 'Implementation' and/or device 'xcku5p'
|
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xcku5p'
|
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Running DRC as a precondition to command write_bitstream
|
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INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
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INFO: [DRC 23-27] Running DRC with 2 threads
|
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WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_bubble_removal/u_pack_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_i_1 (pin design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_bubble_removal/u_pack_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_i_1/I1) is not included in the LUT equation: 'O5=(A3)+((~A3)*(~A2)*A5)'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue.
|
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WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A2' of cell dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[31]_i_1 (pin dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[31]_i_1/I1) is not included in the LUT equation: 'O5=(A1*A4)+(A1*(~A4)*(~A5))+((~A1))'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue.
|
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WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A3' of cell dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[31]_i_1 (pin dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[31]_i_1/I0) is not included in the LUT equation: 'O5=(A1*A4)+(A1*(~A4)*(~A5))+((~A1))'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue.
|
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WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A4' of cell dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.id_state[0]_i_1 (pin dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.id_state[0]_i_1/I0) is not included in the LUT equation: 'O6=(A6+~A6)*((A5))'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue.
|
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WARNING: [DRC REQP-1857] RAMB18E2_writefirst_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_bubble_removal/u_pack_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmgb.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_8SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram) in SDP mode with WRITE_FIRST write-mode. It is strongly suggested to change this mode to NO_CHANGE for best power characteristics. However, both WRITE_FIRST and NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
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WARNING: [DRC REQP-1858] RAMB36E2_writefirst_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_bubble_removal/u_pack_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmgb.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_8SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram) in SDP mode with WRITE_FIRST write-mode. It is strongly suggested to change this mode to NO_CHANGE for best power characteristics. However, both WRITE_FIRST and NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[0].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_hi/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[0].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_lo/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[0].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_mid/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[0].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[0].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[0].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[10].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_hi/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[10].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_lo/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[10].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_mid/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[10].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[10].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[10].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[11].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_hi/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
|
|
WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[11].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_lo/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
|||
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[11].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_mid/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
|
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[11].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[11].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[11].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[12].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_hi/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[12].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_lo/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[12].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_mid/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[12].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[12].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[12].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[13].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_hi/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[13].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_lo/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[13].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_mid/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[13].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[13].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[13].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[14].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_hi/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[14].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_lo/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[14].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_mid/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[14].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[14].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[14].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[15].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_hi/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[15].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_lo/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[15].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_mid/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[15].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[15].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[15].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[16].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_hi/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[16].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_lo/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[16].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_mid/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[16].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[16].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[16].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[17].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_hi/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[17].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_lo/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[17].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_mid/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[17].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[17].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[17].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[18].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_hi/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[18].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_lo/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[18].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_mid/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[18].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[18].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[18].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[19].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_hi/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[19].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_lo/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[19].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_mid/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[19].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[19].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[19].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[1].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_hi/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[1].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_lo/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[1].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_mid/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[1].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[1].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[1].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[20].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_hi/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[20].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_lo/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[20].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_mid/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[20].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[20].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[20].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[21].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_hi/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[21].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_lo/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[21].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_mid/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[21].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[21].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[21].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[22].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_hi/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[22].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_lo/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[22].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_mid/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[22].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[22].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[22].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[23].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_hi/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[23].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_lo/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[23].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_mid/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[23].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[23].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[23].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[2].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_hi/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[2].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_lo/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[2].u_lane/u_segment_encoder/u_ac_bitplane/u_cached_commit/u_refine_cache_mid/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[2].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [Common 17-14] Message 'DRC REQP-1934' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[0].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[0].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[0].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[0].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[10].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[10].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[10].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[10].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[11].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[11].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[11].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[11].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[12].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[12].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[12].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[12].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[13].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[13].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[13].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[13].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[14].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[14].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[14].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[14].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[15].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[15].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[15].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[15].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[16].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[16].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[16].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[16].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[17].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[17].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[17].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[17].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[18].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[18].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[18].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[18].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[19].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[19].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[19].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[19].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[1].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[1].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[1].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[1].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[20].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[20].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[20].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[20].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[21].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[21].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[21].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[21].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[22].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[22].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[22].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[22].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[23].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[23].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[23].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[23].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[2].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[2].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[2].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[2].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[3].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[3].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[3].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[3].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[4].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[4].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[4].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[4].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[5].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[5].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[5].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[5].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[6].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[6].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[6].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[6].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[7].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[7].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[7].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[7].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[8].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[8].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[8].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[8].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[9].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[9].u_lane/u_segment_encoder/u_state_bank/u_state_ram/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[9].u_lane/u_segment_fill/u_bank0/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_backend_farm/g_lane[9].u_lane/u_segment_fill/u_bank1/u_ram/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l0/u_level/u_v_stage/g_row_bank[0].u_row_bank/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l0/u_level/u_v_stage/g_row_bank[1].u_row_bank/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l0/u_level/u_v_stage/g_row_bank[2].u_row_bank/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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WARNING: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_encoder/u_dwt_l0/u_level/u_v_stage/g_row_bank[3].u_row_bank/u_ram/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
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INFO: [Common 17-14] Message 'DRC REQP-1935' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
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WARNING: [DRC RTSTAT-10] No routable loads: 156 net(s) have no routable loads. The problem bus(es) and/or net(s) are design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/LMB_CE_riu, design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/LMB_UE_riu, design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/Q[12], design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/Q[13], design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/Q[14], design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/Q[15], design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_low/SYNC[0].sync_reg[1], design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/SYNC[0].sync_reg[1], design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_upp/SYNC[0].sync_reg[1], design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_low/SYNC[0].sync_reg[1], design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_low/SYNC[1].sync_reg[1], design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_upp/SYNC[1].sync_reg[1], design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_low/SYNC[1].sync_reg[1], design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/SYNC[1].sync_reg[1], design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_low/SYNC[2].sync_reg[1]... and (the first 15 of 154 listed).
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INFO: [Vivado 12-3199] DRC finished with 0 Errors, 294 Warnings
|
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INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
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Generating merged BMM file for the design top 'design_1_wrapper'...
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INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: c:/proj/ku5p_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/sw/calibration_0/Debug/calibration_ddr.elf
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INFO: [Designutils 20-2272] Running write_bitstream with 2 threads.
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Loading data files...
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Loading site data...
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Loading route data...
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Processing options...
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Creating bitmap...
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Creating bitstream...
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Writing bitstream ./design_1_wrapper.bit...
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Writing bitstream ./design_1_wrapper.bin...
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INFO: [Vivado 12-1842] Bitgen Completed Successfully.
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INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
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INFO: [Common 17-83] Releasing license: Implementation
|
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139 Infos, 208 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
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write_bitstream completed successfully
|
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write_bitstream: Time (s): cpu = 00:01:54 ; elapsed = 00:01:09 . Memory (MB): peak = 9990.785 ; gain = 662.840
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INFO: [Common 17-206] Exiting Vivado at Wed Jul 8 19:06:17 2026...
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