464 lines
36 KiB
Plaintext
464 lines
36 KiB
Plaintext
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#-----------------------------------------------------------
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# Vivado v2023.2 (64-bit)
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# SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023
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# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
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# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
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# Start of session at: Sat Jul 4 10:43:58 2026
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# Process ID: 21724
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# Current directory: C:/proj/xc7v_ccsds122_datamover_uart
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# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent37844 C:\proj\xc7v_ccsds122_datamover_uart\ccsds122_storage.xpr
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# Log file: C:/proj/xc7v_ccsds122_datamover_uart/vivado.log
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# Journal file: C:/proj/xc7v_ccsds122_datamover_uart\vivado.jou
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# Running On: DESKTOP-EB3SDQ2, OS: Windows, CPU Frequency: 2112 MHz, CPU Physical cores: 16, Host memory: 16817 MB
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#-----------------------------------------------------------
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start_gui
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open_project C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.xpr
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update_compile_order -fileset sources_1
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open_bd_design {C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd}
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report_ip_status -name ip_status
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upgrade_ip [get_ips {design_1_ccsds122_datamover_0_0 design_1_ccsds122_axil_slave_0_0}] -log ip_upgrade.log
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export_ip_user_files -of_objects [get_ips {design_1_ccsds122_datamover_0_0 design_1_ccsds122_axil_slave_0_0}] -no_script -sync -force -quiet
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report_ip_status -name ip_status
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startgroup
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create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:4.2 mig_7series_0
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endgroup
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set_property location {7 2336 1096} [get_bd_cells mig_7series_0]
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set_property location {5.5 2271 1107} [get_bd_cells mig_7series_0]
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set_property CONFIG.XML_INPUT_FILE {mig_a.prj} [get_bd_cells mig_7series_0]
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set_property CONFIG.RESET_BOARD_INTERFACE {Custom} [get_bd_cells mig_7series_0]
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set_property CONFIG.MIG_DONT_TOUCH_PARAM {Custom} [get_bd_cells mig_7series_0]
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set_property CONFIG.BOARD_MIG_PARAM {Custom} [get_bd_cells mig_7series_0]
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set_property location {5 2037 1123} [get_bd_cells mig_7series_0]
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delete_bd_objs [get_bd_intf_nets smartconnect_0_M00_AXI]
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connect_bd_intf_net [get_bd_intf_pins smartconnect_0/M00_AXI] [get_bd_intf_pins mig_7series_0/S_AXI]
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connect_bd_intf_net [get_bd_intf_pins system_ila_0/SLOT_2_AXI] [get_bd_intf_pins mig_7series_0/S_AXI]
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delete_bd_objs [get_bd_intf_nets aclk_0]
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connect_bd_intf_net [get_bd_intf_ports aclk_0] [get_bd_intf_pins mig_7series_0/SYS_CLK]
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undo
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undo
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delete_bd_objs [get_bd_intf_nets aclk_0]
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connect_bd_intf_net [get_bd_intf_ports aclk_0] [get_bd_intf_pins mig_7series_0/SYS_CLK]
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delete_bd_objs [get_bd_nets util_vector_logic_0_Res]
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connect_bd_net [get_bd_pins util_vector_logic_0/Res] [get_bd_pins mig_7series_0/sys_rst]
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delete_bd_objs [get_bd_intf_nets c0_ddr3]
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set_property location {2362 1077} [get_bd_intf_ports c0_ddr3]
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set_property location {2406 1140} [get_bd_intf_ports c0_ddr3]
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connect_bd_intf_net [get_bd_intf_ports c0_ddr3] [get_bd_intf_pins mig_7series_0/DDR3]
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delete_bd_objs [get_bd_nets ddr3_0_c0_init_calib_complete]
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connect_bd_net [get_bd_pins mig_7series_0/init_calib_complete] [get_bd_pins ila_0/probe0]
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delete_bd_objs [get_bd_nets ddr3_0_c0_ddr3_ui_clk_sync_rst]
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connect_bd_net [get_bd_pins mig_7series_0/ui_clk_sync_rst] [get_bd_pins proc_sys_reset_0/ext_reset_in]
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delete_bd_objs [get_bd_cells ddr3_0]
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connect_bd_net [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins axi_chip2chip_0/m_aclk]
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connect_bd_net [get_bd_pins mig_7series_0/aresetn] [get_bd_pins proc_sys_reset_0/peripheral_aresetn]
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set_property CONFIG.XML_INPUT_FILE {c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/mig_b.prj} [get_bd_cells mig_7series_0]
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set_property CONFIG.RESET_BOARD_INTERFACE {Custom} [get_bd_cells mig_7series_0]
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set_property CONFIG.MIG_DONT_TOUCH_PARAM {Custom} [get_bd_cells mig_7series_0]
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set_property CONFIG.BOARD_MIG_PARAM {Custom} [get_bd_cells mig_7series_0]
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set_property CONFIG.XML_INPUT_FILE {c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/mig_a.prj} [get_bd_cells mig_7series_0]
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set_property CONFIG.RESET_BOARD_INTERFACE {Custom} [get_bd_cells mig_7series_0]
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set_property CONFIG.MIG_DONT_TOUCH_PARAM {Custom} [get_bd_cells mig_7series_0]
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set_property CONFIG.BOARD_MIG_PARAM {Custom} [get_bd_cells mig_7series_0]
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delete_bd_objs [get_bd_nets clk_wiz_0_clk_out1]
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connect_bd_net [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins mig_7series_0/clk_ref_i]
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startgroup
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create_bd_cell -type ip -vlnv xilinx.com:user:ccsds_uart_axi:1.0 ccsds_uart_axi_0
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endgroup
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set_property location {3.5 1128 1016} [get_bd_cells ccsds_uart_axi_0]
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delete_bd_objs [get_bd_intf_nets axi_chip2chip_0_m_axi]
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connect_bd_intf_net [get_bd_intf_pins ccsds_uart_axi_0/m_axi] [get_bd_intf_pins smartconnect_0/S02_AXI]
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startgroup
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set_property CONFIG.NUM_SI {4} [get_bd_cells smartconnect_0]
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endgroup
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connect_bd_intf_net [get_bd_intf_pins smartconnect_0/S03_AXI] [get_bd_intf_pins ccsds_uart_axi_0/m_axil]
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delete_bd_objs [get_bd_nets xlconstant_0_dout] [get_bd_nets axi_c2c_selio_tx_clk_out] [get_bd_nets axi_c2c_selio_tx_data_out] [get_bd_nets axi_c2c_selio_rx_clk_in] [get_bd_nets axi_c2c_selio_rx_data_in] [get_bd_nets axi_chip2chip_0_axi_c2c_link_status_out] [get_bd_nets axi_chip2chip_0_axi_c2c_multi_bit_error_out] [get_bd_cells axi_chip2chip_0]
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connect_bd_net [get_bd_pins ccsds_uart_axi_0/clk] [get_bd_pins mig_7series_0/ui_clk]
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connect_bd_net [get_bd_pins ccsds_uart_axi_0/rst_n] [get_bd_pins proc_sys_reset_0/peripheral_aresetn]
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startgroup
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make_bd_pins_external [get_bd_pins ccsds_uart_axi_0/uart_rx_i]
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endgroup
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set_property name uart_rx [get_bd_ports uart_rx_i_0]
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set_property name uart_rx [get_bd_nets uart_rx_i_0_1]
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startgroup
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make_bd_pins_external [get_bd_pins ccsds_uart_axi_0/uart_tx_o]
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endgroup
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set_property name uart_tx [get_bd_nets ccsds_uart_axi_0_uart_tx_o]
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set_property name uart_tx [get_bd_ports uart_tx_o_0]
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delete_bd_objs [get_bd_ports axi_c2c_selio_tx_clk_out] [get_bd_ports axi_c2c_selio_tx_data_out]
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delete_bd_objs [get_bd_ports axi_c2c_selio_rx_clk_in] [get_bd_ports axi_c2c_selio_rx_data_in]
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delete_bd_objs [get_bd_cells xlconstant_0]
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connect_bd_net [get_bd_ports uart_rx] [get_bd_pins ila_0/probe13]
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connect_bd_net [get_bd_pins ila_0/probe14] [get_bd_pins ccsds_uart_axi_0/uart_tx_o]
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startgroup
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set_property CONFIG.C_NUM_MONITOR_SLOTS {5} [get_bd_cells system_ila_0]
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endgroup
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connect_bd_intf_net [get_bd_intf_pins system_ila_0/SLOT_4_AXI] [get_bd_intf_pins ccsds_uart_axi_0/m_axil]
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report_ip_status -name ip_status
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regenerate_bd_layout
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assign_bd_address
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validate_bd_design
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startgroup
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exclude_bd_addr_seg [get_bd_addr_segs ccsds122_datamover_0/m_axi_mm2s/SEG_mig_7series_0_memaddr]
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exclude_bd_addr_seg [get_bd_addr_segs ccsds122_datamover_0/m_axi_s2mm/SEG_mig_7series_0_memaddr]
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exclude_bd_addr_seg [get_bd_addr_segs ccsds_uart_axi_0/m_axi/SEG_mig_7series_0_memaddr]
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exclude_bd_addr_seg [get_bd_addr_segs ccsds_uart_axi_0/m_axil/SEG_mig_7series_0_memaddr]
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endgroup
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startgroup
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include_bd_addr_seg [get_bd_addr_segs -excluded ccsds122_datamover_0/m_axi_mm2s/SEG_mig_7series_0_memaddr]
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endgroup
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set_property offset 0x80000000 [get_bd_addr_segs {ccsds122_datamover_0/m_axi_mm2s/SEG_mig_7series_0_memaddr}]
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set_property offset 0 [get_bd_addr_segs {ccsds122_datamover_0/m_axi_mm2s/SEG_mig_7series_0_memaddr}]
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set_property range 2G [get_bd_addr_segs {ccsds122_datamover_0/m_axi_mm2s/SEG_mig_7series_0_memaddr}]
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startgroup
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include_bd_addr_seg [get_bd_addr_segs -excluded ccsds122_datamover_0/m_axi_s2mm/SEG_mig_7series_0_memaddr]
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endgroup
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set_property offset 0 [get_bd_addr_segs {ccsds122_datamover_0/m_axi_s2mm/SEG_mig_7series_0_memaddr}]
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set_property range 2G [get_bd_addr_segs {ccsds122_datamover_0/m_axi_s2mm/SEG_mig_7series_0_memaddr}]
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startgroup
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include_bd_addr_seg [get_bd_addr_segs -excluded ccsds_uart_axi_0/m_axi/SEG_mig_7series_0_memaddr]
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endgroup
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set_property offset 0x80000000 [get_bd_addr_segs {ccsds_uart_axi_0/m_axi/SEG_mig_7series_0_memaddr}]
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set_property range 64K [get_bd_addr_segs {ccsds_uart_axi_0/m_axi/SEG_ccsds122_axil_slave_0_reg0}]
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set_property offset 0xFFFF0000 [get_bd_addr_segs {ccsds122_datamover_0/m_axi_mm2s/SEG_ccsds122_axil_slave_0_reg0}]
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set_property offset 0xFFFF0000 [get_bd_addr_segs {ccsds_uart_axi_0/m_axi/SEG_ccsds122_axil_slave_0_reg0}]
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set_property range 64K [get_bd_addr_segs {ccsds_uart_axi_0/m_axil/SEG_ccsds122_axil_slave_0_reg0}]
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set_property offset 0xFFFF0000 [get_bd_addr_segs {ccsds_uart_axi_0/m_axil/SEG_ccsds122_axil_slave_0_reg0}]
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startgroup
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include_bd_addr_seg [get_bd_addr_segs -excluded ccsds_uart_axi_0/m_axil/SEG_mig_7series_0_memaddr]
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endgroup
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set_property offset 0 [get_bd_addr_segs {ccsds_uart_axi_0/m_axil/SEG_mig_7series_0_memaddr}]
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set_property range 2G [get_bd_addr_segs {ccsds_uart_axi_0/m_axil/SEG_mig_7series_0_memaddr}]
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report_ip_status -name ip_status
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save_bd_design
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set_property offset 0 [get_bd_addr_segs {ccsds_uart_axi_0/m_axi/SEG_mig_7series_0_memaddr}]
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set_property range 2G [get_bd_addr_segs {ccsds_uart_axi_0/m_axi/SEG_mig_7series_0_memaddr}]
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save_bd_design
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regenerate_bd_layout
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validate_bd_design
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report_ip_status -name ip_status
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generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
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catch { config_ip_cache -export [get_ips -all design_1_ccsds122_datamover_0_0] }
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catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
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catch { config_ip_cache -export [get_ips -all design_1_ccsds122_axil_slave_0_0] }
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catch { config_ip_cache -export [get_ips -all design_1_ila_0_0] }
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catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
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catch { config_ip_cache -export [get_ips -all design_1_proc_sys_reset_0_0] }
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catch { config_ip_cache -export [get_ips -all design_1_util_vector_logic_0_3] }
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catch { config_ip_cache -export [get_ips -all design_1_clk_wiz_0_0] }
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catch { config_ip_cache -export [get_ips -all design_1_ccsds_uart_axi_0_0] }
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export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
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create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
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launch_runs design_1_ccsds122_axil_slave_0_0_synth_1 design_1_ccsds122_datamover_0_0_synth_1 design_1_ccsds_uart_axi_0_0_synth_1 design_1_clk_wiz_0_0_synth_1 design_1_ila_0_0_synth_1 design_1_mig_7series_0_0_synth_1 design_1_proc_sys_reset_0_0_synth_1 design_1_smartconnect_0_1_synth_1 design_1_system_ila_0_0_synth_1 design_1_util_vector_logic_0_3_synth_1 -jobs 24
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wait_on_run design_1_ccsds122_axil_slave_0_0_synth_1
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wait_on_run design_1_ccsds122_datamover_0_0_synth_1
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wait_on_run design_1_ccsds_uart_axi_0_0_synth_1
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wait_on_run design_1_clk_wiz_0_0_synth_1
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wait_on_run design_1_ila_0_0_synth_1
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wait_on_run design_1_mig_7series_0_0_synth_1
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wait_on_run design_1_proc_sys_reset_0_0_synth_1
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wait_on_run design_1_smartconnect_0_1_synth_1
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wait_on_run design_1_system_ila_0_0_synth_1
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wait_on_run design_1_util_vector_logic_0_3_synth_1
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export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
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report_ip_status -name ip_status
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reset_run synth_1
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launch_runs impl_1_copy_2 -to_step write_bitstream -jobs 24
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wait_on_run impl_1_copy_2
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open_run impl_1_copy_2
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open_bd_design {C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd}
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startgroup
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set_property -dict [list \
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CONFIG.CLKOUT1_JITTER {114.829} \
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CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {200.000} \
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CONFIG.MMCM_CLKOUT0_DIVIDE_F {5.000} \
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] [get_bd_cells clk_wiz_0]
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endgroup
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startgroup
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endgroup
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undo
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undo
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startgroup
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set_property -dict [list \
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CONFIG.CLKOUT1_JITTER {114.829} \
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CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {200.000} \
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CONFIG.MMCM_CLKOUT0_DIVIDE_F {5.000} \
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] [get_bd_cells clk_wiz_0]
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endgroup
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regenerate_bd_layout
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validate_bd_design
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generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
|
||
|
|
catch { [ delete_ip_run [get_ips -all design_1_smartconnect_0_1] ] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
|
||
|
|
catch { [ delete_ip_run [get_ips -all design_1_system_ila_0_0] ] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_clk_wiz_0_0] }
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
||
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
launch_runs design_1_clk_wiz_0_0_synth_1 design_1_mig_7series_0_0_synth_1 -jobs 24
|
||
|
|
wait_on_run design_1_clk_wiz_0_0_synth_1
|
||
|
|
wait_on_run design_1_mig_7series_0_0_synth_1
|
||
|
|
export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
||
|
|
reset_run synth_1
|
||
|
|
launch_runs impl_1_copy_2 -to_step write_bitstream -jobs 24
|
||
|
|
wait_on_run impl_1_copy_2
|
||
|
|
set_property CONFIG.XML_INPUT_FILE {c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/mig_b.prj} [get_bd_cells mig_7series_0]
|
||
|
|
set_property CONFIG.RESET_BOARD_INTERFACE {Custom} [get_bd_cells mig_7series_0]
|
||
|
|
set_property CONFIG.MIG_DONT_TOUCH_PARAM {Custom} [get_bd_cells mig_7series_0]
|
||
|
|
set_property CONFIG.BOARD_MIG_PARAM {Custom} [get_bd_cells mig_7series_0]
|
||
|
|
generate_target all [get_files c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0.xci]
|
||
|
|
save_bd_design
|
||
|
|
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
||
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
launch_runs design_1_mig_7series_0_0_synth_1 -jobs 24
|
||
|
|
wait_on_run design_1_mig_7series_0_0_synth_1
|
||
|
|
export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
||
|
|
reset_run synth_1
|
||
|
|
launch_runs impl_1_copy_2 -to_step write_bitstream -jobs 24
|
||
|
|
wait_on_run impl_1_copy_2
|
||
|
|
open_run synth_1 -name synth_1
|
||
|
|
open_bd_design {C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd}
|
||
|
|
reset_run impl_1_copy_2
|
||
|
|
delete_bd_objs [get_bd_intf_nets aclk_0_1] [get_bd_intf_ports aclk_0]
|
||
|
|
startgroup
|
||
|
|
make_bd_intf_pins_external [get_bd_intf_pins mig_7series_0/SYS_CLK]
|
||
|
|
endgroup
|
||
|
|
regenerate_bd_layout
|
||
|
|
undo
|
||
|
|
undo
|
||
|
|
undo
|
||
|
|
regenerate_bd_layout
|
||
|
|
regenerate_bd_layout
|
||
|
|
validate_bd_design
|
||
|
|
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
||
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
||
|
|
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
||
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
||
|
|
reset_run synth_1
|
||
|
|
launch_runs impl_1_copy_2 -to_step write_bitstream -jobs 24
|
||
|
|
wait_on_run impl_1_copy_2
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
set_property CONFIG.XML_INPUT_FILE {c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/mig_a.prj} [get_bd_cells mig_7series_0]
|
||
|
|
set_property CONFIG.RESET_BOARD_INTERFACE {Custom} [get_bd_cells mig_7series_0]
|
||
|
|
set_property CONFIG.MIG_DONT_TOUCH_PARAM {Custom} [get_bd_cells mig_7series_0]
|
||
|
|
set_property CONFIG.BOARD_MIG_PARAM {Custom} [get_bd_cells mig_7series_0]
|
||
|
|
delete_bd_objs [get_bd_nets clk_wiz_0_clk_out1]
|
||
|
|
generate_target all [get_files c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0.xci]
|
||
|
|
set_property CONFIG.XML_INPUT_FILE {c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/mig_b.prj} [get_bd_cells mig_7series_0]
|
||
|
|
set_property CONFIG.RESET_BOARD_INTERFACE {Custom} [get_bd_cells mig_7series_0]
|
||
|
|
set_property CONFIG.MIG_DONT_TOUCH_PARAM {Custom} [get_bd_cells mig_7series_0]
|
||
|
|
set_property CONFIG.BOARD_MIG_PARAM {Custom} [get_bd_cells mig_7series_0]
|
||
|
|
generate_target all [get_files c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0.xci]
|
||
|
|
regenerate_bd_layout
|
||
|
|
validate_bd_design
|
||
|
|
regenerate_bd_layout
|
||
|
|
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
||
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
launch_runs design_1_mig_7series_0_0_synth_1 -jobs 24
|
||
|
|
wait_on_run design_1_mig_7series_0_0_synth_1
|
||
|
|
export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
||
|
|
delete_bd_objs [get_bd_nets proc_sys_reset_0_peripheral_reset] [get_bd_cells clk_wiz_0]
|
||
|
|
undo
|
||
|
|
startgroup
|
||
|
|
create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_1
|
||
|
|
endgroup
|
||
|
|
set_property CONFIG.PRIM_SOURCE {Differential_clock_capable_pin} [get_bd_cells clk_wiz_1]
|
||
|
|
delete_bd_objs [get_bd_cells clk_wiz_1]
|
||
|
|
startgroup
|
||
|
|
create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 util_ds_buf_0
|
||
|
|
endgroup
|
||
|
|
delete_bd_objs [get_bd_intf_nets aclk_0_1]
|
||
|
|
connect_bd_intf_net [get_bd_intf_ports aclk_0] [get_bd_intf_pins util_ds_buf_0/CLK_IN_D]
|
||
|
|
set_property CONFIG.XML_INPUT_FILE {c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/mig_a.prj} [get_bd_cells mig_7series_0]
|
||
|
|
set_property CONFIG.RESET_BOARD_INTERFACE {Custom} [get_bd_cells mig_7series_0]
|
||
|
|
set_property CONFIG.MIG_DONT_TOUCH_PARAM {Custom} [get_bd_cells mig_7series_0]
|
||
|
|
set_property CONFIG.BOARD_MIG_PARAM {Custom} [get_bd_cells mig_7series_0]
|
||
|
|
connect_bd_net [get_bd_pins util_ds_buf_0/IBUF_OUT] [get_bd_pins mig_7series_0/sys_clk_i]
|
||
|
|
startgroup
|
||
|
|
create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_1
|
||
|
|
endgroup
|
||
|
|
connect_bd_net [get_bd_pins clk_wiz_1/clk_in1] [get_bd_pins util_ds_buf_0/IBUF_OUT]
|
||
|
|
connect_bd_net [get_bd_ports sys_rst_n] [get_bd_pins clk_wiz_1/reset]
|
||
|
|
undo
|
||
|
|
connect_bd_net [get_bd_pins clk_wiz_1/reset] [get_bd_pins util_vector_logic_0/Res]
|
||
|
|
delete_bd_objs [get_bd_nets proc_sys_reset_0_peripheral_reset] [get_bd_cells clk_wiz_0]
|
||
|
|
undo
|
||
|
|
delete_bd_objs [get_bd_nets proc_sys_reset_0_peripheral_reset] [get_bd_cells clk_wiz_0]
|
||
|
|
delete_bd_objs [get_bd_nets ddr3_0_c0_ddr3_ui_clk]
|
||
|
|
connect_bd_net [get_bd_pins ila_0/clk] [get_bd_pins clk_wiz_1/clk_out1]
|
||
|
|
connect_bd_net [get_bd_pins system_ila_0/clk] [get_bd_pins clk_wiz_1/clk_out1]
|
||
|
|
connect_bd_net [get_bd_pins ccsds_uart_axi_0/clk] [get_bd_pins mig_7series_0/ui_clk]
|
||
|
|
connect_bd_net [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins smartconnect_0/aclk]
|
||
|
|
connect_bd_net [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins ccsds122_axil_slave_0/clk]
|
||
|
|
connect_bd_net [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk]
|
||
|
|
connect_bd_net [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins ccsds122_datamover_0/clk]
|
||
|
|
regenerate_bd_layout
|
||
|
|
validate_bd_design
|
||
|
|
connect_bd_net [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins ccsds122_datamover_0/m_axi_mm2s_aclk]
|
||
|
|
connect_bd_net [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins ccsds122_datamover_0/m_axis_mm2s_cmdsts_aclk]
|
||
|
|
connect_bd_net [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins ccsds122_datamover_0/m_axi_s2mm_aclk]
|
||
|
|
connect_bd_net [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins ccsds122_datamover_0/m_axis_s2mm_cmdsts_awclk]
|
||
|
|
regenerate_bd_layout
|
||
|
|
validate_bd_design
|
||
|
|
undo
|
||
|
|
undo
|
||
|
|
undo
|
||
|
|
undo
|
||
|
|
undo
|
||
|
|
undo
|
||
|
|
undo
|
||
|
|
undo
|
||
|
|
undo
|
||
|
|
undo
|
||
|
|
undo
|
||
|
|
undo
|
||
|
|
undo
|
||
|
|
undo
|
||
|
|
delete_bd_objs [get_bd_nets mig_7series_0_init_calib_complete]
|
||
|
|
delete_bd_objs [get_bd_nets uart_tx]
|
||
|
|
undo
|
||
|
|
delete_bd_objs [get_bd_nets ccsds122_datamover_0_compress_done_valid]
|
||
|
|
connect_bd_net [get_bd_pins ccsds122_datamover_0/compress_done_valid] [get_bd_pins ila_0/probe0]
|
||
|
|
startgroup
|
||
|
|
create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.2 ila_1
|
||
|
|
endgroup
|
||
|
|
set_property -dict [list \
|
||
|
|
CONFIG.C_MONITOR_TYPE {Native} \
|
||
|
|
CONFIG.C_NUM_OF_PROBES {2} \
|
||
|
|
] [get_bd_cells ila_1]
|
||
|
|
set_property location {3 952 137} [get_bd_cells ccsds122_datamover_0]
|
||
|
|
connect_bd_net [get_bd_pins ila_1/clk] [get_bd_pins clk_wiz_1/clk_out1]
|
||
|
|
connect_bd_net [get_bd_pins ila_1/probe0] [get_bd_pins mig_7series_0/init_calib_complete]
|
||
|
|
connect_bd_net [get_bd_pins mig_7series_0/mmcm_locked] [get_bd_pins ila_1/probe1]
|
||
|
|
startgroup
|
||
|
|
set_property CONFIG.C_NUM_OF_PROBES {3} [get_bd_cells ila_1]
|
||
|
|
endgroup
|
||
|
|
connect_bd_net [get_bd_pins ila_1/probe2] [get_bd_pins mig_7series_0/ui_clk_sync_rst]
|
||
|
|
regenerate_bd_layout
|
||
|
|
validate_bd_design
|
||
|
|
startgroup
|
||
|
|
set_property CONFIG.C_NUM_OF_PROBES {25} [get_bd_cells ila_0]
|
||
|
|
endgroup
|
||
|
|
regenerate_bd_layout
|
||
|
|
validate_bd_design
|
||
|
|
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_ila_0_0] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_util_ds_buf_0_0] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_clk_wiz_1_1] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_ila_1_0] }
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
||
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
launch_runs design_1_clk_wiz_1_1_synth_1 design_1_ila_0_0_synth_1 design_1_ila_1_0_synth_1 design_1_mig_7series_0_0_synth_1 design_1_util_ds_buf_0_0_synth_1 -jobs 24
|
||
|
|
wait_on_run design_1_clk_wiz_1_1_synth_1
|
||
|
|
wait_on_run design_1_ila_0_0_synth_1
|
||
|
|
wait_on_run design_1_ila_1_0_synth_1
|
||
|
|
wait_on_run design_1_mig_7series_0_0_synth_1
|
||
|
|
wait_on_run design_1_util_ds_buf_0_0_synth_1
|
||
|
|
export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
||
|
|
reset_run synth_1
|
||
|
|
launch_runs impl_1_copy_2 -to_step write_bitstream -jobs 24
|
||
|
|
wait_on_run impl_1_copy_2
|
||
|
|
reset_run synth_1
|
||
|
|
reset_run design_1_ila_0_0_synth_1
|
||
|
|
reset_run design_1_mig_7series_0_0_synth_1
|
||
|
|
reset_run design_1_ila_1_0_synth_1
|
||
|
|
startgroup
|
||
|
|
create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 util_ds_buf_1
|
||
|
|
endgroup
|
||
|
|
set_property CONFIG.C_BUF_TYPE {BUFG} [get_bd_cells util_ds_buf_1]
|
||
|
|
delete_bd_objs [get_bd_nets util_ds_buf_0_IBUF_OUT]
|
||
|
|
connect_bd_net [get_bd_pins util_ds_buf_0/IBUF_OUT] [get_bd_pins clk_wiz_1/clk_in1]
|
||
|
|
connect_bd_net [get_bd_pins util_ds_buf_1/BUFG_I] [get_bd_pins util_ds_buf_0/IBUF_OUT]
|
||
|
|
connect_bd_net [get_bd_pins util_ds_buf_1/BUFG_O] [get_bd_pins mig_7series_0/sys_clk_i]
|
||
|
|
regenerate_bd_layout
|
||
|
|
validate_bd_design
|
||
|
|
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_ila_0_0] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_ila_1_0] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_util_ds_buf_1_0] }
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
||
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
launch_runs design_1_ila_0_0_synth_1 design_1_ila_1_0_synth_1 design_1_mig_7series_0_0_synth_1 design_1_util_ds_buf_1_0_synth_1 -jobs 24
|
||
|
|
wait_on_run design_1_ila_0_0_synth_1
|
||
|
|
wait_on_run design_1_ila_1_0_synth_1
|
||
|
|
wait_on_run design_1_mig_7series_0_0_synth_1
|
||
|
|
wait_on_run design_1_util_ds_buf_1_0_synth_1
|
||
|
|
export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
||
|
|
launch_runs impl_1_copy_2 -to_step write_bitstream -jobs 24
|
||
|
|
wait_on_run impl_1_copy_2
|
||
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
refresh_design
|
||
|
|
open_bd_design {C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd}
|
||
|
|
set_property CONFIG.XML_INPUT_FILE {c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/mig_b.prj} [get_bd_cells mig_7series_0]
|
||
|
|
set_property CONFIG.RESET_BOARD_INTERFACE {Custom} [get_bd_cells mig_7series_0]
|
||
|
|
set_property CONFIG.MIG_DONT_TOUCH_PARAM {Custom} [get_bd_cells mig_7series_0]
|
||
|
|
set_property CONFIG.BOARD_MIG_PARAM {Custom} [get_bd_cells mig_7series_0]
|
||
|
|
generate_target all [get_files c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0.xci]
|
||
|
|
regenerate_bd_layout
|
||
|
|
validate_bd_design
|
||
|
|
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
||
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
launch_runs design_1_mig_7series_0_0_synth_1 -jobs 24
|
||
|
|
wait_on_run design_1_mig_7series_0_0_synth_1
|
||
|
|
export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
||
|
|
reset_run synth_1
|
||
|
|
launch_runs synth_1 -jobs 24
|
||
|
|
wait_on_run synth_1
|
||
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
synth_design -rtl -rtl_skip_mlo -name rtl_1
|
||
|
|
launch_runs impl_1_copy_2 -to_step write_bitstream -jobs 24
|
||
|
|
wait_on_run impl_1_copy_2
|
||
|
|
current_design impl_1_copy_2
|
||
|
|
close_design
|
||
|
|
close_design
|
||
|
|
show_objects -name find_1 [get_sites "*CMT_*" ]
|
||
|
|
show_objects -name find_1 [get_sites "*CMT*" ]
|
||
|
|
get_sites -filter "NAME=~CMT"
|
||
|
|
get_sites -of [get_clock_regions -of [get_banks 38]] -filter "NAME=~CMT"
|
||
|
|
get_sites -of [get_clock_regions -of [get_banks 38]] -filter "TYPE==MMCME2_ADV"
|
||
|
|
get_sites -filter "TYPE==MMCME2_ADV"
|
||
|
|
get_sites -filter "TYPE==MMCME2_ADV"
|
||
|
|
get_cells -hier *mmcm_adv*
|
||
|
|
close_design
|
||
|
|
reset_run synth_1
|
||
|
|
launch_runs synth_1 -jobs 24
|
||
|
|
wait_on_run synth_1
|
||
|
|
update_ip_catalog -rebuild -scan_changes
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
upgrade_ip -vlnv xilinx.com:user:ccsds122_datamover:1.0 [get_ips design_1_ccsds122_datamover_0_0] -log ip_upgrade.log
|
||
|
|
export_ip_user_files -of_objects [get_ips design_1_ccsds122_datamover_0_0] -no_script -sync -force -quiet
|
||
|
|
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_ccsds122_datamover_0_0] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
||
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
launch_runs design_1_ccsds122_datamover_0_0_synth_1 -jobs 24
|
||
|
|
wait_on_run design_1_ccsds122_datamover_0_0_synth_1
|
||
|
|
export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
||
|
|
reset_run synth_1
|
||
|
|
launch_runs impl_1_copy_2 -to_step write_bitstream -jobs 24
|
||
|
|
wait_on_run impl_1_copy_2
|
||
|
|
close_bd_design [get_bd_designs design_1]
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
reset_run synth_1
|
||
|
|
reset_run design_1_ccsds122_datamover_0_0_synth_1
|