ku5p_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/vivado.pb

>
Refreshing IP repositories
234*coregenZ19-234hpx<05>

_
 Loaded user IP repository '%s'.
1135*coregen2
c:/proj/FPGA_DESIGN_IPZ19-1700hpx<05>

j
"Loaded Vivado IP repository '%s'.
1332*coregen2!
C:/Xilinx/Vivado/2023.2/data/ipZ19-2313hpx<05>

<EFBFBD>

I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2
add_files: 2

00:00:072

00:00:072	
748.8012	
161.762Z17-268hpx<0C>

<EFBFBD>

Command: %s
1870*	planAhead2<64>

<EFBFBD>
read_checkpoint -auto_incremental -incremental C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/utils_1/imports/synth_1/design_1_wrapper.dcpZ12-2866hpx<04>

<EFBFBD>

;Read reference checkpoint from %s for incremental synthesis3154*	planAhead2i
gC:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/utils_1/imports/synth_1/design_1_wrapper.dcpZ12-5825hpx<05>

T
-Please ensure there are no constraint changes3725*	planAheadZ12-7989hpx<05>

n
Command: %s
53*	vivadotcl2=
;synth_design -top design_1_wrapper -part xc7vx690tffg1761-2Z4-113hpx<04>

:
Starting synth_design
149*	vivadotclZ4-321hpx<04>

|
@Attempting to get a license for feature '%s' and/or device '%s'
308*common2
	Synthesis2
	xc7vx690tZ17-347hpx<04>

l
0Got license for feature '%s' and/or device '%s'
310*common2
	Synthesis2
	xc7vx690tZ17-349hpx<05>

G
Loading part %s157*device2
xc7vx690tffg1761-2Z21-403hpx<05>


VNo compile time benefit to using incremental synthesis; A full resynthesis will be run2353*designutilsZ20-5440hpx<05>

<EFBFBD>
<EFBFBD>
Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}2229*designutilsZ20-4379hpx<05>

o
HMultithreading enabled for synth_design using a maximum of %s processes.4828*oasys2

2Z8-7079hpx<05>

a
?Launching helper process for spawning children vivado processes4827*oasysZ8-7078hpx<05>

N
#Helper process launched with PID %s4824*oasys2
34012Z8-7075hpx<05>

<EFBFBD>

%s*synth2{
yStarting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1803.441 ; gain = 439.133
hpx<0C>

<EFBFBD>

synthesizing module '%s'%s4497*oasys2
design_1_wrapper2
2j
fC:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
2
138
@
Z8-6157hpx<05>

<EFBFBD>

synthesizing module '%s'%s4497*oasys2

design_12
2d
`c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
2
138
@
Z8-6157hpx<05>

<EFBFBD>
synthesizing module '%s'%s4497*oasys2"
 design_1_ccsds122_axil_slave_0_02
2<>

<EFBFBD>
C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/.Xil/Vivado-19404-DESKTOP-EB3SDQ2/realtime/design_1_ccsds122_axil_slave_0_0_stub.v
2

68
@
Z8-6157hpx<05>

<EFBFBD>
'done synthesizing module '%s'%s (%s#%s)4495*oasys2"
 design_1_ccsds122_axil_slave_0_02
2

02

12<31>

<EFBFBD>
C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/.Xil/Vivado-19404-DESKTOP-EB3SDQ2/realtime/design_1_ccsds122_axil_slave_0_0_stub.v
2

68
@
Z8-6155hpx<05>

<EFBFBD>
synthesizing module '%s'%s4497*oasys2!
design_1_ccsds122_datamover_0_02
2<>

<EFBFBD>
C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/.Xil/Vivado-19404-DESKTOP-EB3SDQ2/realtime/design_1_ccsds122_datamover_0_0_stub.v
2

68
@
Z8-6157hpx<05>

<EFBFBD>
'done synthesizing module '%s'%s (%s#%s)4495*oasys2!
design_1_ccsds122_datamover_0_02
2

02

12<31>

<EFBFBD>
C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/.Xil/Vivado-19404-DESKTOP-EB3SDQ2/realtime/design_1_ccsds122_datamover_0_0_stub.v
2

68
@
Z8-6155hpx<05>

<EFBFBD>
synthesizing module '%s'%s4497*oasys2
design_1_ccsds_uart_axi_0_02
2<>

<EFBFBD>
C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/.Xil/Vivado-19404-DESKTOP-EB3SDQ2/realtime/design_1_ccsds_uart_axi_0_0_stub.v
2

68
@
Z8-6157hpx<05>

<EFBFBD>
'done synthesizing module '%s'%s (%s#%s)4495*oasys2
design_1_ccsds_uart_axi_0_02
2

02

12<31>

<EFBFBD>
C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/.Xil/Vivado-19404-DESKTOP-EB3SDQ2/realtime/design_1_ccsds_uart_axi_0_0_stub.v
2

68
@
Z8-6155hpx<05>

<EFBFBD>

synthesizing module '%s'%s4497*oasys2
design_1_clk_wiz_1_12
2<>

<EFBFBD>
C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/.Xil/Vivado-19404-DESKTOP-EB3SDQ2/realtime/design_1_clk_wiz_1_1_stub.v
2

68
@
Z8-6157hpx<05>

<EFBFBD>
'done synthesizing module '%s'%s (%s#%s)4495*oasys2
design_1_clk_wiz_1_12
2

02

12<31>

<EFBFBD>
C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/.Xil/Vivado-19404-DESKTOP-EB3SDQ2/realtime/design_1_clk_wiz_1_1_stub.v
2

68
@
Z8-6155hpx<05>

<EFBFBD>

9port '%s' of module '%s' is unconnected for instance '%s'4818*oasys2
locked2
design_1_clk_wiz_1_12
	clk_wiz_12d
`c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
2
4258
@
Z8-7071hpx<06>

<EFBFBD>
Kinstance '%s' of module '%s' has %s connections declared, but only %s given4757*oasys2
	clk_wiz_12
design_1_clk_wiz_1_12

42

32d
`c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
2
4258
@
Z8-7023hpx<06>

<EFBFBD>

Fall outputs are unconnected for this instance and logic may be removed3605*oasys2d
`c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
2
4298
@
Z8-4446hpx<06>

<EFBFBD>

synthesizing module '%s'%s4497*oasys2
design_1_ila_0_02
2<>

<EFBFBD>
C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/.Xil/Vivado-19404-DESKTOP-EB3SDQ2/realtime/design_1_ila_0_0_stub.v
2

68
@
Z8-6157hpx<05>

<EFBFBD>
'done synthesizing module '%s'%s (%s#%s)4495*oasys2
design_1_ila_0_02
2

02

12<31>

<EFBFBD>
C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/.Xil/Vivado-19404-DESKTOP-EB3SDQ2/realtime/design_1_ila_0_0_stub.v
2

68
@
Z8-6155hpx<05>

<EFBFBD>

Fall outputs are unconnected for this instance and logic may be removed3605*oasys2d
`c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
2
4568
@
Z8-4446hpx<06>

<EFBFBD>

synthesizing module '%s'%s4497*oasys2
design_1_ila_1_02
2<>

<EFBFBD>
C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/.Xil/Vivado-19404-DESKTOP-EB3SDQ2/realtime/design_1_ila_1_0_stub.v
2

68
@
Z8-6157hpx<05>

<EFBFBD>
'done synthesizing module '%s'%s (%s#%s)4495*oasys2
design_1_ila_1_02
2

02

12<31>

<EFBFBD>
C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/.Xil/Vivado-19404-DESKTOP-EB3SDQ2/realtime/design_1_ila_1_0_stub.v
2

68
@
Z8-6155hpx<05>

<EFBFBD>

synthesizing module '%s'%s4497*oasys2
design_1_mig_7series_0_02
2<>

<EFBFBD>
C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/.Xil/Vivado-19404-DESKTOP-EB3SDQ2/realtime/design_1_mig_7series_0_0_stub.v
2

68
@
Z8-6157hpx<05>

<EFBFBD>
'done synthesizing module '%s'%s (%s#%s)4495*oasys2
design_1_mig_7series_0_02
2

02

12<31>

<EFBFBD>
C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/.Xil/Vivado-19404-DESKTOP-EB3SDQ2/realtime/design_1_mig_7series_0_0_stub.v
2

68
@
Z8-6155hpx<05>

<EFBFBD>
9port '%s' of module '%s' is unconnected for instance '%s'4818*oasys2

app_sr_active2
design_1_mig_7series_0_02

mig_7series_02d
`c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
2
4618
@
Z8-7071hpx<06>

<EFBFBD>
9port '%s' of module '%s' is unconnected for instance '%s'4818*oasys2
app_ref_ack2
design_1_mig_7series_0_02

mig_7series_02d
`c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
2
4618
@
Z8-7071hpx<06>

<EFBFBD>
9port '%s' of module '%s' is unconnected for instance '%s'4818*oasys2

app_zq_ack2
design_1_mig_7series_0_02

mig_7series_02d
`c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
2
4618
@
Z8-7071hpx<06>

<EFBFBD>
9port '%s' of module '%s' is unconnected for instance '%s'4818*oasys2
	s_axi_bid2
design_1_mig_7series_0_02

mig_7series_02d
`c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
2
4618
@
Z8-7071hpx<06>

<EFBFBD>
9port '%s' of module '%s' is unconnected for instance '%s'4818*oasys2
	s_axi_rid2
design_1_mig_7series_0_02

mig_7series_02d
`c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
2
4618
@
Z8-7071hpx<06>

<EFBFBD>
9port '%s' of module '%s' is unconnected for instance '%s'4818*oasys2
device_temp2
design_1_mig_7series_0_02

mig_7series_02d
`c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
2
4618
@
Z8-7071hpx<06>

<EFBFBD>
Kinstance '%s' of module '%s' has %s connections declared, but only %s given4757*oasys2

mig_7series_02
design_1_mig_7series_0_02
632
572d
`c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
2
4618
@
Z8-7023hpx<06>

<EFBFBD>
synthesizing module '%s'%s4497*oasys2
design_1_proc_sys_reset_0_02
2<>

<EFBFBD>
C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/.Xil/Vivado-19404-DESKTOP-EB3SDQ2/realtime/design_1_proc_sys_reset_0_0_stub.v
2

68
@
Z8-6157hpx<05>

<EFBFBD>
'done synthesizing module '%s'%s (%s#%s)4495*oasys2
design_1_proc_sys_reset_0_02
2

02

12<31>

<EFBFBD>
C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/.Xil/Vivado-19404-DESKTOP-EB3SDQ2/realtime/design_1_proc_sys_reset_0_0_stub.v
2

68
@
Z8-6155hpx<05>

<EFBFBD>
9port '%s' of module '%s' is unconnected for instance '%s'4818*oasys2

mb_reset2
design_1_proc_sys_reset_0_02
proc_sys_reset_02d
`c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
2
5198
@
Z8-7071hpx<06>

<EFBFBD>
9port '%s' of module '%s' is unconnected for instance '%s'4818*oasys2
bus_struct_reset2
design_1_proc_sys_reset_0_02
proc_sys_reset_02d
`c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
2
5198
@
Z8-7071hpx<06>

<EFBFBD>
9port '%s' of module '%s' is unconnected for instance '%s'4818*oasys2
peripheral_reset2
design_1_proc_sys_reset_0_02
proc_sys_reset_02d
`c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
2
5198
@
Z8-7071hpx<06>

<EFBFBD>
9port '%s' of module '%s' is unconnected for instance '%s'4818*oasys2
interconnect_aresetn2
design_1_proc_sys_reset_0_02
proc_sys_reset_02d
`c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
2
5198
@
Z8-7071hpx<06>

<EFBFBD>
Kinstance '%s' of module '%s' has %s connections declared, but only %s given4757*oasys2
proc_sys_reset_02
design_1_proc_sys_reset_0_02
102

62d
`c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
2
5198
@
Z8-7023hpx<06>

<EFBFBD>

synthesizing module '%s'%s4497*oasys2
design_1_smartconnect_0_12
2<>

<EFBFBD>
C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/.Xil/Vivado-19404-DESKTOP-EB3SDQ2/realtime/design_1_smartconnect_0_1_stub.v
2

68
@
Z8-6157hpx<05>

<EFBFBD>
'done synthesizing module '%s'%s (%s#%s)4495*oasys2
design_1_smartconnect_0_12
2

02

12<31>

<EFBFBD>
C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/.Xil/Vivado-19404-DESKTOP-EB3SDQ2/realtime/design_1_smartconnect_0_1_stub.v
2

68
@
Z8-6155hpx<05>

<EFBFBD>
9port '%s' of module '%s' is unconnected for instance '%s'4818*oasys2
S02_AXI_bid2
design_1_smartconnect_0_12
smartconnect_02d
`c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
2
5268
@
Z8-7071hpx<06>

<EFBFBD>
9port '%s' of module '%s' is unconnected for instance '%s'4818*oasys2
S02_AXI_rid2
design_1_smartconnect_0_12
smartconnect_02d
`c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
2
5268
@
Z8-7071hpx<06>

<EFBFBD>
Kinstance '%s' of module '%s' has %s connections declared, but only %s given4757*oasys2
smartconnect_02
design_1_smartconnect_0_12
1472
1452d
`c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
2
5268
@
Z8-7023hpx<06>

<EFBFBD>

Fall outputs are unconnected for this instance and logic may be removed3605*oasys2d
`c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
2
6728
@
Z8-4446hpx<06>

<EFBFBD>

synthesizing module '%s'%s4497*oasys2
design_1_system_ila_0_02
2<>

<EFBFBD>
C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/.Xil/Vivado-19404-DESKTOP-EB3SDQ2/realtime/design_1_system_ila_0_0_stub.v
2

68
@
Z8-6157hpx<05>

<EFBFBD>
'done synthesizing module '%s'%s (%s#%s)4495*oasys2
design_1_system_ila_0_02
2

02

12<31>

<EFBFBD>
C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/.Xil/Vivado-19404-DESKTOP-EB3SDQ2/realtime/design_1_system_ila_0_0_stub.v
2

68
@
Z8-6155hpx<05>

<EFBFBD>

synthesizing module '%s'%s4497*oasys2
design_1_util_ds_buf_0_02
2<>

<EFBFBD>
C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/.Xil/Vivado-19404-DESKTOP-EB3SDQ2/realtime/design_1_util_ds_buf_0_0_stub.v
2

68
@
Z8-6157hpx<05>

<EFBFBD>
'done synthesizing module '%s'%s (%s#%s)4495*oasys2
design_1_util_ds_buf_0_02
2

02

12<31>

<EFBFBD>
C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/.Xil/Vivado-19404-DESKTOP-EB3SDQ2/realtime/design_1_util_ds_buf_0_0_stub.v
2

68
@
Z8-6155hpx<05>

<EFBFBD>

synthesizing module '%s'%s4497*oasys2
design_1_util_ds_buf_1_02
2<>

<EFBFBD>
C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/.Xil/Vivado-19404-DESKTOP-EB3SDQ2/realtime/design_1_util_ds_buf_1_0_stub.v
2

68
@
Z8-6157hpx<05>

<EFBFBD>
'done synthesizing module '%s'%s (%s#%s)4495*oasys2
design_1_util_ds_buf_1_02
2

02

12<31>

<EFBFBD>
C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/.Xil/Vivado-19404-DESKTOP-EB3SDQ2/realtime/design_1_util_ds_buf_1_0_stub.v
2

68
@
Z8-6155hpx<05>

<EFBFBD>
synthesizing module '%s'%s4497*oasys2 
design_1_util_vector_logic_0_32
2<>

<EFBFBD>
C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/.Xil/Vivado-19404-DESKTOP-EB3SDQ2/realtime/design_1_util_vector_logic_0_3_stub.v
2

68
@
Z8-6157hpx<05>

<EFBFBD>
'done synthesizing module '%s'%s (%s#%s)4495*oasys2 
design_1_util_vector_logic_0_32
2

02

12<31>

<EFBFBD>
C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/.Xil/Vivado-19404-DESKTOP-EB3SDQ2/realtime/design_1_util_vector_logic_0_3_stub.v
2

68
@
Z8-6155hpx<05>

<EFBFBD>

'done synthesizing module '%s'%s (%s#%s)4495*oasys2

design_12
2

02

12d
`c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
2
138
@
Z8-6155hpx<05>

<EFBFBD>

'done synthesizing module '%s'%s (%s#%s)4495*oasys2
design_1_wrapper2
2

02

12j
fC:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
2
138
@
Z8-6155hpx<05>

<EFBFBD>
fMark debug on the nets applies keep_hierarchy on instance '%s'. This will prevent further optimization4399*oasys2
ccsds122_datamover_02d
`c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
2
3008
@
Z8-6071hpx<05>

<EFBFBD>
fMark debug on the nets applies keep_hierarchy on instance '%s'. This will prevent further optimization4399*oasys2
ila_02d
`c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
2
4298
@
Z8-6071hpx<05>

<EFBFBD>
fMark debug on the nets applies keep_hierarchy on instance '%s'. This will prevent further optimization4399*oasys2
proc_sys_reset_02d
`c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
2
5198
@
Z8-6071hpx<05>

<EFBFBD>
fMark debug on the nets applies keep_hierarchy on instance '%s'. This will prevent further optimization4399*oasys2
system_ila_02d
`c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
2
6728
@
Z8-6071hpx<05>

<EFBFBD>
fMark debug on the nets applies keep_hierarchy on instance '%s'. This will prevent further optimization4399*oasys2
smartconnect_02d
`c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
2
5268
@
Z8-6071hpx<05>

<EFBFBD>
fMark debug on the nets applies keep_hierarchy on instance '%s'. This will prevent further optimization4399*oasys2

mig_7series_02d
`c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
2
4618
@
Z8-6071hpx<05>

<EFBFBD>
fMark debug on the nets applies keep_hierarchy on instance '%s'. This will prevent further optimization4399*oasys2
ccsds_uart_axi_02d
`c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
2
3708
@
Z8-6071hpx<05>

<EFBFBD>
fMark debug on the nets applies keep_hierarchy on instance '%s'. This will prevent further optimization4399*oasys2
ccsds122_axil_slave_02d
`c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
2
2648
@
Z8-6071hpx<05>

<EFBFBD>
fMark debug on the nets applies keep_hierarchy on instance '%s'. This will prevent further optimization4399*oasys2

design_1_i2j
fC:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
2
768
@
Z8-6071hpx<05>

<EFBFBD>
fMark debug on the nets applies keep_hierarchy on instance '%s'. This will prevent further optimization4399*oasys2
ila_12d
`c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
2
4568
@
Z8-6071hpx<05>

<EFBFBD>

%s*synth2{
yFinished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1924.391 ; gain = 560.082
hpx<0C>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

;
%s
*synth2#
!Start Handling Custom Attributes
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

<EFBFBD>

%s*synth2<68>

<EFBFBD>
Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1924.391 ; gain = 560.082
hpx<0C>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

<EFBFBD>

%s*synth2<68>

<EFBFBD>
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1924.391 ; gain = 560.082
hpx<0C>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

<EFBFBD>

I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2
Netlist sorting complete. 2

00:00:002
00:00:00.0112

1924.3912
0.000Z17-268hpx<0C>

K
)Preparing netlist for logic optimization
349*projectZ1-570hpx<05>

>

Processing XDC Constraints
244*projectZ1-262hpx<04>

=
Initializing timing engine
348*projectZ1-569hpx<04>

<EFBFBD>
$Parsing XDC File [%s] for cell '%s'
848*designutils2<73>

<EFBFBD>
c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/design_1_ccsds122_datamover_0_0/design_1_ccsds122_datamover_0_0_in_context.xdc
2#
design_1_i/ccsds122_datamover_0	8
Z20-848hpx<04>

<EFBFBD>
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2<73>

<EFBFBD>
c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/design_1_ccsds122_datamover_0_0/design_1_ccsds122_datamover_0_0_in_context.xdc
2#
design_1_i/ccsds122_datamover_0	8
Z20-847hpx<04>

<EFBFBD>
$Parsing XDC File [%s] for cell '%s'
848*designutils2<73>

<EFBFBD>
c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1/design_1_smartconnect_0_1_in_context.xdc
2
design_1_i/smartconnect_0	8
Z20-848hpx<04>

<EFBFBD>
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2<73>

<EFBFBD>
c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1/design_1_smartconnect_0_1_in_context.xdc
2
design_1_i/smartconnect_0	8
Z20-847hpx<04>

<EFBFBD>
$Parsing XDC File [%s] for cell '%s'
848*designutils2<73>

<EFBFBD>
c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_axil_slave_0_0/design_1_ccsds122_axil_slave_0_0/design_1_ccsds122_axil_slave_0_0_in_context.xdc
2$
 design_1_i/ccsds122_axil_slave_0	8
Z20-848hpx<04>

<EFBFBD>
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2<73>

<EFBFBD>
c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_axil_slave_0_0/design_1_ccsds122_axil_slave_0_0/design_1_ccsds122_axil_slave_0_0_in_context.xdc
2$
 design_1_i/ccsds122_axil_slave_0	8
Z20-847hpx<04>

<EFBFBD>

$Parsing XDC File [%s] for cell '%s'
848*designutils2<73>

<EFBFBD>
c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ila_0_0/design_1_ila_0_0/design_1_ila_0_0_in_context.xdc
2
design_1_i/ila_0	8
Z20-848hpx<04>

<EFBFBD>
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2<73>

<EFBFBD>
c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ila_0_0/design_1_ila_0_0/design_1_ila_0_0_in_context.xdc
2
design_1_i/ila_0	8
Z20-847hpx<04>

<EFBFBD>
$Parsing XDC File [%s] for cell '%s'
848*designutils2<73>

<EFBFBD>
c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0/design_1_system_ila_0_0_in_context.xdc
2
design_1_i/system_ila_0	8
Z20-848hpx<04>

<EFBFBD>
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2<73>

<EFBFBD>
c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0/design_1_system_ila_0_0_in_context.xdc
2
design_1_i/system_ila_0	8
Z20-847hpx<04>

<EFBFBD>
$Parsing XDC File [%s] for cell '%s'
848*designutils2<73>

<EFBFBD>
c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0_in_context.xdc
2
design_1_i/proc_sys_reset_0	8
Z20-848hpx<04>

<EFBFBD>
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2<73>

<EFBFBD>
c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0_in_context.xdc
2
design_1_i/proc_sys_reset_0	8
Z20-847hpx<04>

<EFBFBD>
$Parsing XDC File [%s] for cell '%s'
848*designutils2<73>

<EFBFBD>
c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_3/design_1_util_vector_logic_0_3/design_1_util_vector_logic_0_3_in_context.xdc
2"
design_1_i/util_vector_logic_0	8
Z20-848hpx<04>

<EFBFBD>
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2<73>

<EFBFBD>
c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_3/design_1_util_vector_logic_0_3/design_1_util_vector_logic_0_3_in_context.xdc
2"
design_1_i/util_vector_logic_0	8
Z20-847hpx<04>

<EFBFBD>
$Parsing XDC File [%s] for cell '%s'
848*designutils2<73>

<EFBFBD>
c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/design_1_mig_7series_0_0_in_context.xdc
2
design_1_i/mig_7series_0	8
Z20-848hpx<04>

<EFBFBD>
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2<73>

<EFBFBD>
c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/design_1_mig_7series_0_0_in_context.xdc
2
design_1_i/mig_7series_0	8
Z20-847hpx<04>

<EFBFBD>
$Parsing XDC File [%s] for cell '%s'
848*designutils2<73>

<EFBFBD>
c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/design_1_ccsds_uart_axi_0_0/design_1_ccsds_uart_axi_0_0_in_context.xdc
2
design_1_i/ccsds_uart_axi_0	8
Z20-848hpx<04>

<EFBFBD>
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2<73>

<EFBFBD>
c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/design_1_ccsds_uart_axi_0_0/design_1_ccsds_uart_axi_0_0_in_context.xdc
2
design_1_i/ccsds_uart_axi_0	8
Z20-847hpx<04>

<EFBFBD>
$Parsing XDC File [%s] for cell '%s'
848*designutils2<73>

<EFBFBD>
c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_util_ds_buf_0_0/design_1_util_ds_buf_0_0/design_1_util_ds_buf_0_0_in_context.xdc
2
design_1_i/util_ds_buf_0	8
Z20-848hpx<04>

<EFBFBD>
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2<73>

<EFBFBD>
c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_util_ds_buf_0_0/design_1_util_ds_buf_0_0/design_1_util_ds_buf_0_0_in_context.xdc
2
design_1_i/util_ds_buf_0	8
Z20-847hpx<04>

<EFBFBD>
$Parsing XDC File [%s] for cell '%s'
848*designutils2<73>

<EFBFBD>
c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_1_1/design_1_clk_wiz_1_1/design_1_clk_wiz_1_1_in_context.xdc
2
design_1_i/clk_wiz_1	8
Z20-848hpx<04>

<EFBFBD>
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2<73>

<EFBFBD>
c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_1_1/design_1_clk_wiz_1_1/design_1_clk_wiz_1_1_in_context.xdc
2
design_1_i/clk_wiz_1	8
Z20-847hpx<04>

<EFBFBD>

$Parsing XDC File [%s] for cell '%s'
848*designutils2<73>

<EFBFBD>
c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ila_1_0/design_1_ila_1_0/design_1_ila_1_0_in_context.xdc
2
design_1_i/ila_1	8
Z20-848hpx<04>

<EFBFBD>
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2<73>

<EFBFBD>
c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ila_1_0/design_1_ila_1_0/design_1_ila_1_0_in_context.xdc
2
design_1_i/ila_1	8
Z20-847hpx<04>

<EFBFBD>
$Parsing XDC File [%s] for cell '%s'
848*designutils2<73>

<EFBFBD>
c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_util_ds_buf_1_0/design_1_util_ds_buf_1_0/design_1_util_ds_buf_1_0_in_context.xdc
2
design_1_i/util_ds_buf_1	8
Z20-848hpx<04>

<EFBFBD>
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2<73>

<EFBFBD>
c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_util_ds_buf_1_0/design_1_util_ds_buf_1_0/design_1_util_ds_buf_1_0_in_context.xdc
2
design_1_i/util_ds_buf_1	8
Z20-847hpx<04>

<EFBFBD>

Parsing XDC File [%s]
179*designutils2a
]C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/constrs_1/new/ccsds122_storage.xdc
8
Z20-179hpx<04>

<EFBFBD>

No nets matched '%s'.
507*	planAhead2)
'design_1_i/util_ds_buf_0/U0/IBUF_OUT[0]2a
]C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/constrs_1/new/ccsds122_storage.xdc
2
148
@
Z12-507hpx<06>


<EFBFBD>

Finished Parsing XDC File [%s]
178*designutils2a
]C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/constrs_1/new/ccsds122_storage.xdc
8
Z20-178hpx<04>

<EFBFBD>
<EFBFBD>One or more constraints failed evaluation while reading constraint file [%s] and the design contains unresolved black boxes. These constraints will be read post-synthesis (as long as their source constraint file is marked as used_in_implementation) and should be applied correctly then. You should review the constraints listed in the file [%s] and check the run log file to verify that these constraints were correctly applied.301*project2_
]C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/constrs_1/new/ccsds122_storage.xdc2$
".Xil/design_1_wrapper_propImpl.xdcZ1-498hpx<06>

<EFBFBD>
<EFBFBD>
Implementation specific constraints were found while reading constraint file [%s]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [%s].
233*project2_
]C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/constrs_1/new/ccsds122_storage.xdc2$
".Xil/design_1_wrapper_propImpl.xdcZ1-236hpx<05>

<EFBFBD>

Parsing XDC File [%s]
179*designutils2U
QC:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/dont_touch.xdc
8
Z20-179hpx<04>

<EFBFBD>

Finished Parsing XDC File [%s]
178*designutils2U
QC:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/dont_touch.xdc
8
Z20-178hpx<04>

H
&Completed Processing XDC Constraints

245*projectZ1-263hpx<04>

<EFBFBD>

I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2
Netlist sorting complete. 2

00:00:002
00:00:00.0012

1943.7702
0.000Z17-268hpx<0C>

l
!Unisim Transformation Summary:
%s111*project2'
%No Unisim elements were transformed.
Z1-111hpx<05>

<EFBFBD>

I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2"
 Constraint Validation Runtime : 2

00:00:002
00:00:00.0082

1943.7702
0.000Z17-268hpx<0C>


VNo compile time benefit to using incremental synthesis; A full resynthesis will be run2353*designutilsZ20-5440hpx<05>

<EFBFBD>
<EFBFBD>
Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}2229*designutilsZ20-4379hpx<05>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

<EFBFBD>

%s*synth2<68>

Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1943.770 ; gain = 579.461
hpx<0C>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

D
%s
*synth2,
*Start Loading Part and Timing Information
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

;
%s
*synth2#
!Loading part: xc7vx690tffg1761-2
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

<EFBFBD>

%s*synth2<68>

<EFBFBD>
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1943.770 ; gain = 579.461
hpx<0C>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

H
%s
*synth20
.Start Applying 'set_property' XDC Constraints
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

<EFBFBD>

%s*synth2<68>

<EFBFBD>
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1943.770 ; gain = 579.461
hpx<0C>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

<EFBFBD>

%s*synth2<68>

<EFBFBD>
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1943.770 ; gain = 579.461
hpx<0C>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

:
%s
*synth2"
 Start RTL Component Statistics 
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

9
%s
*synth2!
Detailed RTL Component Info : 
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

=
%s
*synth2%
#Finished RTL Component Statistics 
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

6
%s
*synth2
Start Part Resource Summary
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

v
%s
*synth2^
\Part Resources:
DSPs: 3600 (col length:200)
BRAMs: 2940 (col length: RAMB18 200 RAMB36 100)
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

9
%s
*synth2!
Finished Part Resource Summary
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

E
%s
*synth2-
+Start Cross Boundary and Area Optimization
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

H
&Parallel synthesis criteria is not met4829*oasysZ8-7080hpx<06>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

<EFBFBD>

%s*synth2<68>

<EFBFBD>
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1943.770 ; gain = 579.461
hpx<0C>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

@
%s
*synth2(
&Start Applying XDC Timing Constraints
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

<EFBFBD>

%s*synth2<68>

<EFBFBD>
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 1943.770 ; gain = 579.461
hpx<0C>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

4
%s
*synth2
Start Timing Optimization
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

<EFBFBD>

%s*synth2
}Finished Timing Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 1943.770 ; gain = 579.461
hpx<0C>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

3
%s
*synth2
Start Technology Mapping
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

<EFBFBD>

%s*synth2~
|Finished Technology Mapping : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 1943.770 ; gain = 579.461
hpx<0C>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

-
%s
*synth2
Start IO Insertion
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

?
%s
*synth2'
%Start Flattening Before IO Insertion
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

B
%s
*synth2*
(Finished Flattening Before IO Insertion
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

6
%s
*synth2
Start Final Netlist Cleanup
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

9
%s
*synth2!
Finished Final Netlist Cleanup
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

<EFBFBD>

%s*synth2x
vFinished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1943.770 ; gain = 579.461
hpx<0C>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

=
%s
*synth2%
#Start Renaming Generated Instances
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

<EFBFBD>

%s*synth2<68>

<EFBFBD>
Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1943.770 ; gain = 579.461
hpx<0C>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

:
%s
*synth2"
 Start Rebuilding User Hierarchy
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

<EFBFBD>

%s*synth2<68>

<EFBFBD>
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1943.770 ; gain = 579.461
hpx<0C>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

9
%s
*synth2!
Start Renaming Generated Ports
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

<EFBFBD>

%s*synth2<68>

<EFBFBD>
Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1943.770 ; gain = 579.461
hpx<0C>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

;
%s
*synth2#
!Start Handling Custom Attributes
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

<EFBFBD>

%s*synth2<68>

<EFBFBD>
Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1943.770 ; gain = 579.461
hpx<0C>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

8
%s
*synth2 
Start Renaming Generated Nets
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

<EFBFBD>

%s*synth2<68>

<EFBFBD>
Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1943.770 ; gain = 579.461
hpx<0C>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

9
%s
*synth2!
Start Writing Synthesis Report
hp
x
<EFBFBD>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

/
%s
*synth2

Report BlackBoxes: 
hp
x
<EFBFBD>

P
%s
*synth28
6+------+---------------------------------+----------+
hp
x
<EFBFBD>

P
%s
*synth28
6|      |BlackBox name                    |Instances |
hp
x
<EFBFBD>

P
%s
*synth28
6+------+---------------------------------+----------+
hp
x
<EFBFBD>

P
%s
*synth28
6|1     |design_1_ccsds122_axil_slave_0_0 |         1|
hp
x
<EFBFBD>

P
%s
*synth28
6|2     |design_1_ccsds122_datamover_0_0  |         1|
hp
x
<EFBFBD>

P
%s
*synth28
6|3     |design_1_ccsds_uart_axi_0_0      |         1|
hp
x
<EFBFBD>

P
%s
*synth28
6|4     |design_1_clk_wiz_1_1             |         1|
hp
x
<EFBFBD>

P
%s
*synth28
6|5     |design_1_ila_0_0                 |         1|
hp
x
<EFBFBD>

P
%s
*synth28
6|6     |design_1_ila_1_0                 |         1|
hp
x
<EFBFBD>

P
%s
*synth28
6|7     |design_1_mig_7series_0_0         |         1|
hp
x
<EFBFBD>

P
%s
*synth28
6|8     |design_1_proc_sys_reset_0_0      |         1|
hp
x
<EFBFBD>

P
%s
*synth28
6|9     |design_1_smartconnect_0_1        |         1|
hp
x
<EFBFBD>

P
%s
*synth28
6|10    |design_1_system_ila_0_0          |         1|
hp
x
<EFBFBD>

P
%s
*synth28
6|11    |design_1_util_ds_buf_0_0         |         1|
hp
x
<EFBFBD>

P
%s
*synth28
6|12    |design_1_util_ds_buf_1_0         |         1|
hp
x
<EFBFBD>

P
%s
*synth28
6|13    |design_1_util_vector_logic_0_3   |         1|
hp
x
<EFBFBD>

P
%s
*synth28
6+------+---------------------------------+----------+
hp
x
<EFBFBD>

/
%s*synth2

Report Cell Usage: 
hpx<0C>

J
%s*synth22
0+------+-------------------------------+------+
hpx<0C>

J
%s*synth22
0|      |Cell                           |Count |
hpx<0C>

J
%s*synth22
0+------+-------------------------------+------+
hpx<0C>

J
%s*synth22
0|1     |design_1_ccsds122_axil_slave_0 |     1|
hpx<0C>

J
%s*synth22
0|2     |design_1_ccsds122_datamover_0  |     1|
hpx<0C>

J
%s*synth22
0|3     |design_1_ccsds_uart_axi_0      |     1|
hpx<0C>

J
%s*synth22
0|4     |design_1_clk_wiz_1             |     1|
hpx<0C>

J
%s*synth22
0|5     |design_1_ila_0                 |     1|
hpx<0C>

J
%s*synth22
0|6     |design_1_ila_1                 |     1|
hpx<0C>

J
%s*synth22
0|7     |design_1_mig_7series_0         |     1|
hpx<0C>

J
%s*synth22
0|8     |design_1_proc_sys_reset_0      |     1|
hpx<0C>

J
%s*synth22
0|9     |design_1_smartconnect_0        |     1|
hpx<0C>

J
%s*synth22
0|10    |design_1_system_ila_0          |     1|
hpx<0C>

J
%s*synth22
0|11    |design_1_util_ds_buf_0         |     1|
hpx<0C>

J
%s*synth22
0|12    |design_1_util_ds_buf_1         |     1|
hpx<0C>

J
%s*synth22
0|13    |design_1_util_vector_logic_0   |     1|
hpx<0C>

J
%s*synth22
0|14    |IBUF                           |     2|
hpx<0C>

J
%s*synth22
0|15    |OBUF                           |     1|
hpx<0C>

J
%s*synth22
0+------+-------------------------------+------+
hpx<0C>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

<EFBFBD>

%s*synth2<68>

<EFBFBD>
Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1943.770 ; gain = 579.461
hpx<0C>

l
%s
*synth2T
R---------------------------------------------------------------------------------
hp
x
<EFBFBD>

`
%s
*synth2H
FSynthesis finished with 0 errors, 0 critical warnings and 1 warnings.
hp
x
<EFBFBD>

<EFBFBD>

%s
*synth2<68>

Synthesis Optimization Runtime : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1943.770 ; gain = 560.082
hp
x
<EFBFBD>

<EFBFBD>

%s
*synth2<68>

<EFBFBD>
Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1943.770 ; gain = 579.461
hp
x
<EFBFBD>

B
 Translating synthesized netlist
350*projectZ1-571hpx<05>

<EFBFBD>

I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2
Netlist sorting complete. 2

00:00:002
00:00:00.0122

1943.7702
0.000Z17-268hpx<0C>

K
)Preparing netlist for logic optimization
349*projectZ1-570hpx<05>

Q
)Pushed %s inverter(s) to %s load pin(s).
98*opt2

02

0Z31-138hpx<05>

<EFBFBD>

I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2
Netlist sorting complete. 2

00:00:002

00:00:002

1951.1022
0.000Z17-268hpx<0C>

l
!Unisim Transformation Summary:
%s111*project2'
%No Unisim elements were transformed.
Z1-111hpx<05>

V
%Synth Design complete | Checksum: %s
562*	vivadotcl2

5da95f05Z4-1430hpx<04>

C
Releasing license: %s
83*common2
	SynthesisZ17-83hpx<05>


G%s Infos, %s Warnings, %s Critical Warnings and %s Errors encountered.
28*	vivadotcl2
622
232

02

0Z4-41hpx<04>

L
%s completed successfully
29*	vivadotcl2
synth_designZ4-42hpx<04>

<EFBFBD>

I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2
synth_design: 2

00:00:212

00:00:232

1951.1022

1187.555Z17-268hpx<0C>

<EFBFBD>

I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2
Write ShapeDB Complete: 2

00:00:002

00:00:002

1951.1022
0.000Z17-268hpx<0C>

<EFBFBD>

 The %s '%s' has been generated.
621*common2

checkpoint2Y
WC:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1/design_1_wrapper.dcpZ17-1381hpx<05>

<EFBFBD>

%s
4*runtcl2x
vExecuting : report_utilization -file design_1_wrapper_utilization_synth.rpt -pb design_1_wrapper_utilization_synth.pb
hpx<05>

\
Exiting %s at %s...
206*common2
Vivado2
Sat Jul  4 17:13:36 2026Z17-206hpx<05>



End Record