986 lines
80 KiB
Plaintext
986 lines
80 KiB
Plaintext
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#-----------------------------------------------------------
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# Vivado v2023.2 (64-bit)
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# SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023
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# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
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# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
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# Start of session at: Sun Jul 5 16:02:55 2026
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# Process ID: 33620
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# Current directory: C:/proj/xc7v_ccsds122_datamover_uart
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# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent38164 C:\proj\xc7v_ccsds122_datamover_uart\ccsds122_storage.xpr
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# Log file: C:/proj/xc7v_ccsds122_datamover_uart/vivado.log
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# Journal file: C:/proj/xc7v_ccsds122_datamover_uart\vivado.jou
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# Running On: DESKTOP-EB3SDQ2, OS: Windows, CPU Frequency: 2112 MHz, CPU Physical cores: 16, Host memory: 16817 MB
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#-----------------------------------------------------------
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start_gui
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open_project C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.xpr
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update_compile_order -fileset sources_1
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launch_simulation
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launch_simulation
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source tb_design_1_wrapper.tcl
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current_wave_config {Untitled 1}
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add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl}}
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current_wave_config {Untitled 1}
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add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_bubble_removal}}
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current_wave_config {Untitled 1}
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add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/ccsds122_axil_slave_0}}
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current_wave_config {Untitled 1}
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add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/ccsds_uart_axi_0}}
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current_wave_config {Untitled 1}
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add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/ccsds_uart_axi_0/inst/u_core}}
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restart
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run 7 ms
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run 7 ms
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open_bd_design {C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd}
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close_bd_design [get_bd_designs design_1]
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run 7 ms
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current_wave_config {Untitled 1}
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add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/ccsds122_datamover_0/inst/u_datamover}}
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current_wave_config {Untitled 1}
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add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/ccsds122_datamover_0/inst}}
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current_wave_config {Untitled 1}
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add_wave {{/tb_design_1_wrapper/u_dut}}
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close_sim
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open_bd_design {C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd}
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open_run synth_1_copy_1 -name synth_1_copy_1
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report_utilization -name utilization_1
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open_bd_design {C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd}
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delete_bd_objs [get_bd_intf_nets ccsds_uart_axi_0_m_axil]
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connect_bd_intf_net [get_bd_intf_pins ccsds_uart_axi_0/m_axil] [get_bd_intf_pins smartconnect_0/S03_AXI]
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connect_bd_intf_net [get_bd_intf_pins system_ila_0/SLOT_3_AXI] [get_bd_intf_pins smartconnect_0/M01_AXI]
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delete_bd_objs [get_bd_intf_nets ccsds_uart_axi_0_m_axi]
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undo
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open_bd_design {C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd}
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delete_bd_objs [get_bd_intf_nets ccsds_uart_axi_0_m_axi]
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connect_bd_intf_net [get_bd_intf_pins ccsds_uart_axi_0/m_axi] [get_bd_intf_pins smartconnect_0/S02_AXI]
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startgroup
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set_property CONFIG.C_NUM_MONITOR_SLOTS {3} [get_bd_cells system_ila_0]
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endgroup
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connect_bd_intf_net [get_bd_intf_pins system_ila_0/SLOT_2_AXI] [get_bd_intf_pins smartconnect_0/M01_AXI]
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copy_bd_objs / [get_bd_cells {system_ila_0}]
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set_property CONFIG.C_NUM_MONITOR_SLOTS {1} [get_bd_cells system_ila_1]
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connect_bd_intf_net [get_bd_intf_pins system_ila_1/SLOT_0_AXI] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI]
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connect_bd_net [get_bd_pins system_ila_1/clk] [get_bd_pins ddr4_0/c0_ddr4_ui_clk]
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connect_bd_net [get_bd_pins system_ila_1/resetn] [get_bd_pins proc_sys_reset_0/peripheral_aresetn]
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regenerate_bd_layout
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validate_bd_design
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generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
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catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
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catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
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catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_1] }
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export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
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create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
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export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
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reset_run synth_1_copy_1
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launch_runs impl_2 -to_step write_bitstream -jobs 24
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wait_on_run impl_2
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report_utilization -name utilization_2
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close_design
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open_run synth_1_copy_1 -name synth_1_copy_1
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report_utilization -name utilization_1
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close_design
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delete_bd_objs [get_bd_nets ccsds122_datamover_0_compress_base_addr_out]
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delete_bd_objs [get_bd_nets ccsds122_datamover_0_compress_image_len]
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delete_bd_objs [get_bd_nets ccsds122_datamover_0_s2mm_total_bytes]
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delete_bd_objs [get_bd_nets ccsds122_axil_slave_0_compress_base_addr]
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connect_bd_net [get_bd_pins ccsds122_axil_slave_0/compress_base_addr] [get_bd_pins ccsds122_datamover_0/compress_base_addr]
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delete_bd_objs [get_bd_nets ccsds122_axil_slave_0_flaw_image_addr]
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connect_bd_net [get_bd_pins ccsds122_axil_slave_0/flaw_image_addr] [get_bd_pins ccsds122_datamover_0/flaw_image_addr]
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startgroup
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set_property -dict [list \
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CONFIG.C_NUM_OF_PROBES {23} \
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CONFIG.C_PROBE2_WIDTH {1} \
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CONFIG.C_PROBE5_WIDTH {1} \
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] [get_bd_cells ila_0]
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delete_bd_objs [get_bd_nets ccsds122_datamover_0_compress_b3_base_addr] [get_bd_nets ccsds122_datamover_0_compress_b4_base_addr]
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endgroup
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connect_bd_net [get_bd_pins ccsds122_datamover_0/compress_b3_base_addr] [get_bd_pins ila_0/probe8]
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connect_bd_net [get_bd_pins ccsds122_datamover_0/compress_b4_base_addr] [get_bd_pins ila_0/probe10]
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connect_bd_net [get_bd_pins ila_0/probe2] [get_bd_pins ddr4_0/c0_init_calib_complete]
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connect_bd_net [get_bd_pins ila_0/probe5] [get_bd_pins ddr4_0/c0_ddr4_ui_clk_sync_rst]
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undo
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connect_bd_net [get_bd_pins ddr4_0/c0_ddr4_ui_clk_sync_rst] [get_bd_pins ila_0/probe5]
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regenerate_bd_layout
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validate_bd_design
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generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
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catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
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catch { config_ip_cache -export [get_ips -all design_1_ila_0_0] }
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catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
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catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_1] }
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export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
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create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
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launch_runs design_1_ila_0_0_synth_1 -jobs 24
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wait_on_run design_1_ila_0_0_synth_1
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export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
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connect_bd_net [get_bd_pins ccsds122_datamover_0/s2mm_total_bytes] [get_bd_pins ccsds122_axil_slave_0/s2mm_total_bytes]
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connect_bd_net [get_bd_pins ccsds122_axil_slave_0/compress_image_len] [get_bd_pins ccsds122_datamover_0/compress_image_len]
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regenerate_bd_layout
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regenerate_bd_layout
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validate_bd_design
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generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
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catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
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catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
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catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_1] }
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export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
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create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
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export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
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update_ip_catalog -rebuild -scan_changes
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report_ip_status -name ip_status
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upgrade_ip [get_ips {design_1_ccsds122_datamover_0_0 design_1_ccsds122_axil_slave_0_0}] -log ip_upgrade.log
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export_ip_user_files -of_objects [get_ips {design_1_ccsds122_datamover_0_0 design_1_ccsds122_axil_slave_0_0}] -no_script -sync -force -quiet
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connect_bd_net [get_bd_pins ccsds122_axil_slave_0/max_images_per_region] [get_bd_pins ccsds122_datamover_0/max_images_per_region]
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update_ip_catalog -rebuild -scan_changes
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report_ip_status -name ip_status
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upgrade_ip -vlnv xilinx.com:user:ccsds122_datamover:1.0 [get_ips design_1_ccsds122_datamover_0_0] -log ip_upgrade.log
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export_ip_user_files -of_objects [get_ips design_1_ccsds122_datamover_0_0] -no_script -sync -force -quiet
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startgroup
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set_property CONFIG.MAX_IMAGES_PER_REGION {0xff} [get_bd_cells ccsds122_datamover_0]
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endgroup
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report_ip_status -name ip_status
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startgroup
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set_property CONFIG.C_NUM_OF_PROBES {24} [get_bd_cells ila_0]
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endgroup
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connect_bd_net [get_bd_pins ila_0/probe23] [get_bd_pins ccsds122_axil_slave_0/max_images_per_region]
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regenerate_bd_layout
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validate_bd_design
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report_ip_status -name ip_status
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generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
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catch { config_ip_cache -export [get_ips -all design_1_ccsds122_datamover_0_0] }
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catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
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catch { config_ip_cache -export [get_ips -all design_1_ccsds122_axil_slave_0_0] }
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catch { config_ip_cache -export [get_ips -all design_1_ila_0_0] }
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catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
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catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_1] }
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export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
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create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
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launch_runs design_1_ccsds122_axil_slave_0_0_synth_1 design_1_ccsds122_datamover_0_0_synth_1 design_1_ila_0_0_synth_1 -jobs 24
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wait_on_run design_1_ccsds122_axil_slave_0_0_synth_1
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wait_on_run design_1_ccsds122_datamover_0_0_synth_1
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wait_on_run design_1_ila_0_0_synth_1
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export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
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update_ip_catalog -rebuild -scan_changes
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report_ip_status -name ip_status
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upgrade_ip -vlnv xilinx.com:user:ccsds_uart_axi:1.0 [get_ips design_1_ccsds_uart_axi_0_0] -log ip_upgrade.log
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export_ip_user_files -of_objects [get_ips design_1_ccsds_uart_axi_0_0] -no_script -sync -force -quiet
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generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
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catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
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catch { config_ip_cache -export [get_ips -all design_1_ccsds_uart_axi_0_0] }
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|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_1] }
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
||
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
launch_runs design_1_ccsds_uart_axi_0_0_synth_1 -jobs 24
|
||
|
|
wait_on_run design_1_ccsds_uart_axi_0_0_synth_1
|
||
|
|
export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
||
|
|
startgroup
|
||
|
|
set_property CONFIG.C_PROBE23_WIDTH {8} [get_bd_cells ila_0]
|
||
|
|
endgroup
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
regenerate_bd_layout
|
||
|
|
validate_bd_design
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_ila_0_0] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_1] }
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
||
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
launch_runs design_1_ila_0_0_synth_1 -jobs 24
|
||
|
|
wait_on_run design_1_ila_0_0_synth_1
|
||
|
|
export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
||
|
|
reset_run synth_1_copy_1
|
||
|
|
launch_runs impl_2 -to_step write_bitstream -jobs 24
|
||
|
|
wait_on_run impl_2
|
||
|
|
launch_simulation
|
||
|
|
source tb_design_1_wrapper.tcl
|
||
|
|
current_wave_config {Untitled 2}
|
||
|
|
add_wave {{/tb_design_1_wrapper}}
|
||
|
|
current_wave_config {Untitled 2}
|
||
|
|
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/ccsds122_axil_slave_0}}
|
||
|
|
current_wave_config {Untitled 2}
|
||
|
|
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl}}
|
||
|
|
current_wave_config {Untitled 2}
|
||
|
|
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/ccsds_uart_axi_0/inst/u_core}}
|
||
|
|
current_wave_config {Untitled 2}
|
||
|
|
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0}}
|
||
|
|
restart
|
||
|
|
run 7 ms
|
||
|
|
run 7 ms
|
||
|
|
current_wave_config {Untitled 2}
|
||
|
|
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/ccsds_uart_axi_0/inst/u_core}}
|
||
|
|
close_sim
|
||
|
|
launch_simulation
|
||
|
|
source tb_design_1_wrapper.tcl
|
||
|
|
current_wave_config {Untitled 3}
|
||
|
|
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl}}
|
||
|
|
current_wave_config {Untitled 3}
|
||
|
|
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/ccsds122_axil_slave_0}}
|
||
|
|
current_wave_config {Untitled 3}
|
||
|
|
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/ccsds_uart_axi_0/inst/u_core}}
|
||
|
|
current_wave_config {Untitled 3}
|
||
|
|
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/smartconnect_0}}
|
||
|
|
restart
|
||
|
|
run 7 ms
|
||
|
|
run 7 ms
|
||
|
|
current_wave_config {Untitled 3}
|
||
|
|
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/ccsds_uart_axi_0/inst/u_core}}
|
||
|
|
close_sim
|
||
|
|
launch_simulation
|
||
|
|
source tb_design_1_wrapper.tcl
|
||
|
|
current_wave_config {Untitled 4}
|
||
|
|
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/ccsds_uart_axi_0/inst/u_core}}
|
||
|
|
restart
|
||
|
|
run 7 ms
|
||
|
|
run 7 ms
|
||
|
|
close_sim
|
||
|
|
update_ip_catalog -rebuild -scan_changes
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
upgrade_ip -vlnv xilinx.com:user:ccsds_uart_axi:1.0 [get_ips design_1_ccsds_uart_axi_0_0] -log ip_upgrade.log
|
||
|
|
export_ip_user_files -of_objects [get_ips design_1_ccsds_uart_axi_0_0] -no_script -sync -force -quiet
|
||
|
|
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_ccsds_uart_axi_0_0] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_1] }
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
||
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
launch_runs design_1_ccsds_uart_axi_0_0_synth_1 -jobs 24
|
||
|
|
wait_on_run design_1_ccsds_uart_axi_0_0_synth_1
|
||
|
|
export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
launch_simulation
|
||
|
|
source tb_design_1_wrapper.tcl
|
||
|
|
current_wave_config {Untitled 5}
|
||
|
|
add_wave {{/tb_design_1_wrapper/u_dut/design_1_i/ccsds_uart_axi_0/inst/u_core}}
|
||
|
|
restart
|
||
|
|
run 7 ms
|
||
|
|
run 7 ms
|
||
|
|
close_sim
|
||
|
|
update_ip_catalog -rebuild
|
||
|
|
startgroup
|
||
|
|
create_bd_cell -type ip -vlnv xilinx.com:user:axi_image_gen:1.0 axi_image_gen_0
|
||
|
|
endgroup
|
||
|
|
startgroup
|
||
|
|
set_property CONFIG.NUM_SI {5} [get_bd_cells smartconnect_0]
|
||
|
|
endgroup
|
||
|
|
connect_bd_intf_net [get_bd_intf_pins axi_image_gen_0/m_axi] [get_bd_intf_pins smartconnect_0/S04_AXI]
|
||
|
|
connect_bd_net [get_bd_pins axi_image_gen_0/clk] [get_bd_pins ddr4_0/addn_ui_clkout1]
|
||
|
|
connect_bd_net [get_bd_pins axi_image_gen_0/rst_n] [get_bd_pins proc_sys_reset_0/peripheral_aresetn]
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
update_ip_catalog -rebuild -scan_changes
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
upgrade_ip -vlnv xilinx.com:user:ccsds122_axil_slave:1.0 [get_ips design_1_ccsds122_axil_slave_0_0] -log ip_upgrade.log
|
||
|
|
export_ip_user_files -of_objects [get_ips design_1_ccsds122_axil_slave_0_0] -no_script -sync -force -quiet
|
||
|
|
connect_bd_net [get_bd_pins ccsds122_axil_slave_0/img_src_sel] [get_bd_pins axi_image_gen_0/img_src_sel]
|
||
|
|
startgroup
|
||
|
|
connect_bd_net [get_bd_pins ccsds122_axil_slave_0/img_gen_start] [get_bd_pins axi_image_gen_0/start]
|
||
|
|
endgroup
|
||
|
|
connect_bd_net [get_bd_pins ccsds122_axil_slave_0/img_rows] [get_bd_pins axi_image_gen_0/img_rows_in]
|
||
|
|
connect_bd_net [get_bd_pins ccsds122_axil_slave_0/memory_block_size] [get_bd_pins axi_image_gen_0/mode]
|
||
|
|
startgroup
|
||
|
|
connect_bd_net [get_bd_pins axi_image_gen_0/block_mb] [get_bd_pins ccsds122_axil_slave_0/memory_block_size]
|
||
|
|
endgroup
|
||
|
|
undo
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
update_ip_catalog -rebuild -scan_changes
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
upgrade_ip -vlnv xilinx.com:user:ccsds122_axil_slave:1.0 [get_ips design_1_ccsds122_axil_slave_0_0] -log ip_upgrade.log
|
||
|
|
export_ip_user_files -of_objects [get_ips design_1_ccsds122_axil_slave_0_0] -no_script -sync -force -quiet
|
||
|
|
delete_bd_objs [get_bd_nets ccsds122_axil_slave_0_memory_block_size]
|
||
|
|
connect_bd_net [get_bd_pins axi_image_gen_0/mode] [get_bd_pins ccsds122_axil_slave_0/storage_mode]
|
||
|
|
connect_bd_net [get_bd_pins ccsds122_axil_slave_0/memory_block_size] [get_bd_pins ccsds122_datamover_0/memory_block_size]
|
||
|
|
connect_bd_net [get_bd_pins ccsds122_axil_slave_0/memory_block_size] [get_bd_pins axi_image_gen_0/block_mb]
|
||
|
|
startgroup
|
||
|
|
connect_bd_net [get_bd_pins axi_image_gen_0/img_per_region] [get_bd_pins ccsds122_axil_slave_0/max_images_per_region]
|
||
|
|
endgroup
|
||
|
|
connect_bd_net [get_bd_pins axi_image_gen_0/done_o] [get_bd_pins ccsds122_axil_slave_0/img_gen_done]
|
||
|
|
startgroup
|
||
|
|
connect_bd_net [get_bd_pins ccsds122_axil_slave_0/img_gen_busy] [get_bd_pins axi_image_gen_0/busy_o]
|
||
|
|
endgroup
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
regenerate_bd_layout
|
||
|
|
assign_bd_address
|
||
|
|
validate_bd_design
|
||
|
|
assign_bd_address -target_address_space /axi_image_gen_0/m_axi [get_bd_addr_segs ccsds122_axil_slave_0/s_axil/reg0] -force
|
||
|
|
set_property range 2G [get_bd_addr_segs {axi_image_gen_0/m_axi/SEG_ccsds122_axil_slave_0_reg0}]
|
||
|
|
assign_bd_address -target_address_space /axi_image_gen_0/m_axi [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force
|
||
|
|
set_property offset 0x80000000 [get_bd_addr_segs {ccsds122_datamover_0/m_axi_mm2s/SEG_ccsds122_axil_slave_0_reg0}]
|
||
|
|
set_property offset 0x80000000 [get_bd_addr_segs {axi_image_gen_0/m_axi/SEG_ccsds122_axil_slave_0_reg0}]
|
||
|
|
set_property range 64K [get_bd_addr_segs {axi_image_gen_0/m_axi/SEG_ccsds122_axil_slave_0_reg0}]
|
||
|
|
startgroup
|
||
|
|
exclude_bd_addr_seg [get_bd_addr_segs axi_image_gen_0/m_axi/SEG_ddr4_0_C0_DDR4_ADDRESS_BLOCK]
|
||
|
|
endgroup
|
||
|
|
startgroup
|
||
|
|
include_bd_addr_seg [get_bd_addr_segs -excluded axi_image_gen_0/m_axi/SEG_ddr4_0_C0_DDR4_ADDRESS_BLOCK]
|
||
|
|
endgroup
|
||
|
|
save_bd_design
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
set_property SOURCE_SET sources_1 [get_filesets sim_1]
|
||
|
|
add_files -fileset sim_1 -norecurse C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/tb_axi_image_gen.sv
|
||
|
|
update_compile_order -fileset sim_1
|
||
|
|
# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention.
|
||
|
|
set_property source_mgmt_mode None [current_project]
|
||
|
|
set_property top tb_axi_image_gen [get_filesets sim_1]
|
||
|
|
set_property top_lib xil_defaultlib [get_filesets sim_1]
|
||
|
|
# Re-enabling previously disabled source management mode.
|
||
|
|
set_property source_mgmt_mode All [current_project]
|
||
|
|
update_compile_order -fileset sim_1
|
||
|
|
regenerate_bd_layout
|
||
|
|
validate_bd_design
|
||
|
|
regenerate_bd_layout
|
||
|
|
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_ccsds122_axil_slave_0_0] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_1] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_axi_image_gen_0_0] }
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
||
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
launch_runs design_1_axi_image_gen_0_0_synth_1 design_1_ccsds122_axil_slave_0_0_synth_1 design_1_smartconnect_0_1_synth_1 -jobs 24
|
||
|
|
wait_on_run design_1_axi_image_gen_0_0_synth_1
|
||
|
|
wait_on_run design_1_ccsds122_axil_slave_0_0_synth_1
|
||
|
|
wait_on_run design_1_smartconnect_0_1_synth_1
|
||
|
|
export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
||
|
|
launch_simulation
|
||
|
|
launch_simulation
|
||
|
|
update_ip_catalog -rebuild -scan_changes
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
upgrade_ip -vlnv xilinx.com:user:axi_image_gen:1.0 [get_ips design_1_axi_image_gen_0_0] -log ip_upgrade.log
|
||
|
|
export_ip_user_files -of_objects [get_ips design_1_axi_image_gen_0_0] -no_script -sync -force -quiet
|
||
|
|
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
regenerate_bd_layout
|
||
|
|
regenerate_bd_layout
|
||
|
|
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
|
||
|
|
catch { [ delete_ip_run [get_ips -all design_1_smartconnect_0_1] ] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_1] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_axi_image_gen_0_0] }
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
||
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
launch_runs design_1_axi_image_gen_0_0_synth_1 -jobs 24
|
||
|
|
wait_on_run design_1_axi_image_gen_0_0_synth_1
|
||
|
|
export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
||
|
|
update_ip_catalog -rebuild -scan_changes
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
upgrade_ip -vlnv xilinx.com:user:axi_image_gen:1.0 [get_ips design_1_axi_image_gen_0_0] -log ip_upgrade.log
|
||
|
|
export_ip_user_files -of_objects [get_ips design_1_axi_image_gen_0_0] -no_script -sync -force -quiet
|
||
|
|
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
connect_bd_net [get_bd_pins ila_0/probe9] [get_bd_pins ccsds122_axil_slave_0/memory_block_size]
|
||
|
|
regenerate_bd_layout
|
||
|
|
validate_bd_design
|
||
|
|
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_1] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_axi_image_gen_0_0] }
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
||
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
launch_runs design_1_axi_image_gen_0_0_synth_1 -jobs 24
|
||
|
|
wait_on_run design_1_axi_image_gen_0_0_synth_1
|
||
|
|
export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
||
|
|
launch_simulation
|
||
|
|
source tb_axi_image_gen.tcl
|
||
|
|
current_wave_config {Untitled 6}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/axi_image_gen_0}}
|
||
|
|
restart
|
||
|
|
run 7 ms
|
||
|
|
run 7 ms
|
||
|
|
current_wave_config {Untitled 6}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/axi_image_gen_0/inst}}
|
||
|
|
current_wave_config {Untitled 6}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/axi_image_gen_0/inst}}
|
||
|
|
restart
|
||
|
|
run 7 ms
|
||
|
|
run 7 ms
|
||
|
|
current_wave_config {Untitled 6}
|
||
|
|
add_wave {{/tb_axi_image_gen}}
|
||
|
|
restart
|
||
|
|
current_wave_config {Untitled 6}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds_uart_axi_0/inst/u_core}}
|
||
|
|
restart
|
||
|
|
run 7 ms
|
||
|
|
current_wave_config {Untitled 6}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/axi_image_gen_0}}
|
||
|
|
restart
|
||
|
|
run 7 ms
|
||
|
|
current_wave_config {Untitled 6}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/axi_image_gen_0/inst}}
|
||
|
|
current_wave_config {Untitled 6}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds_uart_axi_0/inst/u_core}}
|
||
|
|
restart
|
||
|
|
run 7 ms
|
||
|
|
run 7 ms
|
||
|
|
run 7 ms
|
||
|
|
current_wave_config {Untitled 6}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/axi_image_gen_0}}
|
||
|
|
current_wave_config {Untitled 6}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl}}
|
||
|
|
current_wave_config {Untitled 6}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds_uart_axi_0/inst/u_core}}
|
||
|
|
current_wave_config {Untitled 6}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_axil_slave_0}}
|
||
|
|
current_wave_config {Untitled 6}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/smartconnect_0}}
|
||
|
|
restart
|
||
|
|
run 7 ms
|
||
|
|
run 7 ms
|
||
|
|
run 7 ms
|
||
|
|
open_bd_design {C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd}
|
||
|
|
close_bd_design [get_bd_designs design_1]
|
||
|
|
run 7 ms
|
||
|
|
close_sim
|
||
|
|
update_ip_catalog -rebuild -scan_changes
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
upgrade_ip -vlnv xilinx.com:user:axi_image_gen:1.0 [get_ips design_1_axi_image_gen_0_0] -log ip_upgrade.log
|
||
|
|
export_ip_user_files -of_objects [get_ips design_1_axi_image_gen_0_0] -no_script -sync -force -quiet
|
||
|
|
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_1] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_axi_image_gen_0_0] }
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
||
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
launch_runs design_1_axi_image_gen_0_0_synth_1 -jobs 24
|
||
|
|
wait_on_run design_1_axi_image_gen_0_0_synth_1
|
||
|
|
export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
||
|
|
regenerate_bd_layout
|
||
|
|
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_axi_image_gen_0_0] }
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
||
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
launch_runs design_1_axi_image_gen_0_0_synth_1 -jobs 24
|
||
|
|
wait_on_run design_1_axi_image_gen_0_0_synth_1
|
||
|
|
export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
||
|
|
launch_simulation
|
||
|
|
update_ip_catalog -rebuild -scan_changes
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
upgrade_ip -vlnv xilinx.com:user:axi_image_gen:1.0 [get_ips design_1_axi_image_gen_0_0] -log ip_upgrade.log
|
||
|
|
export_ip_user_files -of_objects [get_ips design_1_axi_image_gen_0_0] -no_script -sync -force -quiet
|
||
|
|
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_1] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_axi_image_gen_0_0] }
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
||
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
launch_runs design_1_axi_image_gen_0_0_synth_1 -jobs 24
|
||
|
|
wait_on_run design_1_axi_image_gen_0_0_synth_1
|
||
|
|
export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
launch_simulation
|
||
|
|
source tb_axi_image_gen.tcl
|
||
|
|
current_wave_config {Untitled 7}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/axi_image_gen_0/inst}}
|
||
|
|
current_wave_config {Untitled 7}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_axil_slave_0}}
|
||
|
|
current_wave_config {Untitled 7}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl}}
|
||
|
|
current_wave_config {Untitled 7}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds_uart_axi_0/inst/u_core}}
|
||
|
|
current_wave_config {Untitled 7}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/smartconnect_0}}
|
||
|
|
restart
|
||
|
|
run 7 ms
|
||
|
|
run 7 ms
|
||
|
|
run 7 ms
|
||
|
|
current_wave_config {Untitled 7}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl}}
|
||
|
|
current_wave_config {Untitled 7}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/axi_image_gen_0}}
|
||
|
|
close_sim
|
||
|
|
update_ip_catalog -rebuild -scan_changes
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
upgrade_ip -vlnv xilinx.com:user:axi_image_gen:1.0 [get_ips design_1_axi_image_gen_0_0] -log ip_upgrade.log
|
||
|
|
export_ip_user_files -of_objects [get_ips design_1_axi_image_gen_0_0] -no_script -sync -force -quiet
|
||
|
|
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_1] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_axi_image_gen_0_0] }
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
||
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
launch_runs design_1_axi_image_gen_0_0_synth_1 -jobs 24
|
||
|
|
wait_on_run design_1_axi_image_gen_0_0_synth_1
|
||
|
|
export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
launch_simulation
|
||
|
|
source tb_axi_image_gen.tcl
|
||
|
|
current_wave_config {Untitled 8}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/axi_image_gen_0}}
|
||
|
|
current_wave_config {Untitled 8}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_axil_slave_0}}
|
||
|
|
current_wave_config {Untitled 8}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl}}
|
||
|
|
current_wave_config {Untitled 8}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds_uart_axi_0/inst/u_core}}
|
||
|
|
current_wave_config {Untitled 8}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/smartconnect_0}}
|
||
|
|
restart
|
||
|
|
run 7 ms
|
||
|
|
run 7 ms
|
||
|
|
run 7 ms
|
||
|
|
current_wave_config {Untitled 8}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl}}
|
||
|
|
current_wave_config {Untitled 8}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/axi_image_gen_0}}
|
||
|
|
current_wave_config {Untitled 8}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds_uart_axi_0}}
|
||
|
|
current_wave_config {Untitled 8}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/axi_image_gen_0}}
|
||
|
|
current_wave_config {Untitled 8}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl}}
|
||
|
|
current_wave_config {Untitled 8}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0}}
|
||
|
|
current_wave_config {Untitled 8}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0/inst}}
|
||
|
|
current_wave_config {Untitled 8}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/axi_image_gen_0}}
|
||
|
|
current_wave_config {Untitled 8}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0/inst}}
|
||
|
|
current_wave_config {Untitled 8}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/axi_image_gen_0}}
|
||
|
|
current_wave_config {Untitled 8}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_axil_slave_0}}
|
||
|
|
current_wave_config {Untitled 8}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds_uart_axi_0/inst/u_core}}
|
||
|
|
current_wave_config {Untitled 8}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl}}
|
||
|
|
current_wave_config {Untitled 8}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/smartconnect_0}}
|
||
|
|
restart
|
||
|
|
run 7 ms
|
||
|
|
run 7 ms
|
||
|
|
run 7 ms
|
||
|
|
current_wave_config {Untitled 8}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0/inst}}
|
||
|
|
current_wave_config {Untitled 8}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/axi_image_gen_0}}
|
||
|
|
current_wave_config {Untitled 8}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl}}
|
||
|
|
close_sim
|
||
|
|
update_ip_catalog -rebuild -scan_changes
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
upgrade_ip -vlnv xilinx.com:user:axi_image_gen:1.0 [get_ips design_1_axi_image_gen_0_0] -log ip_upgrade.log
|
||
|
|
export_ip_user_files -of_objects [get_ips design_1_axi_image_gen_0_0] -no_script -sync -force -quiet
|
||
|
|
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_1] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_axi_image_gen_0_0] }
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
||
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
launch_runs design_1_axi_image_gen_0_0_synth_1 -jobs 24
|
||
|
|
wait_on_run design_1_axi_image_gen_0_0_synth_1
|
||
|
|
export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
launch_simulation
|
||
|
|
source tb_axi_image_gen.tcl
|
||
|
|
current_wave_config {Untitled 9}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/axi_image_gen_0}}
|
||
|
|
current_wave_config {Untitled 9}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_axil_slave_0}}
|
||
|
|
current_wave_config {Untitled 9}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl}}
|
||
|
|
current_wave_config {Untitled 9}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds_uart_axi_0/inst/u_core}}
|
||
|
|
current_wave_config {Untitled 9}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/smartconnect_0}}
|
||
|
|
restart
|
||
|
|
run 7 ms
|
||
|
|
run 7 ms
|
||
|
|
current_wave_config {Untitled 9}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/axi_image_gen_0}}
|
||
|
|
run 7 ms
|
||
|
|
current_wave_config {Untitled 9}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl}}
|
||
|
|
current_wave_config {Untitled 9}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_axil_slave_0}}
|
||
|
|
run 7 ms
|
||
|
|
close_sim
|
||
|
|
update_ip_catalog -rebuild -scan_changes
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
upgrade_ip -vlnv xilinx.com:user:axi_image_gen:1.0 [get_ips design_1_axi_image_gen_0_0] -log ip_upgrade.log
|
||
|
|
export_ip_user_files -of_objects [get_ips design_1_axi_image_gen_0_0] -no_script -sync -force -quiet
|
||
|
|
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_1] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_axi_image_gen_0_0] }
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
||
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
launch_runs design_1_axi_image_gen_0_0_synth_1 -jobs 24
|
||
|
|
wait_on_run design_1_axi_image_gen_0_0_synth_1
|
||
|
|
export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
launch_simulation
|
||
|
|
source tb_axi_image_gen.tcl
|
||
|
|
current_wave_config {Untitled 10}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/axi_image_gen_0}}
|
||
|
|
current_wave_config {Untitled 10}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_axil_slave_0}}
|
||
|
|
current_wave_config {Untitled 10}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl}}
|
||
|
|
current_wave_config {Untitled 10}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds_uart_axi_0/inst/u_core}}
|
||
|
|
current_wave_config {Untitled 10}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/smartconnect_0}}
|
||
|
|
restart
|
||
|
|
run 7 ms
|
||
|
|
run 7 ms
|
||
|
|
run 7 ms
|
||
|
|
current_wave_config {Untitled 10}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/axi_image_gen_0}}
|
||
|
|
current_wave_config {Untitled 10}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/smartconnect_0}}
|
||
|
|
current_wave_config {Untitled 10}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl}}
|
||
|
|
close_sim
|
||
|
|
update_ip_catalog -rebuild -scan_changes
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
upgrade_ip -vlnv xilinx.com:user:axi_image_gen:1.0 [get_ips design_1_axi_image_gen_0_0] -log ip_upgrade.log
|
||
|
|
export_ip_user_files -of_objects [get_ips design_1_axi_image_gen_0_0] -no_script -sync -force -quiet
|
||
|
|
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_1] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_axi_image_gen_0_0] }
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
||
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
launch_runs design_1_axi_image_gen_0_0_synth_1 -jobs 24
|
||
|
|
wait_on_run design_1_axi_image_gen_0_0_synth_1
|
||
|
|
export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
launch_simulation
|
||
|
|
source tb_axi_image_gen.tcl
|
||
|
|
current_wave_config {Untitled 11}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/axi_image_gen_0}}
|
||
|
|
current_wave_config {Untitled 11}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_axil_slave_0}}
|
||
|
|
current_wave_config {Untitled 11}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl}}
|
||
|
|
current_wave_config {Untitled 11}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_bubble_removal}}
|
||
|
|
current_wave_config {Untitled 11}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds_uart_axi_0/inst/u_core}}
|
||
|
|
current_wave_config {Untitled 11}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/smartconnect_0}}
|
||
|
|
restart
|
||
|
|
run 7 ms
|
||
|
|
run 7 ms
|
||
|
|
run 7 ms
|
||
|
|
current_wave_config {Untitled 11}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl}}
|
||
|
|
current_wave_config {Untitled 11}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0/inst}}
|
||
|
|
close_sim
|
||
|
|
update_ip_catalog -rebuild -scan_changes
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
upgrade_ip -vlnv xilinx.com:user:axi_image_gen:1.0 [get_ips design_1_axi_image_gen_0_0] -log ip_upgrade.log
|
||
|
|
export_ip_user_files -of_objects [get_ips design_1_axi_image_gen_0_0] -no_script -sync -force -quiet
|
||
|
|
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_1] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_axi_image_gen_0_0] }
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
||
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
launch_runs design_1_axi_image_gen_0_0_synth_1 -jobs 24
|
||
|
|
wait_on_run design_1_axi_image_gen_0_0_synth_1
|
||
|
|
export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
launch_simulation
|
||
|
|
source tb_axi_image_gen.tcl
|
||
|
|
current_wave_config {Untitled 12}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/axi_image_gen_0}}
|
||
|
|
current_wave_config {Untitled 12}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_axil_slave_0}}
|
||
|
|
current_wave_config {Untitled 12}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0/inst}}
|
||
|
|
current_wave_config {Untitled 12}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl}}
|
||
|
|
current_wave_config {Untitled 12}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_bubble_removal}}
|
||
|
|
current_wave_config {Untitled 12}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds_uart_axi_0/inst/u_core}}
|
||
|
|
current_wave_config {Untitled 12}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/smartconnect_0}}
|
||
|
|
restart
|
||
|
|
run 7 ms
|
||
|
|
run 7 ms
|
||
|
|
run 7 ms
|
||
|
|
close_sim
|
||
|
|
update_ip_catalog -rebuild -scan_changes
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
upgrade_ip -vlnv xilinx.com:user:axi_image_gen:1.0 [get_ips design_1_axi_image_gen_0_0] -log ip_upgrade.log
|
||
|
|
export_ip_user_files -of_objects [get_ips design_1_axi_image_gen_0_0] -no_script -sync -force -quiet
|
||
|
|
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_1] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_axi_image_gen_0_0] }
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
||
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
launch_runs design_1_axi_image_gen_0_0_synth_1 -jobs 24
|
||
|
|
wait_on_run design_1_axi_image_gen_0_0_synth_1
|
||
|
|
export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
launch_simulation
|
||
|
|
source tb_axi_image_gen.tcl
|
||
|
|
current_wave_config {Untitled 13}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/axi_image_gen_0}}
|
||
|
|
current_wave_config {Untitled 13}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_axil_slave_0}}
|
||
|
|
current_wave_config {Untitled 13}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0/inst}}
|
||
|
|
current_wave_config {Untitled 13}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl}}
|
||
|
|
current_wave_config {Untitled 13}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_bubble_removal}}
|
||
|
|
current_wave_config {Untitled 13}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds_uart_axi_0/inst/u_core}}
|
||
|
|
current_wave_config {Untitled 13}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/smartconnect_0}}
|
||
|
|
restart
|
||
|
|
run 7 ms
|
||
|
|
run 7 ms
|
||
|
|
run 7 ms
|
||
|
|
current_wave_config {Untitled 13}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/axi_image_gen_0}}
|
||
|
|
current_wave_config {Untitled 13}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0/inst}}
|
||
|
|
current_wave_config {Untitled 13}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl}}
|
||
|
|
current_wave_config {Untitled 13}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/smartconnect_0}}
|
||
|
|
current_wave_config {Untitled 13}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl}}
|
||
|
|
current_wave_config {Untitled 13}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ddr4_0}}
|
||
|
|
close_sim
|
||
|
|
update_ip_catalog -rebuild -scan_changes
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
upgrade_ip -vlnv xilinx.com:user:axi_image_gen:1.0 [get_ips design_1_axi_image_gen_0_0] -log ip_upgrade.log
|
||
|
|
export_ip_user_files -of_objects [get_ips design_1_axi_image_gen_0_0] -no_script -sync -force -quiet
|
||
|
|
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_1] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_axi_image_gen_0_0] }
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
||
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
launch_runs design_1_axi_image_gen_0_0_synth_1 -jobs 24
|
||
|
|
wait_on_run design_1_axi_image_gen_0_0_synth_1
|
||
|
|
export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
launch_simulation
|
||
|
|
source tb_axi_image_gen.tcl
|
||
|
|
current_wave_config {Untitled 14}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/axi_image_gen_0}}
|
||
|
|
current_wave_config {Untitled 14}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_axil_slave_0}}
|
||
|
|
current_wave_config {Untitled 14}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0/inst}}
|
||
|
|
current_wave_config {Untitled 14}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl}}
|
||
|
|
current_wave_config {Untitled 14}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_bubble_removal}}
|
||
|
|
current_wave_config {Untitled 14}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds_uart_axi_0/inst/u_core}}
|
||
|
|
current_wave_config {Untitled 14}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/smartconnect_0}}
|
||
|
|
restart
|
||
|
|
run 7 ms
|
||
|
|
run 7 ms
|
||
|
|
run 7 ms
|
||
|
|
current_wave_config {Untitled 14}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl}}
|
||
|
|
current_wave_config {Untitled 14}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0/inst}}
|
||
|
|
current_wave_config {Untitled 14}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl}}
|
||
|
|
current_wave_config {Untitled 14}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/smartconnect_0}}
|
||
|
|
current_wave_config {Untitled 14}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/axi_image_gen_0}}
|
||
|
|
update_compile_order -fileset sim_1
|
||
|
|
close_sim
|
||
|
|
set_property SOURCE_SET sources_1 [get_filesets sim_1]
|
||
|
|
add_files -fileset sim_1 -norecurse C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sdram_model_wrapper.sv
|
||
|
|
set_property SOURCE_SET sources_1 [get_filesets sim_1]
|
||
|
|
add_files -fileset sim_1 -norecurse C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/MemoryArray.sv
|
||
|
|
update_compile_order -fileset sim_1
|
||
|
|
set_property SOURCE_SET sources_1 [get_filesets sim_1]
|
||
|
|
add_files -fileset sim_1 -norecurse {C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/interface.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/arch_defines.v C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/arch_package.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_model.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sdram_model_wrapper.sv}
|
||
|
|
update_compile_order -fileset sim_1
|
||
|
|
launch_simulation
|
||
|
|
set_property SOURCE_SET sources_1 [get_filesets sim_1]
|
||
|
|
add_files -fileset sim_1 -norecurse C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/proj_package.sv
|
||
|
|
launch_simulation
|
||
|
|
launch_simulation
|
||
|
|
source tb_axi_image_gen.tcl
|
||
|
|
current_wave_config {Untitled 15}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/axi_image_gen_0}}
|
||
|
|
current_wave_config {Untitled 15}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_axil_slave_0}}
|
||
|
|
current_wave_config {Untitled 15}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0/inst}}
|
||
|
|
current_wave_config {Untitled 15}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl}}
|
||
|
|
current_wave_config {Untitled 15}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds_uart_axi_0/inst/u_core}}
|
||
|
|
current_wave_config {Untitled 15}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/smartconnect_0}}
|
||
|
|
restart
|
||
|
|
run 7 ms
|
||
|
|
run 7 ms
|
||
|
|
run 7 ms
|
||
|
|
current_wave_config {Untitled 15}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0/inst}}
|
||
|
|
current_wave_config {Untitled 15}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl}}
|
||
|
|
current_wave_config {Untitled 15}
|
||
|
|
add_wave {{/tb_axi_image_gen/\mem_model_x16.tranDQ[0].tranDQ1[0].tranDQp[0].bidiDQ }}
|
||
|
|
current_wave_config {Untitled 15}
|
||
|
|
add_wave {{/tb_axi_image_gen/\mem_model_x16.tranDQ[0].tranDQ1[0].tranDQp[0].bidiDQ }}
|
||
|
|
current_wave_config {Untitled 15}
|
||
|
|
add_wave {{/tb_axi_image_gen/\mem_model_x16.tranDQ[0].tranDQ1[0].tranDQp[1].bidiDQ }}
|
||
|
|
current_wave_config {Untitled 15}
|
||
|
|
add_wave {{/tb_axi_image_gen/\mem_model_x16.tranDQ[0].tranDQ1[0].tranDQp[2].bidiDQ }}
|
||
|
|
current_wave_config {Untitled 15}
|
||
|
|
add_wave {{/tb_axi_image_gen/\mem_model_x16.tranDQ[0].tranDQ1[0].tranDQp[7].bidiDQ }}
|
||
|
|
current_wave_config {Untitled 15}
|
||
|
|
add_wave {{/tb_axi_image_gen/\mem_model_x16.tranDQ[0].tranDQ1[0].tranDQp[0].bidiDQ }}
|
||
|
|
current_wave_config {Untitled 15}
|
||
|
|
add_wave {{/tb_axi_image_gen/\mem_model_x16.tranDQ[0].tranDQ1[0].tranDQp[1].bidiDQ }}
|
||
|
|
current_wave_config {Untitled 15}
|
||
|
|
add_wave {{/tb_axi_image_gen/\mem_model_x16.tranDQ[0].tranDQ1[0].tranDQp[2].bidiDQ }}
|
||
|
|
current_wave_config {Untitled 15}
|
||
|
|
add_wave {{/tb_axi_image_gen/\mem_model_x16.tranDQ[0].tranDQ1[0].tranDQp[3].bidiDQ }}
|
||
|
|
current_wave_config {Untitled 15}
|
||
|
|
add_wave {{/tb_axi_image_gen/\mem_model_x16.tranDQ[0].tranDQ1[0].tranDQp[4].bidiDQ }}
|
||
|
|
current_wave_config {Untitled 15}
|
||
|
|
add_wave {{/tb_axi_image_gen/\mem_model_x16.tranDQ[0].tranDQ1[0].tranDQp[5].bidiDQ }}
|
||
|
|
current_wave_config {Untitled 15}
|
||
|
|
add_wave {{/tb_axi_image_gen/\mem_model_x16.tranDQ[0].tranDQ1[0].tranDQp[6].bidiDQ }}
|
||
|
|
current_wave_config {Untitled 15}
|
||
|
|
add_wave {{/tb_axi_image_gen/\mem_model_x16.tranDQ[0].tranDQ1[0].tranDQp[7].bidiDQ }}
|
||
|
|
current_wave_config {Untitled 15}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ddr4_0/inst/u_ddr_axi}}
|
||
|
|
current_wave_config {Untitled 15}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ddr4_0/inst/u_ddr4_mem_intfc}}
|
||
|
|
current_wave_config {Untitled 15}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ddr4_0/inst/u_ddr4_infrastructure}}
|
||
|
|
current_wave_config {Untitled 15}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ddr4_0/inst/u_ddr_axi}}
|
||
|
|
current_wave_config {Untitled 15}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ddr4_0/inst/u_ddr4_infrastructure}}
|
||
|
|
current_wave_config {Untitled 15}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ddr4_0/inst/u_ddr4_mem_intfc}}
|
||
|
|
restart
|
||
|
|
restart
|
||
|
|
run 7 ms
|
||
|
|
run 7 ms
|
||
|
|
run 7 ms
|
||
|
|
set_property -dict [list CONFIG.Simulation_Mode {FULL}] [get_ips design_1_ddr4_0_0]
|
||
|
|
set_property -dict [list CONFIG.Simulation_Mode {Unisim}] [get_ips design_1_ddr4_0_0]
|
||
|
|
generate_target simulation [get_ips design_1_ddr4_0_0]
|
||
|
|
set_property -dict [list CONFIG.Simulation_Mode {Unisim}] [get_ips design_1_ddr4_0_0]
|
||
|
|
generate_target simulation [get_files design_1.bd]
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
close_sim
|
||
|
|
launch_simulation
|
||
|
|
source tb_axi_image_gen.tcl
|
||
|
|
current_wave_config {Untitled 16}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_axil_slave_0}}
|
||
|
|
current_wave_config {Untitled 16}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl}}
|
||
|
|
current_wave_config {Untitled 16}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0/inst}}
|
||
|
|
current_wave_config {Untitled 16}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds_uart_axi_0/inst/u_core}}
|
||
|
|
current_wave_config {Untitled 16}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/smartconnect_0}}
|
||
|
|
current_wave_config {Untitled 16}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ddr4_0/inst/u_ddr4_infrastructure}}
|
||
|
|
current_wave_config {Untitled 16}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ddr4_0/inst/u_ddr4_mem_intfc}}
|
||
|
|
restart
|
||
|
|
run 7 ms
|
||
|
|
run 7 ms
|
||
|
|
run 7 ms
|
||
|
|
current_wave_config {Untitled 16}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ddr4_0/inst/u_ddr4_infrastructure}}
|
||
|
|
current_wave_config {Untitled 16}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ddr4_0/inst/u_ddr4_mem_intfc}}
|
||
|
|
open_bd_design {C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd}
|
||
|
|
close_bd_design [get_bd_designs design_1]
|
||
|
|
current_wave_config {Untitled 16}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/smartconnect_0}}
|
||
|
|
close_sim
|
||
|
|
open_bd_design {C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd}
|
||
|
|
set_property SOURCE_SET sources_1 [get_filesets sim_1]
|
||
|
|
add_files -fileset sim_1 -norecurse {C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/bd_421a_second_lmb_bram_I_0.mem C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/bd_421a_lmb_bram_I_0.mem}
|
||
|
|
add_files -fileset sim_1 -norecurse {C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/ddr4_v2_2_prbs_mode_gen.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/proj_package.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/ddr4_v2_2_custom_mode_gen.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/glbl.v C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/ddr4_sim_microblaze_mcs_0.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/MemoryArray.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/StateTable.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/ddr4_model.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/ddr4_v2_2_data_gen.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/StateTableCore.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/ddr4_v2_2_data_chk.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/sim_tb_top.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/ddr4_sdram_model_wrapper.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/ddr4_v2_2_axi_wrapper.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/example_top.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/timing_tasks.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/arch_package.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/ddr4_v2_2_boot_mode_gen.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/arch_defines.v C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/ddr4_v2_2_axi_tg_top.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/interface.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/ddr4_v2_2_axi_opcode_gen.sv}
|
||
|
|
update_compile_order -fileset sim_1
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/timing_tasks.sv] -no_script -reset -force -quiet
|
||
|
|
remove_files -fileset sim_1 C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/timing_tasks.sv
|
||
|
|
launch_simulation
|
||
|
|
source tb_axi_image_gen.tcl
|
||
|
|
current_wave_config {Untitled 17}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_axil_slave_0}}
|
||
|
|
current_wave_config {Untitled 17}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/axi_image_gen_0}}
|
||
|
|
current_wave_config {Untitled 17}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl}}
|
||
|
|
current_wave_config {Untitled 17}
|
||
|
|
add_wave {{/tb_axi_image_gen/u_dut/design_1_i/ccsds122_datamover_0/inst}}
|
||
|
|
restart
|
||
|
|
run 7 ms
|
||
|
|
run 7 ms
|
||
|
|
open_bd_design {C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd}
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/arch_defines.v] -no_script -reset -force -quiet
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/arch_defines.v] -no_script -reset -force -quiet
|
||
|
|
remove_files -fileset sim_1 {C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/arch_defines.v C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/arch_defines.v}
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/arch_package.sv] -no_script -reset -force -quiet
|
||
|
|
remove_files -fileset sim_1 C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/arch_package.sv
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/sim_tb_top.sv] -no_script -reset -force -quiet
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/example_top.sv] -no_script -reset -force -quiet
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/ddr4_model.sv] -no_script -reset -force -quiet
|
||
|
|
remove_files -fileset sim_1 {C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/sim_tb_top.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/example_top.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/ddr4_model.sv}
|
||
|
|
update_compile_order -fileset sim_1
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/ddr4_v2_2_axi_tg_top.sv] -no_script -reset -force -quiet
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/ddr4_v2_2_boot_mode_gen.sv] -no_script -reset -force -quiet
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/ddr4_v2_2_prbs_mode_gen.sv] -no_script -reset -force -quiet
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/ddr4_v2_2_custom_mode_gen.sv] -no_script -reset -force -quiet
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/ddr4_v2_2_axi_opcode_gen.sv] -no_script -reset -force -quiet
|
||
|
|
remove_files -fileset sim_1 {C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/ddr4_v2_2_axi_tg_top.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/ddr4_v2_2_boot_mode_gen.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/ddr4_v2_2_prbs_mode_gen.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/ddr4_v2_2_custom_mode_gen.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/ddr4_v2_2_axi_opcode_gen.sv}
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/ddr4_v2_2_axi_wrapper.sv] -no_script -reset -force -quiet
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/ddr4_v2_2_data_gen.sv] -no_script -reset -force -quiet
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/ddr4_v2_2_data_chk.sv] -no_script -reset -force -quiet
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/ddr4_sim_microblaze_mcs_0.sv] -no_script -reset -force -quiet
|
||
|
|
remove_files -fileset sim_1 {C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/ddr4_v2_2_axi_wrapper.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/ddr4_v2_2_data_gen.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/ddr4_v2_2_data_chk.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/ddr4_sim_microblaze_mcs_0.sv}
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/tb_axi_image_gen.sv] -no_script -reset -force -quiet
|
||
|
|
remove_files -fileset sim_1 C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/tb_axi_image_gen.sv
|
||
|
|
update_compile_order -fileset sim_1
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sdram_model_wrapper.sv] -no_script -reset -force -quiet
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/MemoryArray.sv] -no_script -reset -force -quiet
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/StateTableCore.sv] -no_script -reset -force -quiet
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/ddr4_sdram_model_wrapper.sv] -no_script -reset -force -quiet
|
||
|
|
remove_files -fileset sim_1 {C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sdram_model_wrapper.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/MemoryArray.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/StateTableCore.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/ddr4_sdram_model_wrapper.sv}
|
||
|
|
update_compile_order -fileset sim_1
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_model.sv] -no_script -reset -force -quiet
|
||
|
|
remove_files -fileset sim_1 C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_model.sv
|
||
|
|
update_compile_order -fileset sim_1
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/bd_421a_lmb_bram_I_0.mem] -no_script -reset -force -quiet
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/bd_421a_second_lmb_bram_I_0.mem] -no_script -reset -force -quiet
|
||
|
|
remove_files -fileset sim_1 {C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/bd_421a_lmb_bram_I_0.mem C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/bd_421a_second_lmb_bram_I_0.mem}
|
||
|
|
update_compile_order -fileset sim_1
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/StateTable.sv] -no_script -reset -force -quiet
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/glbl.v] -no_script -reset -force -quiet
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/proj_package.sv] -no_script -reset -force -quiet
|
||
|
|
remove_files -fileset sim_1 {C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/StateTable.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/glbl.v C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/proj_package.sv}
|
||
|
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reset_run design_1_axi_image_gen_0_0_synth_1
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||
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close_sim
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