1201 lines
191 KiB
Plaintext
1201 lines
191 KiB
Plaintext
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#-----------------------------------------------------------
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# Vivado v2023.2 (64-bit)
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# SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023
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# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
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# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
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# Start of session at: Mon Jul 6 15:22:16 2026
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# Process ID: 24964
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# Current directory: C:/proj/xc7v_ccsds122_datamover_uart
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# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent34776 C:\proj\xc7v_ccsds122_datamover_uart\ccsds122_storage.xpr
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# Log file: C:/proj/xc7v_ccsds122_datamover_uart/vivado.log
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# Journal file: C:/proj/xc7v_ccsds122_datamover_uart\vivado.jou
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# Running On: DESKTOP-EB3SDQ2, OS: Windows, CPU Frequency: 2112 MHz, CPU Physical cores: 16, Host memory: 16817 MB
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#-----------------------------------------------------------
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start_gui
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open_project C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.xpr
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.1 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.1/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.0 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.0/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.1 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.1/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.1 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.1/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available
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WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at C:/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
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CRITICAL WARNING: [Project 1-19] Could not find the file 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/tb_design_1_wrapper.sv'.
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CRITICAL WARNING: [Project 1-19] Could not find the file 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/arch_package.sv'.
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CRITICAL WARNING: [Project 1-19] Could not find the file 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/proj_package.sv'.
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CRITICAL WARNING: [Project 1-19] Could not find the file 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/MemoryArray.sv'.
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CRITICAL WARNING: [Project 1-19] Could not find the file 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/interface.sv'.
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CRITICAL WARNING: [Project 1-19] Could not find the file 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/interface.sv'.
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Scanning sources...
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Finished scanning sources
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INFO: [IP_Flow 19-234] Refreshing IP repositories
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INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/proj/FPGA_DESIGN_IP'.
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INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2023.2/data/ip'.
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WARNING: [filemgmt 56-443] The ECC Algorithm string is empty. Setting the Memory Map to default ECC value to ECC_NONE.
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WARNING: [filemgmt 56-443] The ECC Algorithm string is empty. Setting the Memory Map to default ECC value to ECC_NONE.
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WARNING: [IP_Flow 19-3664] IP 'design_1_axi_image_gen_0_0' generated file not found 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_axi_image_gen_0_0/design_1_axi_image_gen_0_0.dcp'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_axi_image_gen_0_0' generated file not found 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_axi_image_gen_0_0/design_1_axi_image_gen_0_0_stub.v'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_axi_image_gen_0_0' generated file not found 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_axi_image_gen_0_0/design_1_axi_image_gen_0_0_stub.vhdl'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_axi_image_gen_0_0' generated file not found 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_axi_image_gen_0_0/design_1_axi_image_gen_0_0_sim_netlist.v'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'design_1_axi_image_gen_0_0' generated file not found 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_axi_image_gen_0_0/design_1_axi_image_gen_0_0_sim_netlist.vhdl'. Please regenerate to continue.
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open_project: Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 1839.086 ; gain = 571.355
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update_compile_order -fileset sources_1
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update_compile_order -fileset sim_1
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export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/MemoryArray.sv] -no_script -reset -force -quiet
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export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/arch_package.sv] -no_script -reset -force -quiet
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export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/interface.sv] -no_script -reset -force -quiet
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export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/interface.sv] -no_script -reset -force -quiet
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export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/proj_package.sv] -no_script -reset -force -quiet
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export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/tb_design_1_wrapper.sv] -no_script -reset -force -quiet
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remove_files -fileset sim_1 {C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/MemoryArray.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/arch_package.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/interface.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/interface.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/ddr4_sim_ex/imports/proj_package.sv C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sim_1/imports/tb_design_1_wrapper.sv}
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open_bd_design {C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd}
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Reading block design file <C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd>...
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Adding component instance block -- xilinx.com:user:ccsds122_datamover:1.0 - ccsds122_datamover_0
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Adding component instance block -- xilinx.com:ip:smartconnect:1.0 - smartconnect_0
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Adding component instance block -- xilinx.com:user:ccsds122_axil_slave:1.0 - ccsds122_axil_slave_0
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Adding component instance block -- xilinx.com:ip:ila:6.2 - ila_0
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INFO: [xilinx.com:ip:ila:6.2-6] /ila_0: AMD recommends using the System ILA IP in IP Integrator. The System ILA IP is functionally equivalent to an ILA and offers additional benefits in debugging interfaces both within IP Integrator and the Hardware Manager. Consult the Programming and Debug User Guide UG908 for further details.
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Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - proc_sys_reset_0
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Adding component instance block -- xilinx.com:user:ccsds_uart_axi:1.0 - ccsds_uart_axi_0
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Adding component instance block -- xilinx.com:ip:ddr4:2.2 - ddr4_0
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Adding component instance block -- xilinx.com:ip:util_vector_logic:2.0 - util_vector_logic_0
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Adding component instance block -- xilinx.com:ip:system_ila:1.1 - system_ila_0
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Adding component instance block -- xilinx.com:ip:system_ila:1.1 - system_ila_1
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Adding component instance block -- xilinx.com:user:axi_image_gen:1.0 - axi_image_gen_0
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Successfully read diagram <design_1> from block design file <C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd>
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regenerate_bd_layout
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reset_run synth_1_copy_1
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INFO: [Project 1-1161] Replacing file C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/utils_1/imports/synth_1/design_1_wrapper.dcp with file C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1_copy_1/design_1_wrapper.dcp
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launch_runs impl_2 -to_step write_bitstream -jobs 24
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INFO: [IP_Flow 19-6930] IPCACHE: runCacheChecks() number of threads = 8
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INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_axi_image_gen_0_0
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INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_ddr4_0_0
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INFO: [IP_Flow 19-8020] IPCACHE: runCacheChecks() calling threadPool finishWork()
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INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_axi_image_gen_0_0
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INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ddr4_0_0
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[Mon Jul 6 15:24:06 2026] Launched design_1_axi_image_gen_0_0_synth_1, design_1_ddr4_0_0_synth_1, synth_1_copy_1...
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Run output will be captured here:
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design_1_axi_image_gen_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_axi_image_gen_0_0_synth_1/runme.log
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design_1_ddr4_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ddr4_0_0_synth_1/runme.log
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synth_1_copy_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1_copy_1/runme.log
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[Mon Jul 6 15:24:06 2026] Launched impl_2...
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Run output will be captured here: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/impl_2/runme.log
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INFO: [Device 21-403] Loading part xcku5p-ffvb676-2-i
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CRITICAL WARNING: [Common 17-3551] The parameter 'ipgui.displayPowerEstimation' is obsolete. All references to this parameter should be removed.
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reset_run design_1_axi_image_gen_0_0_synth_1
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delete_bd_objs [get_bd_intf_nets axi_image_gen_0_m_axi] [get_bd_nets ccsds122_axil_slave_0_img_src_sel] [get_bd_nets ccsds122_axil_slave_0_img_gen_start] [get_bd_nets ccsds122_axil_slave_0_img_rows] [get_bd_nets ccsds122_axil_slave_0_storage_mode] [get_bd_nets axi_image_gen_0_done_o] [get_bd_nets axi_image_gen_0_busy_o] [get_bd_cells axi_image_gen_0]
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regenerate_bd_layout
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validate_bd_design
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INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
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INFO: [BD 5-943] Reserving offset range <0x8000_0000 [ 64K ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
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INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
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INFO: [BD 5-943] Reserving offset range <0x8000_0000 [ 64K ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
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INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
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INFO: [BD 5-943] Reserving offset range <0x8000_0000 [ 64K ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
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INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S03_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
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INFO: [BD 5-943] Reserving offset range <0x8000_0000 [ 64K ]> from slave interface '/smartconnect_0/S03_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
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INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_1: SmartConnect design_1_smartconnect_0_1 is in High-performance Mode.
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xit::source_ipfile: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 3464.941 ; gain = 50.293
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CRITICAL WARNING: [BD 41-1343] Reset pin /ddr4_0/c0_ddr4_aresetn (associated clock /ddr4_0/c0_ddr4_ui_clk) is connected to reset source /proc_sys_reset_0/peripheral_aresetn (synchronous to clock source /ddr4_0/addn_ui_clkout1).
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This may prevent design from meeting timing. Please add Processor System Reset module to create a reset that is synchronous to the associated clock source /ddr4_0/c0_ddr4_ui_clk.
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CRITICAL WARNING: [BD 41-1343] Reset pin /system_ila_1/resetn (associated clock /system_ila_1/clk) is connected to reset source /proc_sys_reset_0/peripheral_aresetn (synchronous to clock source /ddr4_0/addn_ui_clkout1).
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This may prevent design from meeting timing. Please add Processor System Reset module to create a reset that is synchronous to the associated clock source /ddr4_0/c0_ddr4_ui_clk.
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WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ddr4_0/C0_DDR4_S_AXI(0) and /smartconnect_0/M00_AXI(4)
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WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ddr4_0/C0_DDR4_S_AXI(0) and /smartconnect_0/M00_AXI(4)
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CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
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Please check your design and connect them as needed:
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/ccsds122_axil_slave_0/img_gen_busy
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/ccsds122_axil_slave_0/img_gen_done
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validate_bd_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 3573.102 ; gain = 173.426
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regenerate_bd_layout
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generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
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INFO: [BD 41-1662] The design 'design_1.bd' is already validated. Therefore parameter propagation will not be re-run.
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CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
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Please check your design and connect them as needed:
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/ccsds122_axil_slave_0/img_gen_busy
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/ccsds122_axil_slave_0/img_gen_done
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Wrote : <C:\proj\xc7v_ccsds122_datamover_uart\ccsds122_storage.srcs\sources_1\bd\design_1\design_1.bd>
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Wrote : <C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
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Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
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Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/sim/design_1.v
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|
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Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
|
||
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/hw_handoff/design_1_smartconnect_0_1.hwh
|
||
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/synth/design_1_smartconnect_0_1.hwdef
|
||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block smartconnect_0 .
|
||
|
|
WARNING: [filemgmt 56-443] The ECC Algorithm string is empty. Setting the Memory Map to default ECC value to ECC_NONE.
|
||
|
|
WARNING: [filemgmt 56-443] The ECC Algorithm string is empty. Setting the Memory Map to default ECC value to ECC_NONE.
|
||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block ddr4_0 .
|
||
|
|
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_ooc.xdc'
|
||
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/hw_handoff/design_1_system_ila_0_0.hwh
|
||
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/synth/design_1_system_ila_0_0.hwdef
|
||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block system_ila_0 .
|
||
|
|
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_ooc.xdc'
|
||
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/hw_handoff/design_1_system_ila_0_1.hwh
|
||
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/synth/design_1_system_ila_0_1.hwdef
|
||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block system_ila_1 .
|
||
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh
|
||
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.hwdef
|
||
|
|
generate_target: Time (s): cpu = 00:00:25 ; elapsed = 00:00:25 . Memory (MB): peak = 3720.055 ; gain = 107.344
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_smartconnect_0_1
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_ddr4_0_0] }
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ddr4_0_0
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_system_ila_0_0
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_1] }
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_system_ila_0_1
|
||
|
|
INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry 754f7c0da7d9e35f to dir: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/5/754f7c0da7d9e35f/design_1_system_ila_0_1.dcp to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1.dcp.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1.dcp
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/5/754f7c0da7d9e35f/design_1_system_ila_0_1_sim_netlist.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_sim_netlist.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_sim_netlist.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/5/754f7c0da7d9e35f/design_1_system_ila_0_1_sim_netlist.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_sim_netlist.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_sim_netlist.vhdl
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/5/754f7c0da7d9e35f/design_1_system_ila_0_1_stub.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_stub.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_stub.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/5/754f7c0da7d9e35f/design_1_system_ila_0_1_stub.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_stub.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_stub.vhdl
|
||
|
|
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_system_ila_0_1, cache-ID = 754f7c0da7d9e35f; cache size = 4795.167 MB.
|
||
|
|
config_ip_cache: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3734.480 ; gain = 14.426
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
||
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
launch_runs design_1_ddr4_0_0_synth_1 design_1_smartconnect_0_1_synth_1 design_1_system_ila_0_0_synth_1 -jobs 24
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ddr4_0_0
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_smartconnect_0_1
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_system_ila_0_0
|
||
|
|
[Mon Jul 6 15:37:45 2026] Launched design_1_ddr4_0_0_synth_1, design_1_smartconnect_0_1_synth_1, design_1_system_ila_0_0_synth_1...
|
||
|
|
Run output will be captured here:
|
||
|
|
design_1_ddr4_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ddr4_0_0_synth_1/runme.log
|
||
|
|
design_1_smartconnect_0_1_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_smartconnect_0_1_synth_1/runme.log
|
||
|
|
design_1_system_ila_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_system_ila_0_0_synth_1/runme.log
|
||
|
|
export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
||
|
|
reset_run synth_1_copy_1
|
||
|
|
launch_runs impl_2 -to_step write_bitstream -jobs 24
|
||
|
|
INFO: [IP_Flow 19-6930] IPCACHE: runCacheChecks() number of threads = 8
|
||
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_ddr4_0_0
|
||
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_smartconnect_0_1
|
||
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_system_ila_0_0
|
||
|
|
INFO: [IP_Flow 19-8020] IPCACHE: runCacheChecks() calling threadPool finishWork()
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ddr4_0_0
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_smartconnect_0_1
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_system_ila_0_0
|
||
|
|
[Mon Jul 6 15:39:38 2026] Launched design_1_ddr4_0_0_synth_1, design_1_smartconnect_0_1_synth_1, design_1_system_ila_0_0_synth_1, synth_1_copy_1...
|
||
|
|
Run output will be captured here:
|
||
|
|
design_1_ddr4_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ddr4_0_0_synth_1/runme.log
|
||
|
|
design_1_smartconnect_0_1_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_smartconnect_0_1_synth_1/runme.log
|
||
|
|
design_1_system_ila_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_system_ila_0_0_synth_1/runme.log
|
||
|
|
synth_1_copy_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1_copy_1/runme.log
|
||
|
|
[Mon Jul 6 15:39:39 2026] Launched impl_2...
|
||
|
|
Run output will be captured here: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/impl_2/runme.log
|
||
|
|
delete_bd_objs [get_bd_nets ccsds122_datamover_0_mm2s_err] [get_bd_nets ccsds122_datamover_0_img_b1_row] [get_bd_nets ccsds122_datamover_0_compress_b2_base_addr] [get_bd_nets ccsds122_datamover_0_compress_done_valid] [get_bd_nets ccsds122_datamover_0_compress_b4_base_addr] [get_bd_nets ccsds122_datamover_0_s2mm_err] [get_bd_nets ccsds122_datamover_0_img_pan_row] [get_bd_nets ccsds122_datamover_0_img_b2_row] [get_bd_nets ccsds122_datamover_0_compress_pan_base_addr] [get_bd_nets ccsds122_datamover_0_compress_b3_base_addr] [get_bd_nets ccsds122_datamover_0_img_b4_row] [get_bd_nets ccsds122_datamover_0_img_b3_row] [get_bd_nets ccsds122_datamover_0_compress_b1_base_addr] [get_bd_cells ila_0]
|
||
|
|
startgroup
|
||
|
|
set_property CONFIG.C_NUM_MONITOR_SLOTS {5} [get_bd_cells system_ila_0]
|
||
|
|
endgroup
|
||
|
|
startgroup
|
||
|
|
set_property CONFIG.NUM_SI {4} [get_bd_cells smartconnect_0]
|
||
|
|
endgroup
|
||
|
|
connect_bd_intf_net [get_bd_intf_pins system_ila_0/SLOT_3_AXI] [get_bd_intf_pins smartconnect_0/S02_AXI]
|
||
|
|
connect_bd_intf_net [get_bd_intf_pins system_ila_0/SLOT_4_AXI] [get_bd_intf_pins smartconnect_0/S03_AXI]
|
||
|
|
regenerate_bd_layout
|
||
|
|
validate_bd_design
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x8000_0000 [ 64K ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x8000_0000 [ 64K ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x8000_0000 [ 64K ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S03_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x8000_0000 [ 64K ]> from slave interface '/smartconnect_0/S03_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_1: SmartConnect design_1_smartconnect_0_1 is in High-performance Mode.
|
||
|
|
xit::source_ipfile: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 3822.754 ; gain = 0.004
|
||
|
|
CRITICAL WARNING: [BD 41-1343] Reset pin /ddr4_0/c0_ddr4_aresetn (associated clock /ddr4_0/c0_ddr4_ui_clk) is connected to reset source /proc_sys_reset_0/peripheral_aresetn (synchronous to clock source /ddr4_0/addn_ui_clkout1).
|
||
|
|
This may prevent design from meeting timing. Please add Processor System Reset module to create a reset that is synchronous to the associated clock source /ddr4_0/c0_ddr4_ui_clk.
|
||
|
|
CRITICAL WARNING: [BD 41-1343] Reset pin /system_ila_1/resetn (associated clock /system_ila_1/clk) is connected to reset source /proc_sys_reset_0/peripheral_aresetn (synchronous to clock source /ddr4_0/addn_ui_clkout1).
|
||
|
|
This may prevent design from meeting timing. Please add Processor System Reset module to create a reset that is synchronous to the associated clock source /ddr4_0/c0_ddr4_ui_clk.
|
||
|
|
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ddr4_0/C0_DDR4_S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
||
|
|
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ddr4_0/C0_DDR4_S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
||
|
|
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
|
||
|
|
Please check your design and connect them as needed:
|
||
|
|
/ccsds122_axil_slave_0/img_gen_busy
|
||
|
|
/ccsds122_axil_slave_0/img_gen_done
|
||
|
|
|
||
|
|
validate_bd_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 3822.754 ; gain = 0.215
|
||
|
|
delete_bd_objs [get_bd_nets addn_ui_clkout1]
|
||
|
|
connect_bd_net [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins ddr4_0/c0_ddr4_ui_clk]
|
||
|
|
connect_bd_net [get_bd_pins ddr4_0/addn_ui_clkout1] [get_bd_pins system_ila_0/clk]
|
||
|
|
connect_bd_net [get_bd_pins ddr4_0/addn_ui_clkout1] [get_bd_pins smartconnect_0/aclk]
|
||
|
|
connect_bd_net [get_bd_pins ddr4_0/addn_ui_clkout1] [get_bd_pins ccsds122_axil_slave_0/clk]
|
||
|
|
connect_bd_net [get_bd_pins ddr4_0/addn_ui_clkout1] [get_bd_pins ccsds122_datamover_0/clk]
|
||
|
|
connect_bd_net [get_bd_pins ddr4_0/addn_ui_clkout1] [get_bd_pins ccsds122_datamover_0/m_axi_mm2s_aclk]
|
||
|
|
connect_bd_net [get_bd_pins ddr4_0/addn_ui_clkout1] [get_bd_pins ccsds122_datamover_0/m_axis_mm2s_cmdsts_aclk]
|
||
|
|
connect_bd_net [get_bd_pins ddr4_0/addn_ui_clkout1] [get_bd_pins ccsds122_datamover_0/m_axi_s2mm_aclk]
|
||
|
|
connect_bd_net [get_bd_pins ddr4_0/addn_ui_clkout1] [get_bd_pins ccsds122_datamover_0/m_axis_s2mm_cmdsts_awclk]
|
||
|
|
connect_bd_net [get_bd_pins ddr4_0/addn_ui_clkout1] [get_bd_pins ccsds_uart_axi_0/clk]
|
||
|
|
regenerate_bd_layout
|
||
|
|
validate_bd_design
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x8000_0000 [ 64K ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x8000_0000 [ 64K ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x8000_0000 [ 64K ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S03_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x8000_0000 [ 64K ]> from slave interface '/smartconnect_0/S03_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_1: SmartConnect design_1_smartconnect_0_1 is in High-performance Mode.
|
||
|
|
xit::source_ipfile: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 3845.828 ; gain = 0.242
|
||
|
|
CRITICAL WARNING: [BD 41-1343] Reset pin /ccsds122_datamover_0/m_axi_mm2s_aresetn (associated clock /ccsds122_datamover_0/m_axi_mm2s_aclk) is connected to reset source /proc_sys_reset_0/peripheral_aresetn (synchronous to clock source /ddr4_0/c0_ddr4_ui_clk).
|
||
|
|
This may prevent design from meeting timing. Please add Processor System Reset module to create a reset that is synchronous to the associated clock source /ddr4_0/addn_ui_clkout1.
|
||
|
|
CRITICAL WARNING: [BD 41-1343] Reset pin /ccsds122_datamover_0/m_axis_mm2s_cmdsts_aresetn (associated clock /ccsds122_datamover_0/m_axis_mm2s_cmdsts_aclk) is connected to reset source /proc_sys_reset_0/peripheral_aresetn (synchronous to clock source /ddr4_0/c0_ddr4_ui_clk).
|
||
|
|
This may prevent design from meeting timing. Please add Processor System Reset module to create a reset that is synchronous to the associated clock source /ddr4_0/addn_ui_clkout1.
|
||
|
|
CRITICAL WARNING: [BD 41-1343] Reset pin /ccsds122_datamover_0/m_axi_s2mm_aresetn (associated clock /ccsds122_datamover_0/m_axi_s2mm_aclk) is connected to reset source /proc_sys_reset_0/peripheral_aresetn (synchronous to clock source /ddr4_0/c0_ddr4_ui_clk).
|
||
|
|
This may prevent design from meeting timing. Please add Processor System Reset module to create a reset that is synchronous to the associated clock source /ddr4_0/addn_ui_clkout1.
|
||
|
|
CRITICAL WARNING: [BD 41-1343] Reset pin /system_ila_0/resetn (associated clock /system_ila_0/clk) is connected to reset source /proc_sys_reset_0/peripheral_aresetn (synchronous to clock source /ddr4_0/c0_ddr4_ui_clk).
|
||
|
|
This may prevent design from meeting timing. Please add Processor System Reset module to create a reset that is synchronous to the associated clock source /ddr4_0/addn_ui_clkout1.
|
||
|
|
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ddr4_0/C0_DDR4_S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
||
|
|
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ddr4_0/C0_DDR4_S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
||
|
|
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
|
||
|
|
Please check your design and connect them as needed:
|
||
|
|
/ccsds122_axil_slave_0/img_gen_busy
|
||
|
|
/ccsds122_axil_slave_0/img_gen_done
|
||
|
|
|
||
|
|
validate_bd_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 3868.344 ; gain = 38.328
|
||
|
|
delete_bd_objs [get_bd_nets ddr4_ui_clk]
|
||
|
|
connect_bd_net [get_bd_pins ddr4_0/c0_ddr4_ui_clk] [get_bd_pins smartconnect_0/aclk1]
|
||
|
|
connect_bd_net [get_bd_pins ddr4_0/c0_ddr4_ui_clk] [get_bd_pins system_ila_1/clk]
|
||
|
|
copy_bd_objs / [get_bd_cells {proc_sys_reset_0}]
|
||
|
|
connect_bd_net [get_bd_pins ddr4_0/addn_ui_clkout1] [get_bd_pins proc_sys_reset_0/slowest_sync_clk]
|
||
|
|
delete_bd_objs [get_bd_nets s_aresetn_0_1]
|
||
|
|
undo
|
||
|
|
INFO: [Common 17-17] undo 'delete_bd_objs [get_bd_nets s_aresetn_0_1]'
|
||
|
|
delete_bd_objs [get_bd_nets s_aresetn_0_1]
|
||
|
|
connect_bd_net [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins ccsds_uart_axi_0/rst_n]
|
||
|
|
connect_bd_net [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins ccsds122_datamover_0/rst_n]
|
||
|
|
connect_bd_net [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins ccsds122_datamover_0/m_axi_mm2s_aresetn]
|
||
|
|
connect_bd_net [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins ccsds122_datamover_0/m_axis_mm2s_cmdsts_aresetn]
|
||
|
|
connect_bd_net [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins ccsds122_datamover_0/m_axi_s2mm_aresetn]
|
||
|
|
connect_bd_net [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins ccsds122_datamover_0/m_axis_s2mm_cmdsts_aresetn]
|
||
|
|
connect_bd_net [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins ccsds122_axil_slave_0/rst_n]
|
||
|
|
connect_bd_net [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins smartconnect_0/aresetn]
|
||
|
|
connect_bd_net [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins system_ila_0/resetn]
|
||
|
|
connect_bd_net [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins ddr4_0/c0_ddr4_aresetn]
|
||
|
|
connect_bd_net [get_bd_pins ddr4_0/c0_ddr4_ui_clk] [get_bd_pins proc_sys_reset_1/slowest_sync_clk]
|
||
|
|
connect_bd_net [get_bd_pins ddr4_0/c0_ddr4_ui_clk_sync_rst] [get_bd_pins proc_sys_reset_1/ext_reset_in]
|
||
|
|
connect_bd_net [get_bd_pins proc_sys_reset_1/peripheral_aresetn] [get_bd_pins system_ila_1/resetn]
|
||
|
|
regenerate_bd_layout
|
||
|
|
validate_bd_design
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x8000_0000 [ 64K ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x8000_0000 [ 64K ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x8000_0000 [ 64K ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S03_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x8000_0000 [ 64K ]> from slave interface '/smartconnect_0/S03_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_1: SmartConnect design_1_smartconnect_0_1 is in High-performance Mode.
|
||
|
|
xit::source_ipfile: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3943.680 ; gain = 0.000
|
||
|
|
CRITICAL WARNING: [BD 41-1344] Reset pin /ddr4_0/c0_ddr4_aresetn (associated clock /ddr4_0/c0_ddr4_ui_clk) is connected to reset source /proc_sys_reset_0/peripheral_aresetn (synchronous to clock source /ddr4_0/addn_ui_clkout1).
|
||
|
|
This may prevent design from meeting timing. Instead it should be connected to reset source /proc_sys_reset_1/peripheral_aresetn.
|
||
|
|
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ddr4_0/C0_DDR4_S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
||
|
|
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ddr4_0/C0_DDR4_S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
||
|
|
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
|
||
|
|
Please check your design and connect them as needed:
|
||
|
|
/ccsds122_axil_slave_0/img_gen_busy
|
||
|
|
/ccsds122_axil_slave_0/img_gen_done
|
||
|
|
|
||
|
|
validate_bd_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 3943.680 ; gain = 0.000
|
||
|
|
delete_bd_objs [get_bd_nets proc_sys_reset_0_peripheral_aresetn]
|
||
|
|
connect_bd_net [get_bd_pins ddr4_0/c0_ddr4_aresetn] [get_bd_pins proc_sys_reset_1/peripheral_aresetn]
|
||
|
|
connect_bd_net [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins ccsds_uart_axi_0/rst_n]
|
||
|
|
connect_bd_net [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins ccsds122_datamover_0/rst_n]
|
||
|
|
connect_bd_net [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins ccsds122_datamover_0/m_axi_mm2s_aresetn]
|
||
|
|
connect_bd_net [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins ccsds122_datamover_0/m_axis_mm2s_cmdsts_aresetn]
|
||
|
|
connect_bd_net [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins ccsds122_datamover_0/m_axi_s2mm_aresetn]
|
||
|
|
connect_bd_net [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins ccsds122_datamover_0/m_axis_s2mm_cmdsts_aresetn]
|
||
|
|
connect_bd_net [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins ccsds122_axil_slave_0/rst_n]
|
||
|
|
connect_bd_net [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins smartconnect_0/aresetn]
|
||
|
|
connect_bd_net [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins system_ila_0/resetn]
|
||
|
|
regenerate_bd_layout
|
||
|
|
validate_bd_design
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x8000_0000 [ 64K ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x8000_0000 [ 64K ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x8000_0000 [ 64K ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S03_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x8000_0000 [ 64K ]> from slave interface '/smartconnect_0/S03_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_1: SmartConnect design_1_smartconnect_0_1 is in High-performance Mode.
|
||
|
|
xit::source_ipfile: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 3956.730 ; gain = 9.344
|
||
|
|
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ddr4_0/C0_DDR4_S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
||
|
|
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ddr4_0/C0_DDR4_S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
||
|
|
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
|
||
|
|
Please check your design and connect them as needed:
|
||
|
|
/ccsds122_axil_slave_0/img_gen_busy
|
||
|
|
/ccsds122_axil_slave_0/img_gen_done
|
||
|
|
|
||
|
|
validate_bd_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 3983.473 ; gain = 39.793
|
||
|
|
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
INFO: [BD 41-1662] The design 'design_1.bd' is already validated. Therefore parameter propagation will not be re-run.
|
||
|
|
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
|
||
|
|
Please check your design and connect them as needed:
|
||
|
|
/ccsds122_axil_slave_0/img_gen_busy
|
||
|
|
/ccsds122_axil_slave_0/img_gen_done
|
||
|
|
|
||
|
|
Wrote : <C:\proj\xc7v_ccsds122_datamover_uart\ccsds122_storage.srcs\sources_1\bd\design_1\design_1.bd>
|
||
|
|
Wrote : <C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
|
||
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
|
||
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/sim/design_1.v
|
||
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
|
||
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/hw_handoff/design_1_smartconnect_0_1.hwh
|
||
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/synth/design_1_smartconnect_0_1.hwdef
|
||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block smartconnect_0 .
|
||
|
|
INFO: [BD 41-1637] Generated targets are already up-to-date for block design 'bd_45eb' - hence not re-generating.
|
||
|
|
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_ooc.xdc'
|
||
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/hw_handoff/design_1_system_ila_0_0.hwh
|
||
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/synth/design_1_system_ila_0_0.hwdef
|
||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block system_ila_0 .
|
||
|
|
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_ooc.xdc'
|
||
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/hw_handoff/design_1_system_ila_0_1.hwh
|
||
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/synth/design_1_system_ila_0_1.hwdef
|
||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block system_ila_1 .
|
||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_1 .
|
||
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh
|
||
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.hwdef
|
||
|
|
generate_target: Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 4059.430 ; gain = 75.957
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_smartconnect_0_1
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_system_ila_0_0
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_1] }
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_system_ila_0_1
|
||
|
|
INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry 754f7c0da7d9e35f to dir: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/5/754f7c0da7d9e35f/design_1_system_ila_0_1.dcp to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1.dcp.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1.dcp
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/5/754f7c0da7d9e35f/design_1_system_ila_0_1_sim_netlist.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_sim_netlist.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_sim_netlist.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/5/754f7c0da7d9e35f/design_1_system_ila_0_1_sim_netlist.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_sim_netlist.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_sim_netlist.vhdl
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/5/754f7c0da7d9e35f/design_1_system_ila_0_1_stub.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_stub.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_stub.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/5/754f7c0da7d9e35f/design_1_system_ila_0_1_stub.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_stub.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_stub.vhdl
|
||
|
|
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_system_ila_0_1, cache-ID = 754f7c0da7d9e35f; cache size = 4904.112 MB.
|
||
|
|
config_ip_cache: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 4059.430 ; gain = 0.000
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_proc_sys_reset_0_1] }
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_proc_sys_reset_0_1
|
||
|
|
INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry a4b02069820e10bb to dir: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/a/4/a4b02069820e10bb/design_1_proc_sys_reset_0_0.dcp to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1.dcp.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1.dcp
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/a/4/a4b02069820e10bb/design_1_proc_sys_reset_0_0_sim_netlist.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1_sim_netlist.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1_sim_netlist.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/a/4/a4b02069820e10bb/design_1_proc_sys_reset_0_0_sim_netlist.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1_sim_netlist.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1_sim_netlist.vhdl
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/a/4/a4b02069820e10bb/design_1_proc_sys_reset_0_0_stub.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1_stub.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1_stub.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/a/4/a4b02069820e10bb/design_1_proc_sys_reset_0_0_stub.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1_stub.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1_stub.vhdl
|
||
|
|
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_proc_sys_reset_0_1, cache-ID = a4b02069820e10bb; cache size = 4904.112 MB.
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
||
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
launch_runs design_1_smartconnect_0_1_synth_1 design_1_system_ila_0_0_synth_1 -jobs 24
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_smartconnect_0_1
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_system_ila_0_0
|
||
|
|
[Mon Jul 6 17:12:38 2026] Launched design_1_smartconnect_0_1_synth_1, design_1_system_ila_0_0_synth_1...
|
||
|
|
Run output will be captured here:
|
||
|
|
design_1_smartconnect_0_1_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_smartconnect_0_1_synth_1/runme.log
|
||
|
|
design_1_system_ila_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_system_ila_0_0_synth_1/runme.log
|
||
|
|
export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
||
|
|
reset_run synth_1_copy_1
|
||
|
|
INFO: [Project 1-1161] Replacing file C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/utils_1/imports/synth_1/design_1_wrapper.dcp with file C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1_copy_1/design_1_wrapper.dcp
|
||
|
|
WARNING: [Vivado 12-1017] Problems encountered:
|
||
|
|
1. Failed to delete one or more files in run directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1_copy_1
|
||
|
|
|
||
|
|
launch_runs impl_2 -to_step write_bitstream -jobs 24
|
||
|
|
INFO: [IP_Flow 19-6930] IPCACHE: runCacheChecks() number of threads = 8
|
||
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_smartconnect_0_1
|
||
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_system_ila_0_0
|
||
|
|
INFO: [IP_Flow 19-8020] IPCACHE: runCacheChecks() calling threadPool finishWork()
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_smartconnect_0_1
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_system_ila_0_0
|
||
|
|
[Mon Jul 6 17:13:14 2026] Launched design_1_smartconnect_0_1_synth_1, design_1_system_ila_0_0_synth_1, synth_1_copy_1...
|
||
|
|
Run output will be captured here:
|
||
|
|
design_1_smartconnect_0_1_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_smartconnect_0_1_synth_1/runme.log
|
||
|
|
design_1_system_ila_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_system_ila_0_0_synth_1/runme.log
|
||
|
|
synth_1_copy_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1_copy_1/runme.log
|
||
|
|
[Mon Jul 6 17:13:14 2026] Launched impl_2...
|
||
|
|
Run output will be captured here: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/impl_2/runme.log
|
||
|
|
open_run synth_1_copy_1 -name synth_1_copy_1
|
||
|
|
Design is defaulting to impl run constrset: constrs_1
|
||
|
|
Design is defaulting to synth run part: xcku5p-ffvb676-2-i
|
||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_axil_slave_0_0/design_1_ccsds122_axil_slave_0_0.dcp' for cell 'design_1_i/ccsds122_axil_slave_0'
|
||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/design_1_ccsds122_datamover_0_0.dcp' for cell 'design_1_i/ccsds122_datamover_0'
|
||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/design_1_ccsds_uart_axi_0_0.dcp' for cell 'design_1_i/ccsds_uart_axi_0'
|
||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/design_1_ddr4_0_0.dcp' for cell 'design_1_i/ddr4_0'
|
||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0.dcp' for cell 'design_1_i/proc_sys_reset_0'
|
||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1.dcp' for cell 'design_1_i/proc_sys_reset_1'
|
||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1.dcp' for cell 'design_1_i/smartconnect_0'
|
||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0.dcp' for cell 'design_1_i/system_ila_0'
|
||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1.dcp' for cell 'design_1_i/system_ila_1'
|
||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_4/design_1_util_vector_logic_0_4.dcp' for cell 'design_1_i/util_vector_logic_0'
|
||
|
|
Netlist sorting complete. Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 4723.906 ; gain = 52.730
|
||
|
|
INFO: [Netlist 29-17] Analyzing 7860 Unisim elements for replacement
|
||
|
|
INFO: [Netlist 29-28] Unisim Transformation completed in 3 CPU seconds
|
||
|
|
INFO: [Project 1-479] Netlist was created with Vivado 2023.2
|
||
|
|
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||
|
|
INFO: [Chipscope 16-324] Core: design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl/u_ila_1 UUID: 9c1f4e79-feb5-532b-8648-e7237e71eda8
|
||
|
|
INFO: [Chipscope 16-324] Core: design_1_i/ccsds_uart_axi_0/inst/u_core/u_vio_soft_rst UUID: 62b2038d-2768-5030-a5ac-9430fcab7cee
|
||
|
|
INFO: [Chipscope 16-324] Core: design_1_i/ddr4_0 UUID: 5055ccf3-ab28-5f28-a888-99587c896c7c
|
||
|
|
INFO: [Chipscope 16-324] Core: design_1_i/system_ila_0/inst/ila_lib UUID: cd4c83c8-23a6-596d-99ad-09be1335c6b0
|
||
|
|
INFO: [Chipscope 16-324] Core: design_1_i/system_ila_1/inst/ila_lib UUID: 1ac8c4c2-d1ac-5faa-b5d9-9a6ca09c91e7
|
||
|
|
INFO: [Common 17-41] Interrupt caught. Command should exit soon.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'U0' within module 'fifo_generator_0' for instance 'design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_bubble_removal/u_pack_fifo'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/fifo_generator_0/fifo_generator_0.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'U0' within module 'axi_datamover_0' for instance 'design_1_i/ccsds122_datamover_0/inst/u_datamover'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/axi_datamover_0/axi_datamover_0.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'inst' within module 'ila_1' for instance 'design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl/u_ila_1'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/ila_1/ila_v6_2/constraints/ila_impl.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'inst' within module 'ila_1' for instance 'design_1_i/ccsds122_datamover_0/inst/u_stream_ctrl/u_ila_1'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/ila_1/ila_v6_2/constraints/ila.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'U0' within module 'bd_886d_psr0_0' for instance 'design_1_i/smartconnect_0/inst/clk_map/psr0'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_1/bd_886d_psr0_0_board.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'U0' within module 'bd_886d_psr0_0' for instance 'design_1_i/smartconnect_0/inst/clk_map/psr0'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_1/bd_886d_psr0_0.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'U0' within module 'bd_886d_psr_aclk_0' for instance 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_2/bd_886d_psr_aclk_0_board.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'U0' within module 'bd_886d_psr_aclk_0' for instance 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_2/bd_886d_psr_aclk_0.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'U0' within module 'bd_886d_psr_aclk1_0' for instance 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk1'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_3/bd_886d_psr_aclk1_0_board.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'U0' within module 'bd_886d_psr_aclk1_0' for instance 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk1'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_3/bd_886d_psr_aclk1_0.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'inst' within module 'bd_886d_sarn_0' for instance 'design_1_i/smartconnect_0/inst/s00_nodes/s00_ar_node'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'inst' within module 'bd_886d_srn_0' for instance 'design_1_i/smartconnect_0/inst/s00_nodes/s00_r_node'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'inst' within module 'bd_886d_sawn_0' for instance 'design_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'inst' within module 'bd_886d_swn_0' for instance 'design_1_i/smartconnect_0/inst/s01_nodes/s01_w_node'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_20/bd_886d_swn_0_clocks.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'inst' within module 'bd_886d_sbn_0' for instance 'design_1_i/smartconnect_0/inst/s01_nodes/s01_b_node'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_21/bd_886d_sbn_0_clocks.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'inst' within module 'bd_886d_sarn_1' for instance 'design_1_i/smartconnect_0/inst/s02_nodes/s02_ar_node'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_26/bd_886d_sarn_1_clocks.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'inst' within module 'bd_886d_srn_1' for instance 'design_1_i/smartconnect_0/inst/s02_nodes/s02_r_node'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_27/bd_886d_srn_1_clocks.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'inst' within module 'bd_886d_sawn_1' for instance 'design_1_i/smartconnect_0/inst/s02_nodes/s02_aw_node'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_28/bd_886d_sawn_1_clocks.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'inst' within module 'bd_886d_swn_1' for instance 'design_1_i/smartconnect_0/inst/s02_nodes/s02_w_node'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_29/bd_886d_swn_1_clocks.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'inst' within module 'bd_886d_sbn_1' for instance 'design_1_i/smartconnect_0/inst/s02_nodes/s02_b_node'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_30/bd_886d_sbn_1_clocks.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'inst' within module 'bd_886d_sarn_2' for instance 'design_1_i/smartconnect_0/inst/s03_nodes/s03_ar_node'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_35/bd_886d_sarn_2_clocks.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'inst' within module 'bd_886d_srn_2' for instance 'design_1_i/smartconnect_0/inst/s03_nodes/s03_r_node'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_36/bd_886d_srn_2_clocks.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'inst' within module 'bd_886d_sawn_2' for instance 'design_1_i/smartconnect_0/inst/s03_nodes/s03_aw_node'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_37/bd_886d_sawn_2_clocks.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'inst' within module 'bd_886d_swn_2' for instance 'design_1_i/smartconnect_0/inst/s03_nodes/s03_w_node'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_38/bd_886d_swn_2_clocks.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'inst' within module 'bd_886d_sbn_2' for instance 'design_1_i/smartconnect_0/inst/s03_nodes/s03_b_node'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_39/bd_886d_sbn_2_clocks.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'inst' within module 'bd_886d_m00arn_0' for instance 'design_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_41/bd_886d_m00arn_0_clocks.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'inst' within module 'bd_886d_m00rn_0' for instance 'design_1_i/smartconnect_0/inst/m00_nodes/m00_r_node'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_42/bd_886d_m00rn_0_clocks.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'inst' within module 'bd_886d_m00awn_0' for instance 'design_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_43/bd_886d_m00awn_0_clocks.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'inst' within module 'bd_886d_m00wn_0' for instance 'design_1_i/smartconnect_0/inst/m00_nodes/m00_w_node'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_44/bd_886d_m00wn_0_clocks.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'inst' within module 'bd_886d_m00bn_0' for instance 'design_1_i/smartconnect_0/inst/m00_nodes/m00_b_node'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_45/bd_886d_m00bn_0_clocks.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'inst' within module 'bd_886d_m01arn_0' for instance 'design_1_i/smartconnect_0/inst/m01_nodes/m01_ar_node'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_48/bd_886d_m01arn_0_clocks.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'inst' within module 'bd_886d_m01rn_0' for instance 'design_1_i/smartconnect_0/inst/m01_nodes/m01_r_node'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_49/bd_886d_m01rn_0_clocks.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'inst' within module 'bd_886d_m01awn_0' for instance 'design_1_i/smartconnect_0/inst/m01_nodes/m01_aw_node'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_50/bd_886d_m01awn_0_clocks.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'inst' within module 'bd_886d_m01wn_0' for instance 'design_1_i/smartconnect_0/inst/m01_nodes/m01_w_node'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_51/bd_886d_m01wn_0_clocks.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'inst' within module 'bd_886d_m01bn_0' for instance 'design_1_i/smartconnect_0/inst/m01_nodes/m01_b_node'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_52/bd_886d_m01bn_0_clocks.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'inst' within module 'design_1_smartconnect_0_1' for instance 'design_1_i/smartconnect_0'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/smartconnect.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'U0' within module 'design_1_proc_sys_reset_0_0' for instance 'design_1_i/proc_sys_reset_0'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0_board.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'U0' within module 'design_1_proc_sys_reset_0_0' for instance 'design_1_i/proc_sys_reset_0'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0.xdc will not be read for this cell.
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/src/vio_0/vio_0.xdc] for cell 'design_1_i/ccsds_uart_axi_0/inst/u_core/u_vio_soft_rst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/src/vio_0/vio_0.xdc] for cell 'design_1_i/ccsds_uart_axi_0/inst/u_core/u_vio_soft_rst'
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'U0' within module 'bd_45eb_microblaze_I_0' for instance 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_0/bd_45eb_microblaze_I_0.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'U0' within module 'bd_45eb_rst_0_0' for instance 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_1/bd_45eb_rst_0_0_board.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'U0' within module 'bd_45eb_rst_0_0' for instance 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_1/bd_45eb_rst_0_0.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'U0' within module 'bd_45eb_ilmb_0' for instance 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_2/bd_45eb_ilmb_0.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'U0' within module 'bd_45eb_dlmb_0' for instance 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/dlmb'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_3/bd_45eb_dlmb_0.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'U0' within module 'bd_45eb_iomodule_0_0' for instance 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_10/bd_45eb_iomodule_0_0_board.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'inst' within module 'design_1_ddr4_0_0_microblaze_mcs' for instance 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/ip_0/design_1_ddr4_0_0_microblaze_mcs_board.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'inst' within module 'design_1_ddr4_0_0' for instance 'design_1_i/ddr4_0'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/par/design_1_ddr4_0_0.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'inst' within module 'bd_f60c_ila_lib_0' for instance 'design_1_i/system_ila_0/inst/ila_lib'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/ila_v6_2/constraints/ila_impl.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'inst' within module 'bd_f60c_ila_lib_0' for instance 'design_1_i/system_ila_0/inst/ila_lib'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/ila_v6_2/constraints/ila.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'inst' within module 'bd_36cd_ila_lib_0' for instance 'design_1_i/system_ila_1/inst/ila_lib'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/ip/ip_0/ila_v6_2/constraints/ila_impl.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'inst' within module 'bd_36cd_ila_lib_0' for instance 'design_1_i/system_ila_1/inst/ila_lib'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/ip/ip_0/ila_v6_2/constraints/ila.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'U0' within module 'design_1_proc_sys_reset_0_1' for instance 'design_1_i/proc_sys_reset_1'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1_board.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'U0' within module 'design_1_proc_sys_reset_0_1' for instance 'design_1_i/proc_sys_reset_1'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1.xdc will not be read for this cell.
|
||
|
|
Parsing XDC File [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/constrs_1/new/ccsds122_storage.xdc]
|
||
|
|
Finished Parsing XDC File [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/constrs_1/new/ccsds122_storage.xdc]
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'U0' within module 'axi_datamover_0' for instance 'design_1_i/ccsds122_datamover_0/inst/u_datamover'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/axi_datamover_0/axi_datamover_0_clocks.xdc will not be read for this cell.
|
||
|
|
CRITICAL WARNING: [Designutils 20-1275] Could not find cell 'inst' within module 'design_1_ddr4_0_0' for instance 'design_1_i/ddr4_0'. The XDC file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/design_1_ddr4_0_0_board.xdc will not be read for this cell.
|
||
|
|
INFO: [Project 1-1714] 345 XPM XDC files have been applied to the design.
|
||
|
|
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||
|
|
open_run: Time (s): cpu = 00:01:19 ; elapsed = 00:01:18 . Memory (MB): peak = 5223.426 ; gain = 1134.781
|
||
|
|
INFO: [Common 17-344] 'open_run' was cancelled
|
||
|
|
delete_bd_objs [get_bd_intf_nets ccsds_uart_axi_0_m_axi]
|
||
|
|
delete_bd_objs [get_bd_intf_nets ccsds_uart_axi_0_m_axil]
|
||
|
|
connect_bd_intf_net [get_bd_intf_pins system_ila_0/SLOT_3_AXI] [get_bd_intf_pins smartconnect_0/S02_AXI]
|
||
|
|
connect_bd_intf_net [get_bd_intf_pins smartconnect_0/S02_AXI] [get_bd_intf_pins ccsds_uart_axi_0/m_axil]
|
||
|
|
connect_bd_intf_net [get_bd_intf_pins ccsds_uart_axi_0/m_axi] [get_bd_intf_pins smartconnect_0/S03_AXI]
|
||
|
|
startgroup
|
||
|
|
set_property CONFIG.C_NUM_MONITOR_SLOTS {4} [get_bd_cells system_ila_0]
|
||
|
|
endgroup
|
||
|
|
WARNING: [IP_Flow 19-4318] IP-XACT file does not exist: c:/proj/FPGA_DESIGN_IP/ccsds_uart_axi/component.xml. It will be created.
|
||
|
|
update_ip_catalog -rebuild -scan_changes
|
||
|
|
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||
|
|
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/proj/FPGA_DESIGN_IP'.
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
upgrade_ip [get_ips {design_1_ccsds122_datamover_0_0 design_1_ccsds_uart_axi_0_0}] -log ip_upgrade.log
|
||
|
|
Upgrading 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd'
|
||
|
|
INFO: [IP_Flow 19-3420] Updated design_1_ccsds122_datamover_0_0 to use current project options
|
||
|
|
INFO: [IP_Flow 19-3420] Updated design_1_ccsds_uart_axi_0_0 to use current project options
|
||
|
|
Wrote : <C:\proj\xc7v_ccsds122_datamover_uart\ccsds122_storage.srcs\sources_1\bd\design_1\design_1.bd>
|
||
|
|
Wrote : <C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
|
||
|
|
INFO: [Coretcl 2-1525] Wrote upgrade log to 'C:/proj/xc7v_ccsds122_datamover_uart/ip_upgrade.log'.
|
||
|
|
export_ip_user_files -of_objects [get_ips {design_1_ccsds122_datamover_0_0 design_1_ccsds_uart_axi_0_0}] -no_script -sync -force -quiet
|
||
|
|
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x8000_0000 [ 64K ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x8000_0000 [ 64K ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x8000_0000 [ 64K ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S03_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x8000_0000 [ 64K ]> from slave interface '/smartconnect_0/S03_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_1: SmartConnect design_1_smartconnect_0_1 is in High-performance Mode.
|
||
|
|
xit::source_ipfile: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 5501.926 ; gain = 0.191
|
||
|
|
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ddr4_0/C0_DDR4_S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
||
|
|
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ddr4_0/C0_DDR4_S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
||
|
|
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
|
||
|
|
Please check your design and connect them as needed:
|
||
|
|
/ccsds122_axil_slave_0/img_gen_busy
|
||
|
|
/ccsds122_axil_slave_0/img_gen_done
|
||
|
|
|
||
|
|
Wrote : <C:\proj\xc7v_ccsds122_datamover_uart\ccsds122_storage.srcs\sources_1\bd\design_1\design_1.bd>
|
||
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
|
||
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/sim/design_1.v
|
||
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
|
||
|
|
WARNING: [IP_Flow 19-640] IP 'design_1_ccsds122_datamover_0_0' does not support specified targets: Implementation. Running all supported targets by default.
|
||
|
|
WARNING: [IP_Flow 19-640] IP 'design_1_ccsds122_datamover_0_0' does not support specified targets: Implementation. Running all supported targets by default.
|
||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block ccsds122_datamover_0 .
|
||
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/hw_handoff/design_1_smartconnect_0_1.hwh
|
||
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/synth/design_1_smartconnect_0_1.hwdef
|
||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block smartconnect_0 .
|
||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block ccsds_uart_axi_0 .
|
||
|
|
INFO: [BD 41-1637] Generated targets are already up-to-date for block design 'bd_45eb' - hence not re-generating.
|
||
|
|
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_ooc.xdc'
|
||
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/hw_handoff/design_1_system_ila_0_0.hwh
|
||
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/synth/design_1_system_ila_0_0.hwdef
|
||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block system_ila_0 .
|
||
|
|
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_ooc.xdc'
|
||
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/hw_handoff/design_1_system_ila_0_1.hwh
|
||
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/synth/design_1_system_ila_0_1.hwdef
|
||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block system_ila_1 .
|
||
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh
|
||
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.hwdef
|
||
|
|
generate_target: Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 5557.465 ; gain = 67.523
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_ccsds122_datamover_0_0] }
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds122_datamover_0_0
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_smartconnect_0_1
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_ccsds_uart_axi_0_0] }
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds_uart_axi_0_0
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_system_ila_0_0
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_1] }
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_system_ila_0_1
|
||
|
|
INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry 754f7c0da7d9e35f to dir: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/5/754f7c0da7d9e35f/design_1_system_ila_0_1.dcp to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1.dcp.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1.dcp
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/5/754f7c0da7d9e35f/design_1_system_ila_0_1_sim_netlist.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_sim_netlist.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_sim_netlist.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/5/754f7c0da7d9e35f/design_1_system_ila_0_1_sim_netlist.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_sim_netlist.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_sim_netlist.vhdl
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/5/754f7c0da7d9e35f/design_1_system_ila_0_1_stub.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_stub.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_stub.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/5/754f7c0da7d9e35f/design_1_system_ila_0_1_stub.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_stub.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_stub.vhdl
|
||
|
|
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_system_ila_0_1, cache-ID = 754f7c0da7d9e35f; cache size = 4985.523 MB.
|
||
|
|
config_ip_cache: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 5557.465 ; gain = 0.000
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
||
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
launch_runs design_1_ccsds122_datamover_0_0_synth_1 design_1_ccsds_uart_axi_0_0_synth_1 design_1_smartconnect_0_1_synth_1 design_1_system_ila_0_0_synth_1 -jobs 24
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds122_datamover_0_0
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds_uart_axi_0_0
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_smartconnect_0_1
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_system_ila_0_0
|
||
|
|
[Mon Jul 6 17:37:49 2026] Launched design_1_ccsds122_datamover_0_0_synth_1, design_1_ccsds_uart_axi_0_0_synth_1, design_1_smartconnect_0_1_synth_1, design_1_system_ila_0_0_synth_1...
|
||
|
|
Run output will be captured here:
|
||
|
|
design_1_ccsds122_datamover_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ccsds122_datamover_0_0_synth_1/runme.log
|
||
|
|
design_1_ccsds_uart_axi_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ccsds_uart_axi_0_0_synth_1/runme.log
|
||
|
|
design_1_smartconnect_0_1_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_smartconnect_0_1_synth_1/runme.log
|
||
|
|
design_1_system_ila_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_system_ila_0_0_synth_1/runme.log
|
||
|
|
export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
reset_run synth_1_copy_1
|
||
|
|
INFO: [Project 1-1161] Replacing file C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/utils_1/imports/synth_1/design_1_wrapper.dcp with file C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1_copy_1/design_1_wrapper.dcp
|
||
|
|
WARNING: [Vivado 12-1017] Problems encountered:
|
||
|
|
1. Failed to delete one or more files in run directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1_copy_1
|
||
|
|
|
||
|
|
launch_runs impl_2 -to_step write_bitstream -jobs 24
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds122_datamover_0_0
|
||
|
|
[Mon Jul 6 17:42:05 2026] Launched design_1_ccsds122_datamover_0_0_synth_1, synth_1_copy_1...
|
||
|
|
Run output will be captured here:
|
||
|
|
design_1_ccsds122_datamover_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ccsds122_datamover_0_0_synth_1/runme.log
|
||
|
|
synth_1_copy_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1_copy_1/runme.log
|
||
|
|
[Mon Jul 6 17:42:05 2026] Launched impl_2...
|
||
|
|
Run output will be captured here: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/impl_2/runme.log
|
||
|
|
open_run synth_1_copy_1 -name synth_1_copy_1
|
||
|
|
Design is defaulting to impl run constrset: constrs_1
|
||
|
|
Design is defaulting to synth run part: xcku5p-ffvb676-2-i
|
||
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|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_axil_slave_0_0/design_1_ccsds122_axil_slave_0_0.dcp' for cell 'design_1_i/ccsds122_axil_slave_0'
|
||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/design_1_ccsds122_datamover_0_0.dcp' for cell 'design_1_i/ccsds122_datamover_0'
|
||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/design_1_ccsds_uart_axi_0_0.dcp' for cell 'design_1_i/ccsds_uart_axi_0'
|
||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/design_1_ddr4_0_0.dcp' for cell 'design_1_i/ddr4_0'
|
||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0.dcp' for cell 'design_1_i/proc_sys_reset_0'
|
||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1.dcp' for cell 'design_1_i/proc_sys_reset_1'
|
||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1.dcp' for cell 'design_1_i/smartconnect_0'
|
||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0.dcp' for cell 'design_1_i/system_ila_0'
|
||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1.dcp' for cell 'design_1_i/system_ila_1'
|
||
|
|
INFO: [Project 1-454] Reading design checkpoint 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_util_vector_logic_0_4/design_1_util_vector_logic_0_4.dcp' for cell 'design_1_i/util_vector_logic_0'
|
||
|
|
Netlist sorting complete. Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 5557.465 ; gain = 0.000
|
||
|
|
INFO: [Netlist 29-17] Analyzing 7409 Unisim elements for replacement
|
||
|
|
INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds
|
||
|
|
INFO: [Project 1-479] Netlist was created with Vivado 2023.2
|
||
|
|
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||
|
|
INFO: [Chipscope 16-324] Core: design_1_i/ccsds_uart_axi_0/inst/u_core/u_ila UUID: 224cb1a1-1f43-5694-9b06-fc581d8cbbfe
|
||
|
|
INFO: [Chipscope 16-324] Core: design_1_i/ccsds_uart_axi_0/inst/u_core/u_vio_soft_rst UUID: 62b2038d-2768-5030-a5ac-9430fcab7cee
|
||
|
|
INFO: [Chipscope 16-324] Core: design_1_i/ddr4_0 UUID: 5055ccf3-ab28-5f28-a888-99587c896c7c
|
||
|
|
INFO: [Chipscope 16-324] Core: design_1_i/system_ila_0/inst/ila_lib UUID: cd4c83c8-23a6-596d-99ad-09be1335c6b0
|
||
|
|
INFO: [Chipscope 16-324] Core: design_1_i/system_ila_1/inst/ila_lib UUID: 1ac8c4c2-d1ac-5faa-b5d9-9a6ca09c91e7
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/axi_datamover_0/axi_datamover_0.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_datamover/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/axi_datamover_0/axi_datamover_0.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_datamover/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/fifo_generator_0/fifo_generator_0.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_bubble_removal/u_pack_fifo/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/fifo_generator_0/fifo_generator_0.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_compression_top/u_bubble_removal/u_pack_fifo/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_1/bd_886d_psr0_0_board.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr0/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_1/bd_886d_psr0_0_board.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr0/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_1/bd_886d_psr0_0.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr0/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_1/bd_886d_psr0_0.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr0/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_2/bd_886d_psr_aclk_0_board.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_2/bd_886d_psr_aclk_0_board.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_2/bd_886d_psr_aclk_0.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_2/bd_886d_psr_aclk_0.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_3/bd_886d_psr_aclk1_0_board.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk1/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_3/bd_886d_psr_aclk1_0_board.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk1/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_3/bd_886d_psr_aclk1_0.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk1/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_3/bd_886d_psr_aclk1_0.xdc] for cell 'design_1_i/smartconnect_0/inst/clk_map/psr_aclk1/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s00_nodes/s00_ar_node/inst'
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:49]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:52]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:55]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:59]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:63]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:66]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:70]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:73]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:76]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:79]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:85]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:88]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:91]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:94]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:97]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:100]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:104]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:107]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:110]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:113]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:116]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:119]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-13' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:122]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:125]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:128]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-13' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:131]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:134]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:137]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:140]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:143]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:146]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:149]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:152]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:155]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:161]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:164]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:167]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:171]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:174]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc:178]
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_13/bd_886d_sarn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s00_nodes/s00_ar_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst'
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:49]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:52]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:55]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:59]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:63]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:66]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:70]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:73]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:76]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:79]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:82]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:85]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:88]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:91]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:94]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:97]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:100]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:104]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:107]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:110]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:113]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:116]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:119]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-13' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:122]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:125]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:128]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-13' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:131]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:134]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:137]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:140]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:143]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:146]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:149]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:152]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:155]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:158]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:161]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:164]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:167]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:171]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:174]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc:178]
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_14/bd_886d_srn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s00_nodes/s00_r_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst'
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:49]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:52]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:55]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:59]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:63]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:66]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:70]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:73]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:76]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:79]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:85]
|
||
|
|
INFO: [Common 17-14] Message 'Vivado 12-180' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:88]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:88]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:91]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:94]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:97]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:100]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:104]
|
||
|
|
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:107]
|
||
|
|
INFO: [Common 17-14] Message 'Vivado_Tcl 4-921' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc:107]
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_19/bd_886d_sawn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_aw_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_20/bd_886d_swn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_20/bd_886d_swn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_w_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_21/bd_886d_sbn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_21/bd_886d_sbn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s01_nodes/s01_b_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_26/bd_886d_sarn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_ar_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_26/bd_886d_sarn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_ar_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_27/bd_886d_srn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_r_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_27/bd_886d_srn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_r_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_28/bd_886d_sawn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_aw_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_28/bd_886d_sawn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_aw_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_29/bd_886d_swn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_w_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_29/bd_886d_swn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_w_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_30/bd_886d_sbn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_b_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_30/bd_886d_sbn_1_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s02_nodes/s02_b_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_35/bd_886d_sarn_2_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s03_nodes/s03_ar_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_35/bd_886d_sarn_2_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s03_nodes/s03_ar_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_36/bd_886d_srn_2_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s03_nodes/s03_r_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_36/bd_886d_srn_2_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s03_nodes/s03_r_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_37/bd_886d_sawn_2_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s03_nodes/s03_aw_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_37/bd_886d_sawn_2_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s03_nodes/s03_aw_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_38/bd_886d_swn_2_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s03_nodes/s03_w_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_38/bd_886d_swn_2_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s03_nodes/s03_w_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_39/bd_886d_sbn_2_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s03_nodes/s03_b_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_39/bd_886d_sbn_2_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/s03_nodes/s03_b_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_41/bd_886d_m00arn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_41/bd_886d_m00arn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_ar_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_42/bd_886d_m00rn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_42/bd_886d_m00rn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_r_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_43/bd_886d_m00awn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_43/bd_886d_m00awn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_44/bd_886d_m00wn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_44/bd_886d_m00wn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_w_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_45/bd_886d_m00bn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_45/bd_886d_m00bn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m00_nodes/m00_b_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_48/bd_886d_m01arn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_ar_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_48/bd_886d_m01arn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_ar_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_49/bd_886d_m01rn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_r_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_49/bd_886d_m01rn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_r_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_50/bd_886d_m01awn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_aw_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_50/bd_886d_m01awn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_aw_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_51/bd_886d_m01wn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_w_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_51/bd_886d_m01wn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_w_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_52/bd_886d_m01bn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_b_node/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/ip/ip_52/bd_886d_m01bn_0_clocks.xdc] for cell 'design_1_i/smartconnect_0/inst/m01_nodes/m01_b_node/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/smartconnect.xdc] for cell 'design_1_i/smartconnect_0/inst'
|
||
|
|
WARNING: [Vivado_Tcl 4-919] Waiver ID 'CDC-1' -from list should not be empty. [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/smartconnect.xdc:1]
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/smartconnect.xdc] for cell 'design_1_i/smartconnect_0/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0_board.xdc] for cell 'design_1_i/proc_sys_reset_0/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0_board.xdc] for cell 'design_1_i/proc_sys_reset_0/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0.xdc] for cell 'design_1_i/proc_sys_reset_0/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_0/design_1_proc_sys_reset_0_0.xdc] for cell 'design_1_i/proc_sys_reset_0/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/src/vio_0/vio_0.xdc] for cell 'design_1_i/ccsds_uart_axi_0/inst/u_core/u_vio_soft_rst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/src/vio_0/vio_0.xdc] for cell 'design_1_i/ccsds_uart_axi_0/inst/u_core/u_vio_soft_rst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/src/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/ccsds_uart_axi_0/inst/u_core/u_ila/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/src/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/ccsds_uart_axi_0/inst/u_core/u_ila/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/src/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/ccsds_uart_axi_0/inst/u_core/u_ila/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds_uart_axi_0_0/src/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/ccsds_uart_axi_0/inst/u_core/u_ila/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_0/bd_45eb_microblaze_I_0.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_0/bd_45eb_microblaze_I_0.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_1/bd_45eb_rst_0_0_board.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_1/bd_45eb_rst_0_0_board.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_1/bd_45eb_rst_0_0.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_1/bd_45eb_rst_0_0.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_2/bd_45eb_ilmb_0.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_2/bd_45eb_ilmb_0.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_3/bd_45eb_dlmb_0.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/dlmb/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_3/bd_45eb_dlmb_0.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/dlmb/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_10/bd_45eb_iomodule_0_0_board.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/bd_0/ip/ip_10/bd_45eb_iomodule_0_0_board.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/ip_0/design_1_ddr4_0_0_microblaze_mcs_board.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/ip_0/design_1_ddr4_0_0_microblaze_mcs_board.xdc] for cell 'design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/par/design_1_ddr4_0_0.xdc] for cell 'design_1_i/ddr4_0/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/par/design_1_ddr4_0_0.xdc] for cell 'design_1_i/ddr4_0/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/system_ila_0/inst/ila_lib/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/system_ila_0/inst/ila_lib/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/system_ila_0/inst/ila_lib/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/system_ila_0/inst/ila_lib/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/ip/ip_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/system_ila_1/inst/ila_lib/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/ip/ip_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/system_ila_1/inst/ila_lib/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/ip/ip_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/system_ila_1/inst/ila_lib/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/ip/ip_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/system_ila_1/inst/ila_lib/inst'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1_board.xdc] for cell 'design_1_i/proc_sys_reset_1/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1_board.xdc] for cell 'design_1_i/proc_sys_reset_1/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1.xdc] for cell 'design_1_i/proc_sys_reset_1/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_proc_sys_reset_0_1/design_1_proc_sys_reset_0_1.xdc] for cell 'design_1_i/proc_sys_reset_1/U0'
|
||
|
|
Parsing XDC File [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/constrs_1/new/ccsds122_storage.xdc]
|
||
|
|
Finished Parsing XDC File [C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/constrs_1/new/ccsds122_storage.xdc]
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/axi_datamover_0/axi_datamover_0_clocks.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_datamover/U0'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ccsds122_datamover_0_0/src/axi_datamover_0/axi_datamover_0_clocks.xdc] for cell 'design_1_i/ccsds122_datamover_0/inst/u_datamover/U0'
|
||
|
|
Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/design_1_ddr4_0_0_board.xdc] for cell 'design_1_i/ddr4_0/inst'
|
||
|
|
Finished Parsing XDC File [c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/design_1_ddr4_0_0_board.xdc] for cell 'design_1_i/ddr4_0/inst'
|
||
|
|
INFO: [Project 1-1714] 345 XPM XDC files have been applied to the design.
|
||
|
|
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||
|
|
Generating merged BMM file for the design top 'design_1_wrapper'...
|
||
|
|
Generating merged BMM file for the design top 'design_1_ddr4_0_0'...
|
||
|
|
INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/sw/calibration_0/Debug/calibration_ddr.elf c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_ddr4_0_0/sw/calibration_0/Debug/calibration_ddr.elf
|
||
|
|
INFO: [Project 1-1687] 1078 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design.
|
||
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.186 . Memory (MB): peak = 6311.496 ; gain = 0.000
|
||
|
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
||
|
|
A total of 2578 instances were transformed.
|
||
|
|
CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 1448 instances
|
||
|
|
DSP48E1 => DSP48E2 (DSP_ALU, DSP_A_B_DATA, DSP_C_DATA, DSP_MULTIPLIER, DSP_M_DATA, DSP_OUTPUT, DSP_PREADD, DSP_PREADD_DATA): 3 instances
|
||
|
|
IBUF => IBUF (IBUFCTRL, INBUF): 2 instances
|
||
|
|
IBUFDS => IBUFDS (DIFFINBUF, IBUFCTRL): 1 instance
|
||
|
|
IOBUFDS => IOBUFDS (DIFFINBUF, IBUFCTRL, INV, OBUFT(x2)): 4 instances
|
||
|
|
IOBUFE3 => IOBUFE3 (IBUFCTRL, INBUF, OBUFT_DCIEN): 36 instances
|
||
|
|
LUT6_2 => LUT6_2 (LUT5, LUT6): 31 instances
|
||
|
|
OBUFDS => OBUFDS_DUAL_BUF (INV, OBUF(x2)): 1 instance
|
||
|
|
RAM16X1D => RAM32X1D (RAMD32(x2)): 12 instances
|
||
|
|
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 114 instances
|
||
|
|
RAM32M16 => RAM32M16 (RAMD32(x14), RAMS32(x2)): 924 instances
|
||
|
|
RAM32X1D => RAM32X1D (RAMD32(x2)): 2 instances
|
||
|
|
|
||
|
|
open_run: Time (s): cpu = 00:02:45 ; elapsed = 00:02:29 . Memory (MB): peak = 6311.496 ; gain = 754.031
|
||
|
|
report_utilization -name utilization_1
|
||
|
|
report_utilization: Time (s): cpu = 00:00:32 ; elapsed = 00:00:16 . Memory (MB): peak = 7238.828 ; gain = 923.770
|
||
|
|
close_design
|
||
|
|
startgroup
|
||
|
|
set_property CONFIG.C_NUM_MONITOR_SLOTS {3} [get_bd_cells system_ila_0]
|
||
|
|
endgroup
|
||
|
|
delete_bd_objs [get_bd_intf_nets ccsds122_datamover_0_m_axi_s2mm]
|
||
|
|
set_property location {2 624 311} [get_bd_cells ccsds122_datamover_0]
|
||
|
|
connect_bd_intf_net [get_bd_intf_pins ccsds122_datamover_0/m_axi_s2mm] [get_bd_intf_pins smartconnect_0/S01_AXI]
|
||
|
|
connect_bd_intf_net [get_bd_intf_pins system_ila_0/SLOT_1_AXI] [get_bd_intf_pins ccsds_uart_axi_0/m_axil]
|
||
|
|
delete_bd_objs [get_bd_intf_nets ccsds122_datamover_0_m_axi_mm2s]
|
||
|
|
set_property location {2 681 222} [get_bd_cells ccsds122_datamover_0]
|
||
|
|
connect_bd_intf_net [get_bd_intf_pins ccsds122_datamover_0/m_axi_mm2s] [get_bd_intf_pins smartconnect_0/S00_AXI]
|
||
|
|
connect_bd_intf_net [get_bd_intf_pins system_ila_0/SLOT_0_AXI] [get_bd_intf_pins smartconnect_0/S03_AXI]
|
||
|
|
regenerate_bd_layout
|
||
|
|
validate_bd_design
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x8000_0000 [ 64K ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x8000_0000 [ 64K ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x8000_0000 [ 64K ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S03_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x8000_0000 [ 64K ]> from slave interface '/smartconnect_0/S03_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_1: SmartConnect design_1_smartconnect_0_1 is in High-performance Mode.
|
||
|
|
xit::source_ipfile: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 7491.250 ; gain = 0.340
|
||
|
|
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ddr4_0/C0_DDR4_S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
||
|
|
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ddr4_0/C0_DDR4_S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
||
|
|
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
|
||
|
|
Please check your design and connect them as needed:
|
||
|
|
/ccsds122_axil_slave_0/img_gen_busy
|
||
|
|
/ccsds122_axil_slave_0/img_gen_done
|
||
|
|
|
||
|
|
validate_bd_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 7495.688 ; gain = 10.578
|
||
|
|
startgroup
|
||
|
|
set_property CONFIG.C_NUM_MONITOR_SLOTS {2} [get_bd_cells system_ila_0]
|
||
|
|
endgroup
|
||
|
|
delete_bd_objs [get_bd_intf_nets ccsds_uart_axi_0_m_axi]
|
||
|
|
connect_bd_intf_net [get_bd_intf_pins ccsds_uart_axi_0/m_axi] [get_bd_intf_pins smartconnect_0/S03_AXI]
|
||
|
|
connect_bd_intf_net [get_bd_intf_pins system_ila_0/SLOT_0_AXI] [get_bd_intf_pins smartconnect_0/M01_AXI]
|
||
|
|
regenerate_bd_layout
|
||
|
|
validate_bd_design
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x8000_0000 [ 64K ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x8000_0000 [ 64K ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x8000_0000 [ 64K ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S03_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x8000_0000 [ 64K ]> from slave interface '/smartconnect_0/S03_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_1: SmartConnect design_1_smartconnect_0_1 is in High-performance Mode.
|
||
|
|
xit::source_ipfile: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 7501.410 ; gain = 0.090
|
||
|
|
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ddr4_0/C0_DDR4_S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
||
|
|
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ddr4_0/C0_DDR4_S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
||
|
|
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
|
||
|
|
Please check your design and connect them as needed:
|
||
|
|
/ccsds122_axil_slave_0/img_gen_busy
|
||
|
|
/ccsds122_axil_slave_0/img_gen_done
|
||
|
|
|
||
|
|
validate_bd_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 7501.969 ; gain = 2.324
|
||
|
|
startgroup
|
||
|
|
set_property -dict [list \
|
||
|
|
CONFIG.NUM_MI {1} \
|
||
|
|
CONFIG.NUM_SI {3} \
|
||
|
|
] [get_bd_cells smartconnect_0]
|
||
|
|
delete_bd_objs [get_bd_intf_nets ccsds_uart_axi_0_m_axi]
|
||
|
|
endgroup
|
||
|
|
delete_bd_objs [get_bd_intf_nets Conn]
|
||
|
|
connect_bd_intf_net [get_bd_intf_pins ccsds_uart_axi_0/m_axi] [get_bd_intf_pins smartconnect_0/S02_AXI]
|
||
|
|
connect_bd_intf_net [get_bd_intf_pins ccsds_uart_axi_0/m_axil] [get_bd_intf_pins ccsds122_axil_slave_0/s_axil]
|
||
|
|
connect_bd_intf_net [get_bd_intf_pins system_ila_0/SLOT_1_AXI] [get_bd_intf_pins smartconnect_0/S02_AXI]
|
||
|
|
regenerate_bd_layout
|
||
|
|
validate_bd_design
|
||
|
|
WARNING: [BD 41-2670] Found an incomplete address path from address space '/ccsds122_datamover_0/m_axi_s2mm' to slave segment '/ccsds122_axil_slave_0/s_axil/reg0'. Please either complete or remove this path to resolve.
|
||
|
|
WARNING: [BD 41-2670] Found an incomplete address path from address space '/ccsds122_datamover_0/m_axi_mm2s' to slave segment '/ccsds122_axil_slave_0/s_axil/reg0'. Please either complete or remove this path to resolve.
|
||
|
|
WARNING: [BD 41-2670] Found an incomplete address path from address space '/ccsds_uart_axi_0/m_axi' to slave segment '/ccsds122_axil_slave_0/s_axil/reg0'. Please either complete or remove this path to resolve.
|
||
|
|
WARNING: [BD 41-2670] Found an incomplete address path from address space '/ccsds_uart_axi_0/m_axil' to slave segment '/ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK'. Please either complete or remove this path to resolve.
|
||
|
|
ERROR: [BD 41-1075] Cannot assign slave segment '/ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK' into address space '/ccsds_uart_axi_0/m_axil' at address '0x0000_0000 [ 2G ]'. Master segment '/ccsds_uart_axi_0/m_axil/SEG_ddr4_0_C0_DDR4_ADDRESS_BLOCK' is invalid. The proposed address '0x0000_0000 [ 2G ]' cannot be assigned through an incomplete addressing path.
|
||
|
|
ERROR: [BD 41-1075] Cannot assign slave segment '/ccsds122_axil_slave_0/s_axil/reg0' into address space '/ccsds_uart_axi_0/m_axi' at address '0x8000_0000 [ 64K ]'. Master segment '/ccsds_uart_axi_0/m_axi/SEG_ccsds122_axil_slave_0_reg0' is invalid. The proposed address '0x8000_0000 [ 64K ]' cannot be assigned through an incomplete addressing path.
|
||
|
|
ERROR: [BD 41-1075] Cannot assign slave segment '/ccsds122_axil_slave_0/s_axil/reg0' into address space '/ccsds122_datamover_0/m_axi_mm2s' at address '0x8000_0000 [ 64K ]'. Master segment '/ccsds122_datamover_0/m_axi_mm2s/SEG_ccsds122_axil_slave_0_reg0' is invalid. The proposed address '0x8000_0000 [ 64K ]' cannot be assigned through an incomplete addressing path.
|
||
|
|
ERROR: [BD 41-1075] Cannot assign slave segment '/ccsds122_axil_slave_0/s_axil/reg0' into address space '/ccsds122_datamover_0/m_axi_s2mm' at address '0x8000_0000 [ 64K ]'. Master segment '/ccsds122_datamover_0/m_axi_s2mm/SEG_ccsds122_axil_slave_0_reg0' is invalid. The proposed address '0x8000_0000 [ 64K ]' cannot be assigned through an incomplete addressing path.
|
||
|
|
ERROR: [Common 17-39] 'validate_bd_design' failed due to earlier errors.
|
||
|
|
delete_bd_objs [get_bd_addr_segs ccsds122_datamover_0/m_axi_mm2s/SEG_ccsds122_axil_slave_0_reg0]
|
||
|
|
delete_bd_objs [get_bd_addr_segs ccsds122_datamover_0/m_axi_s2mm/SEG_ccsds122_axil_slave_0_reg0]
|
||
|
|
delete_bd_objs [get_bd_addr_segs ccsds_uart_axi_0/m_axi/SEG_ccsds122_axil_slave_0_reg0]
|
||
|
|
delete_bd_objs [get_bd_addr_segs ccsds_uart_axi_0/m_axil/SEG_ccsds122_axil_slave_0_reg0]
|
||
|
|
delete_bd_objs [get_bd_addr_segs ccsds_uart_axi_0/m_axil/SEG_ddr4_0_C0_DDR4_ADDRESS_BLOCK]
|
||
|
|
assign_bd_address -target_address_space /ccsds_uart_axi_0/m_axil [get_bd_addr_segs ccsds122_axil_slave_0/s_axil/reg0] -force
|
||
|
|
Slave segment '/ccsds122_axil_slave_0/s_axil/reg0' is being assigned into address space '/ccsds_uart_axi_0/m_axil' at <0x0_0000_0000 [ 4G ]>.
|
||
|
|
set_property range 64K [get_bd_addr_segs {ccsds_uart_axi_0/m_axil/SEG_ccsds122_axil_slave_0_reg0}]
|
||
|
|
set_property offset 0x80000000 [get_bd_addr_segs {ccsds_uart_axi_0/m_axil/SEG_ccsds122_axil_slave_0_reg0}]
|
||
|
|
WARNING: [IP_Flow 19-4318] IP-XACT file does not exist: c:/proj/FPGA_DESIGN_IP/ccsds_uart_axi/component.xml. It will be created.
|
||
|
|
update_ip_catalog -rebuild -scan_changes
|
||
|
|
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||
|
|
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/proj/FPGA_DESIGN_IP'.
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
upgrade_ip [get_ips {design_1_ccsds122_axil_slave_0_0 design_1_ccsds_uart_axi_0_0}] -log ip_upgrade.log
|
||
|
|
Upgrading 'C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd'
|
||
|
|
INFO: [IP_Flow 19-3420] Updated design_1_ccsds122_axil_slave_0_0 to use current project options
|
||
|
|
WARNING: [IP_Flow 19-4700] Upgrade has removed port 'img_gen_busy'
|
||
|
|
WARNING: [IP_Flow 19-4700] Upgrade has removed port 'img_gen_done'
|
||
|
|
WARNING: [IP_Flow 19-4700] Upgrade has removed port 'img_gen_start'
|
||
|
|
WARNING: [IP_Flow 19-4700] Upgrade has removed port 'img_rows'
|
||
|
|
WARNING: [IP_Flow 19-4700] Upgrade has removed port 'img_src_sel'
|
||
|
|
WARNING: [IP_Flow 19-4700] Upgrade has removed port 'storage_mode'
|
||
|
|
WARNING: [IP_Flow 19-3298] Detected external port differences while upgrading 'design_1_ccsds122_axil_slave_0_0'. These changes may impact your design.
|
||
|
|
INFO: [IP_Flow 19-3420] Updated design_1_ccsds_uart_axi_0_0 to use current project options
|
||
|
|
CRITICAL WARNING: [Coretcl 2-1279] The upgrade of 'design_1_ccsds122_axil_slave_0_0' has identified issues that may require user intervention. Please review the upgrade log 'c:/proj/xc7v_ccsds122_datamover_uart/ip_upgrade.log', and verify that the upgraded IP is correctly configured.
|
||
|
|
Wrote : <C:\proj\xc7v_ccsds122_datamover_uart\ccsds122_storage.srcs\sources_1\bd\design_1\design_1.bd>
|
||
|
|
Wrote : <C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
|
||
|
|
INFO: [Coretcl 2-1525] Wrote upgrade log to 'C:/proj/xc7v_ccsds122_datamover_uart/ip_upgrade.log'.
|
||
|
|
upgrade_ip: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 7549.078 ; gain = 0.000
|
||
|
|
export_ip_user_files -of_objects [get_ips {design_1_ccsds122_axil_slave_0_0 design_1_ccsds_uart_axi_0_0}] -no_script -sync -force -quiet
|
||
|
|
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_1: SmartConnect design_1_smartconnect_0_1 is in High-performance Mode.
|
||
|
|
xit::source_ipfile: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 7549.078 ; gain = 0.000
|
||
|
|
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ddr4_0/C0_DDR4_S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
||
|
|
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ddr4_0/C0_DDR4_S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
||
|
|
Wrote : <C:\proj\xc7v_ccsds122_datamover_uart\ccsds122_storage.srcs\sources_1\bd\design_1\design_1.bd>
|
||
|
|
Wrote : <C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
|
||
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
|
||
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/sim/design_1.v
|
||
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
|
||
|
|
Wrote : <C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
|
||
|
|
WARNING: [IP_Flow 19-640] IP 'design_1_ccsds122_datamover_0_0' does not support specified targets: Implementation. Running all supported targets by default.
|
||
|
|
WARNING: [IP_Flow 19-640] IP 'design_1_ccsds122_datamover_0_0' does not support specified targets: Implementation. Running all supported targets by default.
|
||
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/hw_handoff/design_1_smartconnect_0_1.hwh
|
||
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/synth/design_1_smartconnect_0_1.hwdef
|
||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block smartconnect_0 .
|
||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block ccsds122_axil_slave_0 .
|
||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block ccsds_uart_axi_0 .
|
||
|
|
INFO: [BD 41-1637] Generated targets are already up-to-date for block design 'bd_45eb' - hence not re-generating.
|
||
|
|
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_ooc.xdc'
|
||
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/hw_handoff/design_1_system_ila_0_0.hwh
|
||
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/synth/design_1_system_ila_0_0.hwdef
|
||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block system_ila_0 .
|
||
|
|
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_ooc.xdc'
|
||
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/hw_handoff/design_1_system_ila_0_1.hwh
|
||
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/synth/design_1_system_ila_0_1.hwdef
|
||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block system_ila_1 .
|
||
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh
|
||
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.hwdef
|
||
|
|
generate_target: Time (s): cpu = 00:00:34 ; elapsed = 00:00:39 . Memory (MB): peak = 7549.078 ; gain = 0.000
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_smartconnect_0_1
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_ccsds122_axil_slave_0_0] }
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds122_axil_slave_0_0
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_ccsds_uart_axi_0_0] }
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds_uart_axi_0_0
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_system_ila_0_0
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_1] }
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_system_ila_0_1
|
||
|
|
INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry 754f7c0da7d9e35f to dir: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/5/754f7c0da7d9e35f/design_1_system_ila_0_1.dcp to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1.dcp.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1.dcp
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/5/754f7c0da7d9e35f/design_1_system_ila_0_1_sim_netlist.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_sim_netlist.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_sim_netlist.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/5/754f7c0da7d9e35f/design_1_system_ila_0_1_sim_netlist.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_sim_netlist.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_sim_netlist.vhdl
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/5/754f7c0da7d9e35f/design_1_system_ila_0_1_stub.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_stub.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_stub.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/5/754f7c0da7d9e35f/design_1_system_ila_0_1_stub.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_stub.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_stub.vhdl
|
||
|
|
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_system_ila_0_1, cache-ID = 754f7c0da7d9e35f; cache size = 5311.521 MB.
|
||
|
|
config_ip_cache: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 7549.078 ; gain = 0.000
|
||
|
|
export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
|
||
|
|
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
launch_runs design_1_ccsds122_axil_slave_0_0_synth_1 design_1_ccsds_uart_axi_0_0_synth_1 design_1_smartconnect_0_1_synth_1 design_1_system_ila_0_0_synth_1 -jobs 24
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds122_axil_slave_0_0
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds_uart_axi_0_0
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_smartconnect_0_1
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_system_ila_0_0
|
||
|
|
[Mon Jul 6 21:28:05 2026] Launched design_1_ccsds122_axil_slave_0_0_synth_1, design_1_ccsds_uart_axi_0_0_synth_1, design_1_smartconnect_0_1_synth_1, design_1_system_ila_0_0_synth_1...
|
||
|
|
Run output will be captured here:
|
||
|
|
design_1_ccsds122_axil_slave_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ccsds122_axil_slave_0_0_synth_1/runme.log
|
||
|
|
design_1_ccsds_uart_axi_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ccsds_uart_axi_0_0_synth_1/runme.log
|
||
|
|
design_1_smartconnect_0_1_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_smartconnect_0_1_synth_1/runme.log
|
||
|
|
design_1_system_ila_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_system_ila_0_0_synth_1/runme.log
|
||
|
|
export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
|
||
|
|
report_ip_status -name ip_status
|
||
|
|
set_property location {3 1249 716} [get_bd_cells smartconnect_0]
|
||
|
|
reset_run synth_1_copy_1
|
||
|
|
INFO: [Project 1-1161] Replacing file C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/utils_1/imports/synth_1/design_1_wrapper.dcp with file C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1_copy_1/design_1_wrapper.dcp
|
||
|
|
WARNING: [Vivado 12-1017] Problems encountered:
|
||
|
|
1. Failed to delete one or more files in run directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1_copy_1
|
||
|
|
|
||
|
|
launch_runs impl_2 -to_step write_bitstream -jobs 24
|
||
|
|
INFO: [IP_Flow 19-6930] IPCACHE: runCacheChecks() number of threads = 8
|
||
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_ccsds122_axil_slave_0_0
|
||
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_ccsds_uart_axi_0_0
|
||
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_smartconnect_0_1
|
||
|
|
INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_1_system_ila_0_0
|
||
|
|
INFO: [IP_Flow 19-8020] IPCACHE: runCacheChecks() calling threadPool finishWork()
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds122_axil_slave_0_0
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_ccsds_uart_axi_0_0
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_smartconnect_0_1
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_system_ila_0_0
|
||
|
|
[Mon Jul 6 21:28:52 2026] Launched design_1_smartconnect_0_1_synth_1, design_1_system_ila_0_0_synth_1, design_1_ccsds122_axil_slave_0_0_synth_1, design_1_ccsds_uart_axi_0_0_synth_1, synth_1_copy_1...
|
||
|
|
Run output will be captured here:
|
||
|
|
design_1_smartconnect_0_1_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_smartconnect_0_1_synth_1/runme.log
|
||
|
|
design_1_system_ila_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_system_ila_0_0_synth_1/runme.log
|
||
|
|
design_1_ccsds122_axil_slave_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ccsds122_axil_slave_0_0_synth_1/runme.log
|
||
|
|
design_1_ccsds_uart_axi_0_0_synth_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_ccsds_uart_axi_0_0_synth_1/runme.log
|
||
|
|
synth_1_copy_1: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1_copy_1/runme.log
|
||
|
|
[Mon Jul 6 21:28:52 2026] Launched impl_2...
|
||
|
|
Run output will be captured here: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/impl_2/runme.log
|
||
|
|
regenerate_bd_layout
|
||
|
|
startgroup
|
||
|
|
set_property CONFIG.C_NUM_MONITOR_SLOTS {1} [get_bd_cells system_ila_0]
|
||
|
|
endgroup
|
||
|
|
validate_bd_design
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S01_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/smartconnect_0/S02_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
|
||
|
|
INFO: [xilinx.com:ip:smartconnect:1.0-1] design_1_smartconnect_0_1: SmartConnect design_1_smartconnect_0_1 is in High-performance Mode.
|
||
|
|
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ddr4_0/C0_DDR4_S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
||
|
|
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ddr4_0/C0_DDR4_S_AXI(0) and /smartconnect_0/M00_AXI(4)
|
||
|
|
validate_bd_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 7549.078 ; gain = 0.000
|
||
|
|
regenerate_bd_layout
|
||
|
|
generate_target all [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
|
||
|
|
INFO: [BD 41-1662] The design 'design_1.bd' is already validated. Therefore parameter propagation will not be re-run.
|
||
|
|
Wrote : <C:\proj\xc7v_ccsds122_datamover_uart\ccsds122_storage.srcs\sources_1\bd\design_1\design_1.bd>
|
||
|
|
Wrote : <C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui>
|
||
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.v
|
||
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/sim/design_1.v
|
||
|
|
Verilog Output written to : c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
|
||
|
|
WARNING: [IP_Flow 19-640] IP 'design_1_ccsds122_datamover_0_0' does not support specified targets: Implementation. Running all supported targets by default.
|
||
|
|
WARNING: [IP_Flow 19-640] IP 'design_1_ccsds122_datamover_0_0' does not support specified targets: Implementation. Running all supported targets by default.
|
||
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/hw_handoff/design_1_smartconnect_0_1.hwh
|
||
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/bd_0/synth/design_1_smartconnect_0_1.hwdef
|
||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block smartconnect_0 .
|
||
|
|
INFO: [BD 41-1637] Generated targets are already up-to-date for block design 'bd_45eb' - hence not re-generating.
|
||
|
|
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_ooc.xdc'
|
||
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/hw_handoff/design_1_system_ila_0_0.hwh
|
||
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/synth/design_1_system_ila_0_0.hwdef
|
||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block system_ila_0 .
|
||
|
|
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_ooc.xdc'
|
||
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/hw_handoff/design_1_system_ila_0_1.hwh
|
||
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/synth/design_1_system_ila_0_1.hwdef
|
||
|
|
INFO: [BD 41-1029] Generation completed for the IP Integrator block system_ila_1 .
|
||
|
|
Exporting to file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh
|
||
|
|
Generated Hardware Definition File c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/synth/design_1.hwdef
|
||
|
|
generate_target: Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 7549.078 ; gain = 0.000
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_smartconnect_0_1] }
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_smartconnect_0_1
|
||
|
|
INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry df7df6e2ec47fd18 to dir: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/d/f/df7df6e2ec47fd18/design_1_smartconnect_0_1.dcp to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1.dcp.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1.dcp
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/d/f/df7df6e2ec47fd18/design_1_smartconnect_0_1_sim_netlist.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/d/f/df7df6e2ec47fd18/design_1_smartconnect_0_1_sim_netlist.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_sim_netlist.vhdl
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/d/f/df7df6e2ec47fd18/design_1_smartconnect_0_1_stub.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/d/f/df7df6e2ec47fd18/design_1_smartconnect_0_1_stub.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_smartconnect_0_1/design_1_smartconnect_0_1_stub.vhdl
|
||
|
|
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_smartconnect_0_1, cache-ID = df7df6e2ec47fd18; cache size = 5374.292 MB.
|
||
|
|
catch { [ delete_ip_run [get_ips -all design_1_smartconnect_0_1] ] }
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_0] }
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_system_ila_0_0
|
||
|
|
catch { config_ip_cache -export [get_ips -all design_1_system_ila_0_1] }
|
||
|
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_system_ila_0_1
|
||
|
|
INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry 754f7c0da7d9e35f to dir: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/5/754f7c0da7d9e35f/design_1_system_ila_0_1.dcp to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1.dcp.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1.dcp
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/5/754f7c0da7d9e35f/design_1_system_ila_0_1_sim_netlist.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_sim_netlist.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_sim_netlist.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/5/754f7c0da7d9e35f/design_1_system_ila_0_1_sim_netlist.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_sim_netlist.vhdl.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_sim_netlist.vhdl
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/5/754f7c0da7d9e35f/design_1_system_ila_0_1_stub.v to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_stub.v.
|
||
|
|
INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_stub.v
|
||
|
|
INFO: [IP_Flow 19-6928] IPCACHE: copied cached file c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/ip/2023.2/7/5/754f7c0da7d9e35f/design_1_system_ila_0_1_stub.vhdl to c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_stub.vhdl.
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INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: c:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1_stub.vhdl
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||
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INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_system_ila_0_1, cache-ID = 754f7c0da7d9e35f; cache size = 5374.292 MB.
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config_ip_cache: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 7549.078 ; gain = 0.000
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export_ip_user_files -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
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||
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create_ip_run [get_files -of_objects [get_fileset sources_1] C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd]
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launch_runs design_1_system_ila_0_0_synth_1 -jobs 24
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INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_system_ila_0_0
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[Mon Jul 6 21:55:28 2026] Launched design_1_system_ila_0_0_synth_1...
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||
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Run output will be captured here: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/design_1_system_ila_0_0_synth_1/runme.log
|
||
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export_simulation -of_objects [get_files C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/sources_1/bd/design_1/design_1.bd] -directory C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/sim_scripts -ip_user_files_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files -ipstatic_source_dir C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/modelsim} {questa=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/questa} {riviera=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/riviera} {activehdl=C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
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||
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reset_run synth_1_copy_1
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||
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INFO: [Project 1-1161] Replacing file C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.srcs/utils_1/imports/synth_1/design_1_wrapper.dcp with file C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1_copy_1/design_1_wrapper.dcp
|
||
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launch_runs impl_2 -to_step write_bitstream -jobs 24
|
||
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[Mon Jul 6 22:00:22 2026] Launched synth_1_copy_1...
|
||
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|
Run output will be captured here: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/synth_1_copy_1/runme.log
|
||
|
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[Mon Jul 6 22:00:22 2026] Launched impl_2...
|
||
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Run output will be captured here: C:/proj/xc7v_ccsds122_datamover_uart/ccsds122_storage.runs/impl_2/runme.log
|
||
|
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CRITICAL WARNING: [Common 17-3551] The parameter 'ipgui.displayPowerEstimation' is obsolete. All references to this parameter should be removed.
|
||
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CRITICAL WARNING: [Common 17-3551] The parameter 'ipgui.displayPowerEstimation' is obsolete. All references to this parameter should be removed.
|
||
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CRITICAL WARNING: [Common 17-3551] The parameter 'ipgui.displayPowerEstimation' is obsolete. All references to this parameter should be removed.
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||
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startgroup
|
||
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set_property CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {None} [get_bd_cells ddr4_0]
|
||
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WARNING: [BD 5-699] No address segments matched 'get_bd_addr_segs -of_object /ilmb_cntlr/SLMB/Mem'
|
||
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WARNING: [BD 5-699] No address segments matched 'get_bd_addr_segs -of_object /second_ilmb_cntlr/SLMB/Mem'
|
||
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WARNING: [BD 5-699] No address segments matched 'get_bd_addr_segs -of_object /dlmb_cntlr/SLMB/Mem'
|
||
|
|
WARNING: [BD 5-699] No address segments matched 'get_bd_addr_segs -of_object /second_dlmb_cntlr/SLMB/Mem'
|
||
|
|
WARNING: [BD 5-699] No address segments matched 'get_bd_addr_segs -of_object /iomodule_0/SLMB/Reg'
|
||
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WARNING: [BD 5-699] No address segments matched 'get_bd_addr_segs -of_object /iomodule_0/SLMB/IO'
|
||
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WARNING: [BD 41-1684] Pin /ddr4_0/addn_ui_clkout1 is now disabled. All connections to this pin have been removed.
|
||
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endgroup
|
||
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startgroup
|
||
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create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0
|
||
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endgroup
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