forked from liuwenbo/simulation_Peripheral
544 lines
19 KiB
C#
544 lines
19 KiB
C#
//
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// UART 外设实现
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// 基于 UART 规格,包含完整的 FIFO、中断和调制解调器控制功能
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//
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using System;
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using System.Collections.Generic;
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using Antmicro.Renode.Core;
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using Antmicro.Renode.Logging;
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using Antmicro.Renode.Peripherals.Bus;
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using Antmicro.Renode.Peripherals.UART;
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using Antmicro.Renode.Utilities;
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using Antmicro.Renode.Time;
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namespace Antmicro.Renode.Peripherals.CustomPeripherals
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{
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/// <summary>
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/// UART_771_RUHW_2CFG 控制器
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/// 接收缓存1024B，发送缓存2048B，时钟24MHz
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/// </summary>
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public class UART_771_RUHW_2CFG4 : IDoubleWordPeripheral, IKnownSize
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{
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private readonly IMachine machine; //TODO
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public UART_771_RUHW_2CFG4(IMachine machine)
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{
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this.clockFrequency = 24000000;
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this.machine = machine; //TODO
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// 创建 FIFO
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rxFifo = new Queue<byte>();
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txFifo = new Queue<byte>();
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// 创建中断线
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IRQ = new GPIO();
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// 初始化寄存器
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DefineRegisters();
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Reset();
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this.Log(LogLevel.Info, "771 UART initialized, clock: {0} Hz", clockFrequency);
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}
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public void Reset()
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{
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rxFifo.Clear();
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txFifo.Clear();
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ucr = 0x00; // 控制寄存器
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usr = USR_TFE; // 状态寄存器
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mcr = 0x00; // 调制控制寄存器：中断使能，接收使能
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brsr = 0; // 波特率设置寄存器
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fsta = (byte)(FSTA_TEMP | FSTA_REMP); // FIFO状态寄存器
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tbr = 0; // 发送FIFO剩余字节数
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rbr = 0; // 接收FIFO剩余字节数
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rstr = 0x00; // 复位/使能寄存器
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RxfifoEnabled = true; //接收fifo使能
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TxfifoEnabled = true; //发送fifo使能
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fifoTriggerLevel = 1;
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IRQ.Set(false);
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UpdateInterrupts();
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this.Log(LogLevel.Info, "UART reset");
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}
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private void DefineRegisters()
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{
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// 寄存器访问通过 ReadDoubleWord/WriteDoubleWord 实现
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}
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// ========================================
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// IBusPeripheral 接口实现
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// ========================================
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public uint ReadDoubleWord(long offset)
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{
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return ReadRegisters(offset);
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}
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public void WriteDoubleWord(long offset, uint value)
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{
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WriteRegisters(offset, value);
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}
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// ========================================
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// 自定义
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// ========================================
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public uint ReadRegisters(long offset)
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{
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uint value = 0;
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switch (offset)
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{
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case (long)Registers.TBR_RBR: //接收FIFO，读操作
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// 在接收FIFO寄存器中读取数据
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value = ReadRBR();
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this.Log(LogLevel.Info, "Read TBR_RBR: 0x{0:X2}", value);
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break;
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case (long)Registers.UCR_USR: //USR状态寄存器
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value = (byte)(usr & 0xFF);
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this.Log(LogLevel.Info, "Read USR: 0x{0:X2}", value);
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// usr = (byte)(usr & (~USR_RBFI)); //usr寄存器，取消接收中断，与hw_uart_isr关联，暂定
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break;
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case (long)Registers.MCR: //MCR调制控制寄存器
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value = (byte)(mcr & 0xFF);
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this.Log(LogLevel.Info, "Read MCR: 0x{0:X2}", value);
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break;
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case (long)Registers.BRSR: //波特率寄存器，暂无读操作
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value = (uint)(brsr);
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this.Log(LogLevel.Info, "Read MCR: 0x{0}", value);
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break;
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case (long)Registers.FSTA: // FIFO状态寄存器
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value = (byte)(fsta & 0xFF);
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this.Log(LogLevel.Info, "Read FSTA: 0x{0:X2}", value);
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//GetTXFIFODataString(); //测试TODO,删除
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break;
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case (long)Registers.TBR_FreeBytes: //发送FIFO剩余字节数
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tbr = (ushort)txFifo.Count;
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value = (uint)tbr;
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this.Log(LogLevel.Info, "Read TBR_FreeBytes: {0}", value);
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break;
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case (long)Registers.RBR_FreeBytes: //接收FIFO剩余字节数
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rbr = (ushort)rxFifo.Count;
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value = (uint)rbr;
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this.Log(LogLevel.Info, "Read RBR_FreeBytes: {0}", value);
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break;
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case (long)Registers.RSTR: // 复位/使能,暂无读操作
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value = (uint)rstr;
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break;
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case (long)Registers.EXTI: //自定义，向外部提供读发送FIFO寄存器
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//value = (uint)GetTXFIFOData();
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break;
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default:
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this.Log(LogLevel.Warning, "Read to unknown offset: 0x{0:X} = 0x{1:X2}", offset, value);
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break;
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}
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return value;
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}
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public void WriteRegisters(long offset, uint value)
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{
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switch (offset)
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{
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case (long)Registers.TBR_RBR:
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WriteTBR((byte)value);
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this.Log(LogLevel.Info, "Write TBR_RBR: 0x{0:X2}", value);
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break;
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case (long)Registers.UCR_USR: //控制寄存器
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ucr = (byte)(value & 0xFF);
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this.Log(LogLevel.Info, "Write UCR_USR: 0x{0:X2}", ucr);
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break;
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case (long)Registers.MCR: //调制控制寄存器
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mcr = (byte)(value & 0xFF);
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this.Log(LogLevel.Info, "Write MCR: 0x{0:X2}", mcr);
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UpdateModemControl();
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break;
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case (long)Registers.BRSR: //波特率寄存器
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if(value != 0)
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{
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currentBaudRate = (uint)(clockFrequency / value);
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brsr = (ushort)value;
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this.Log(LogLevel.Info, "Write BRSR: {0}", brsr);
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}
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break;
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case (long)Registers.RSTR: // 复位/使能
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rstr = (byte)(value & 0xFF);
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this.Log(LogLevel.Info, "Write RSTR: 0x{0:X2}", rstr);
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if ((rstr & 0XFF) == RSTR_RES)
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{
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Reset();
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}
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break;
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case (long)Registers.EXTI: //向外部提供写RXFIFO寄存器
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//WriteRXFIFOData((byte)value);
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break;
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default:
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this.Log(LogLevel.Warning, "Write to unknown offset: 0x{0:X} = 0x{1:X2}", offset, value);
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break;
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}
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}
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private void UpdateInterrupts()
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{
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bool interrupt = false;
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// D2中断使能 必须置位才能产生中断
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if ((mcr & MCR_BEN) != 0)
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{
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// 检查各种中断条件
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if ((usr & USR_TCMP) != 0 ) //发送完成，发送FIFO空（发送中断）
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interrupt = true;
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else if ((usr & USR_RBFI) != 0 ) //接收FIFO中有数据后，延迟10ms产生一次（接收中断）
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interrupt = true;
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else if ((usr & (USR_PE | USR_FE | USR_OE | USR_BI)) != 0 ) //校验错、帧错、溢出错、接收碎片
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interrupt = true;
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}
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IRQ.Set(interrupt);
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if (interrupt)
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{
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this.Log(LogLevel.Info, "Interrupt asserted");
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}
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machine.ScheduleAction(TimeInterval.FromMicroseconds(1),
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_ => {
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IRQ.Set(false);
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this.Log(LogLevel.Info, "Interrupt deasserted");
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});
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}
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private void UpdateModemControl()
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{
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if((mcr & MCR_REN) == 0)
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{
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RxfifoEnabled = false; //待定
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}
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this.Log(LogLevel.Info, "Modem control: MCR_BEN={0}, MCR_REN={1}",
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(mcr & MCR_BEN) != 0, (mcr & MCR_REN) != 0);
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UpdateInterrupts();
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}
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public void WriteTBR(byte value)
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{
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// 从星务接收数据 ，操作txFifo
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this.Log(LogLevel.Info, "Write TBR: 0x{0:X2} ('{1}')", value,
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(value >= 32 && value < 127) ? (char)value : '.');
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if (TxfifoEnabled)
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{
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if (txFifo.Count < TX_FIFO_SIZE)
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{
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txFifo.Enqueue(value);
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fsta = (byte)(fsta & (~FSTA_TEMP)); // 发送缓冲区不为空，D0置0
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usr = (byte)(usr & (~USR_TFE)); //发送FIFO不为空，D6置0
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}
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else
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{
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fsta = (byte)(fsta | FSTA_TFUL); // 发送FIFO满
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this.Log(LogLevel.Warning, "TX FIFO overflow");
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}
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}
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else
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{
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// 非 FIFO 模式，待定
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txFifo.Clear();
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txFifo.Enqueue(value);
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fsta = (byte)(fsta & (~FSTA_TEMP)); // 发送缓冲区不为空，D0置0
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}
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// 暂时不发送数据，由中间层自取
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}
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public uint GetTXFIFOData()
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{
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uint data = 0x00;
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// 从 TX FIFO 发送数据，中间层获取txfifo接口
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if (txFifo.Count > 0)
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{
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data = txFifo.Dequeue();
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// 调用基类的 TransmitCharacter 发送数据
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// TransmitCharacter(data);
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this.Log(LogLevel.Info, "Transmitted: 0x{0:X2} ('{1}')", data,
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(data >= 32 && data < 127) ? (char)data : '.');
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}
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else
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{
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this.Log(LogLevel.Info, "TXFIFO Null ");
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}
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// 更新状态
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if (txFifo.Count == 0)
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{
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fsta = (byte)((fsta &0xF0) | FSTA_TEMP); // 发送缓冲区为空，D0置0
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usr = (byte)(usr | USR_TFE); // 发送FIFO空
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usr = (byte)(usr | USR_TCMP); // 发送完成（发送中断）
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}
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UpdateInterrupts();
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return data;
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}
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public string GetTXFIFODataString()
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{
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string data = "0x";
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byte tmp;
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// 从 TX FIFO 发送数据，中间层获取txfifo接口
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if(txFifo.Count == 0)
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{
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this.Log(LogLevel.Info, "TXFIFO Null");
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return "0x00";
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}
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while (txFifo.Count > 0)
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{
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tmp = txFifo.Dequeue();
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data += tmp.ToString("X2"); // 转换为16进制字符串
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}
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this.Log(LogLevel.Info, "Transmitted: 0x{0}, TXFIFO Null", data);
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// 更新状态
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if (txFifo.Count == 0)
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{
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fsta = (byte)((fsta &0xF0) | FSTA_TEMP); // 发送缓冲区为空，D0置0
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usr = (byte)(usr | USR_TFE); // 发送FIFO空
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usr = (byte)(usr | USR_TCMP); // 发送完成（发送中断）
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}
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UpdateInterrupts();
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return data;
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}
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public byte ReadRBR()
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{
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byte value = 0;
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if (rxFifo.Count > 0)
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{
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value = rxFifo.Dequeue();
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this.Log(LogLevel.Info, "Read: 0x{0:X2} ('{1}')", value,
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(value >= 32 && value < 127) ? (char)value : '.');
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}
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else
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{
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this.Log(LogLevel.Warning, "Read from empty RBR");
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}
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// 更新状态
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if (rxFifo.Count == 0)
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{
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fsta = (byte)(fsta | FSTA_REMP); // 接收FIFO空
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usr = (byte)(usr & (~USR_OE)); // 清除溢出错误
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}
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UpdateInterrupts();
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return value;
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}
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public void WriteRXFIFOData(byte value)
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{
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// 向外部网络提供RXFIFO数据写入功能
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if(RxfifoEnabled)
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{
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if(rxFifo.Count < RX_FIFO_SIZE)
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{
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rxFifo.Enqueue(value);
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fsta = (byte)(fsta & (~FSTA_REMP)); //接收FIFO非空
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this.Log(LogLevel.Info, "External Write RXFIFO: 0x{0:X2} ('{1}')", value,
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(value >= 32 && value < 127) ? (char)value : '.');
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}
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else
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{
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//待定
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fsta = (byte)(fsta | FSTA_RFUL); //接收FIFO满
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this.Log(LogLevel.Warning, "RX FIFO Already Full");
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}
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}
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// this.Wait(TimeInterval.FromMilliseconds(10)); 无法实现等待10ms，暂不实现
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usr = (byte)(usr | USR_RBFI); //usr寄存器，置接收中断
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UpdateInterrupts();
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}
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public void WriteRXFIFODataString(string value)
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{
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// 向外部网络提供RXFIFO数据写入功能，value=0xAABB...
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string data = value.StartsWith("0x",StringComparison.OrdinalIgnoreCase) ? value.Substring(2) : value;
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//this.Log(LogLevel.Info, "External Write RXFIFO: {0} ", value);
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string tmpString;
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byte tmpHex;
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int i;
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if(RxfifoEnabled)
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{
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if(data.Length % 2 != 0)
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{
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data = "0" + data; // 前面补0
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}
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if((data.Length/2) > (RX_FIFO_SIZE - rxFifo.Count)) //value超出fifo剩余
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{
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this.Log(LogLevel.Warning, "Data too long");
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return;
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}
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for(i = 0; i < data.Length ; i+=2)
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{
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tmpString = data.Substring(i, 2);
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tmpHex = Convert.ToByte(tmpString, 16);
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rxFifo.Enqueue(tmpHex);
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}
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fsta = (byte)(fsta & (~FSTA_REMP)); //接收FIFO非空
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if(rxFifo.Count == RX_FIFO_SIZE)
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{
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fsta = (byte)(fsta | FSTA_RFUL); //接收FIFO满
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this.Log(LogLevel.Warning, "RX FIFO Already Full");
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}
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// this.Wait(TimeInterval.FromMilliseconds(10)); 无法实现等待10ms，暂不实现
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machine.ScheduleAction(TimeInterval.FromMicroseconds(10000),
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_ => {
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usr = (byte)(usr | USR_RBFI); //usr寄存器，置接收中断
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UpdateInterrupts();
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});
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}
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else
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{
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}
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}
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public long Size => 0x28; //uart地址长度总空间
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public GPIO IRQ { get; }
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// ========================================
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// 寄存器定义
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// ========================================
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private enum Registers : long
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{
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TBR_RBR = 0x00, // TBR发送FIFO，RBR接收FIFO
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UCR_USR = 0x04, // UCR控制寄存器,USR状态寄存器
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MCR = 0x08, // 调制控制寄存器
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BRSR = 0x0C, // 波特率设置寄存器
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FSTA = 0x10, // FIFO状态寄存器
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TBR_FreeBytes = 0x14, // 发送FIFO剩余字节数
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RBR_FreeBytes = 0x18, // 接收FIFO剩余字节数
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RSTR = 0x20, // 复位/使能 x55复位；其他使能
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EXTI = 0x24 // 向外部提供读写FIFO接口
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}
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// UCR控制寄存器 位定义
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private const byte UCR_STB = 0x01; // 停止位1位
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private const byte UCR_PB = 0x0E; // 奇偶校验3位
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private const byte USR_PE = 0x01; // 校验错
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private const byte USR_FE = 0x02; // 帧错
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private const byte USR_OE = 0x04; // 溢出错
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private const byte USR_BI = 0x08; // 接收碎片
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private const byte USR_TCMP = 0x20; // 发送完成（发送中断）
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private const byte USR_TFE = 0x40; // 发送FIFO空
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private const byte USR_RBFI = 0x80; // 接收中断
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// MCR 调制控制寄存器
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private const byte MCR_BEN = 0x04; // 中断使能
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private const byte MCR_REN = 0x20; // 接收使能
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// FSTA FIFO状态寄存器
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||
private const byte FSTA_TEMP = 0x01; // 发送FIFO空
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||
private const byte FSTA_TLHF= 0x02; // 发送FIFO低阈值半满
|
||
private const byte FSTA_TFUL = 0x04; // 发送FIFO满
|
||
private const byte FSTA_THHF = 0x08; // 发送FIFO高阈值半满
|
||
private const byte FSTA_REMP = 0x10; // 接收FIFO空
|
||
private const byte FSTA_RLHF = 0x20; // 接收FIFO低阈值半满
|
||
private const byte FSTA_RFUL = 0x40; // 接收FIFO满
|
||
private const byte FSTA_RHHF = 0x80; // 接收FIFO 高阈值半满
|
||
|
||
|
||
// RSTR 复位/使能寄存器
|
||
private const byte RSTR_RES = 0x55; // 复位
|
||
private const byte RSTR_EN = 0xAA; // 使能
|
||
|
||
// 常量
|
||
private const int RX_FIFO_SIZE = 1024; // 接收FIFO_SIZE
|
||
private const int TX_FIFO_SIZE = 2048; // 发送FIFO_SIZE
|
||
|
||
// ========================================
|
||
// 私有字段
|
||
// ========================================
|
||
|
||
private readonly uint clockFrequency;
|
||
private uint currentBaudRate;
|
||
|
||
|
||
// 寄存器
|
||
private byte ucr; // 控制寄存器
|
||
private byte usr; // 状态寄存器
|
||
private byte mcr; // 调制控制寄存器
|
||
private ushort brsr; // 波特率设置寄存器
|
||
private byte fsta; // FIFO状态寄存器
|
||
private ushort tbr; // 发送FIFO剩余字节数
|
||
private ushort rbr; // 接收FIFO剩余字节数
|
||
private byte rstr; // 复位/使能寄存器
|
||
|
||
|
||
// FIFO
|
||
private readonly Queue<byte> rxFifo;
|
||
private readonly Queue<byte> txFifo;
|
||
private bool RxfifoEnabled;
|
||
private bool TxfifoEnabled;
|
||
private int fifoTriggerLevel;
|
||
}
|
||
}
|