Source compile order for 'synthesis' with fileset 'sources_1' in source management mode 'All': Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name ----- ------------------------ ----------- --------- -------------- ----------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 1 async_fifo_tx.dcp Synth DCP xil_defaultlib d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx/async_fifo_tx.dcp 2 async_fifo_rx.dcp Synth DCP xil_defaultlib d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx/async_fifo_rx.dcp 3 floating_multi.dcp Synth DCP xil_defaultlib d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/floating_multi.dcp 4 floating_float.dcp Synth DCP xil_defaultlib d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/floating_float.dcp 5 floating_fixed.dcp Synth DCP xil_defaultlib d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/floating_fixed.dcp 6 floating_add.dcp Synth DCP xil_defaultlib d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/floating_add.dcp 7 async_fifo_tx_SPI.dcp Synth DCP xil_defaultlib d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx_SPI/async_fifo_tx_SPI.dcp 8 async_fifo_rx_SPI.dcp Synth DCP xil_defaultlib d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx_SPI/async_fifo_rx_SPI.dcp 9 clk_dis1.dcp Synth DCP xil_defaultlib d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis1/clk_dis1.dcp 10 clk_dis.dcp Synth DCP xil_defaultlib d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis/clk_dis.dcp 11 uart_tx.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/LBC_UART/uart_tx.v 12 uart_rx.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/LBC_UART/uart_rx.v 13 uart_tx_top.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/LBC_UART/uart_tx_top.v 14 uart_rx_top.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/LBC_UART/uart_rx_top.v 15 uart_intr_ctrl.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/LBC_UART/uart_intr_ctrl.v 16 ABI_Recognition.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/ABI_Recognition.v 17 ABI_Process2.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/ABI_Process2.v 18 ABI_Process1.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/ABI_Process1.v 19 uart_regfile.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/LBC_UART/uart_regfile.v 20 RS422_RXTX.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/imports/new/RS422_RXTX.v 21 SSI_Zero_Pos.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/SSI_Zero_Pos.v 22 SSI_Transfer.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/SSI_Transfer.v 23 SSI_Speed_Estimate.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/SSI_Speed_Estimate.v 24 SSI_RST.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/SSI_RST.v 25 SSI_Collection.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/SSI_Collection.v 26 SPIxIF.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/LBC_SPI/SPIxIF.v 27 RS422_RXTX2.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/imports/new/RS422_RXTX2.v 28 L297.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/L297.v 29 FSM_CMD1.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/imports/new/FSM_CMD1.v 30 FSM_CMD.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/imports/new/FSM_CMD.v 31 ABDecoder.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/ABDecoder.v 32 Temperature_Collection.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/Temperature_Collection.v 33 spi_regfile.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/LBC_SPI/spi_regfile.v 34 UART_LBC.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/LBC_UART/UART_LBC.v 35 Time_Caculation.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/new/Time_Caculation.v 36 SSI_Model.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/SSI_Model.v 37 SSI_Guangshan_Transfer.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/new/SSI_Guangshan_Transfer.v 38 SPI_TOP.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/LBC_SPI/SPI_TOP.v 39 sja1000t.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/sja1000t.v 40 pwm_module.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/pwm_module.v 41 L297_Model.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/L297_Model.v 42 FT2000_HW_CFG_NEW2.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/FT2000_HW_CFG_NEW2.v 43 FSM_model2.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/new/FSM_model2.v 44 FSM_model.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/imports/new/FSM_model.v 45 ABI_Model.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/ABI_Model.v 46 Temperature_Model.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/Temperature_Model.v 47 TOP.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/new/TOP.v Source compile order for 'simulation' with fileset 'sim_1' in source management mode 'All' and simulation language 'Mixed': Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name ----- ------------ ----------- --------- -------------- ----------- ---------------------------------------------------------------------------------------------------------------------------------------------------- 1 FSM_CMD.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/imports/new/FSM_CMD.v 2 tb_FSM_CMD.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sim_1/new/tb_FSM_CMD.v Constraint evaluation order for 'synthesis' with fileset 'sources_1' & with fileset 'constrs_1': Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name ----- --------------- ------------ ------------- --------------- ---------------- -------------- -------------------------------------------------------------------------------------------------------------------------------------------------- 1 FT2000A2_K7.xdc Synth & Impl NORMAL D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/constrs_1/new/FT2000A2_K7.xdc Constraint evaluation order for 'implementation' with fileset 'sources_1' & with fileset 'constrs_1': Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name ----- ------------------------ ------------ ----------------- --------------- ---------------- -------------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 1 async_fifo_tx.xdc Synth & Impl async_fifo_tx U0 EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx/async_fifo_tx/async_fifo_tx.xdc 2 async_fifo_rx.xdc Synth & Impl async_fifo_rx U0 EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx/async_fifo_rx/async_fifo_rx.xdc 3 clk_dis_board.xdc Synth & Impl clk_dis inst EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis/clk_dis_board.xdc 4 clk_dis.xdc Synth & Impl clk_dis inst EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis/clk_dis.xdc 5 async_fifo_tx_SPI.xdc Synth & Impl async_fifo_tx_SPI U0 EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx_SPI/async_fifo_tx_SPI/async_fifo_tx_SPI.xdc 6 async_fifo_rx_SPI.xdc Synth & Impl async_fifo_rx_SPI U0 EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx_SPI/async_fifo_rx_SPI/async_fifo_rx_SPI.xdc 7 clk_dis1_board.xdc Synth & Impl clk_dis1 inst EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis1/clk_dis1_board.xdc 8 clk_dis1.xdc Synth & Impl clk_dis1 inst EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis1/clk_dis1.xdc 9 FT2000A2_K7.xdc Synth & Impl NORMAL D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/constrs_1/new/FT2000A2_K7.xdc 10 async_fifo_tx_clocks.xdc Synth & Impl async_fifo_tx U0 LATE d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx/async_fifo_tx/async_fifo_tx_clocks.xdc 11 async_fifo_rx_clocks.xdc Synth & Impl async_fifo_rx U0 LATE d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx/async_fifo_rx/async_fifo_rx_clocks.xdc Missing instances for 'synthesis' with fileset 'sources_1': Index Instance Path File Path Line ----- ------------- --------- ---- < empty > Missing instances for 'simulation' with fileset 'sim_1': Index Instance Path File Path Line ----- ------------- --------- ---- < empty > ---------------------------------------------------------- | Compile Order for Out-of-Context BlockSet: 'async_fifo_tx' | Top Module: 'async_fifo_tx' ---------------------------------------------------------- Source compile order for 'synthesis' with fileset 'async_fifo_tx' in source management mode 'All': Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name ----- ---------------------------------- ------- --------- ---------------------- ----------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 1 blk_mem_gen_v8_3_vhsyn_rfs.vhd Synth VHDL blk_mem_gen_v8_3_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx/blk_mem_gen_v8_3_1/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd 2 blk_mem_gen_v8_3.vhd Synth VHDL blk_mem_gen_v8_3_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx/blk_mem_gen_v8_3_1/hdl/blk_mem_gen_v8_3.vhd 3 fifo_generator_v13_0_vhsyn_rfs.vhd Synth VHDL fifo_generator_v13_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx/fifo_generator_v13_0_1/hdl/fifo_generator_v13_0_vhsyn_rfs.vhd 4 fifo_generator_v13_0.vhd Synth VHDL fifo_generator_v13_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx/fifo_generator_v13_0_1/hdl/fifo_generator_v13_0.vhd 5 async_fifo_tx.vhd Synth VHDL xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx/synth/async_fifo_tx.vhd Source compile order for 'simulation' with fileset 'async_fifo_tx' in source management mode 'All' and simulation language 'Mixed': Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name ----- ---------------------------- ------- --------- ---------------------- ----------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 1 fifo_generator_vhdl_beh.vhd Sim VHDL fifo_generator_v13_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx/fifo_generator_v13_0_1/simulation/fifo_generator_vhdl_beh.vhd 2 fifo_generator_v13_0_rfs.vhd Sim VHDL fifo_generator_v13_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx/fifo_generator_v13_0_1/hdl/fifo_generator_v13_0_rfs.vhd 3 async_fifo_tx.vhd Sim VHDL xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx/sim/async_fifo_tx.vhd Constraint evaluation order for 'synthesis' with fileset 'async_fifo_tx': Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name ----- ------------------------ ------------ ------------- --------------- ---------------- -------------- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 1 async_fifo_tx_ooc.xdc Synth & Impl async_fifo_tx U0 EARLY yes d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx/async_fifo_tx_ooc.xdc 2 async_fifo_tx.xdc Synth & Impl async_fifo_tx U0 EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx/async_fifo_tx/async_fifo_tx.xdc 3 async_fifo_tx_clocks.xdc Synth & Impl async_fifo_tx U0 LATE d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx/async_fifo_tx/async_fifo_tx_clocks.xdc Constraint evaluation order for 'implementation' with fileset 'async_fifo_tx': Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name ----- ------------------------ ------------ ------------- --------------- ---------------- -------------- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 1 async_fifo_tx_ooc.xdc Synth & Impl async_fifo_tx U0 EARLY yes d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx/async_fifo_tx_ooc.xdc 2 async_fifo_tx.xdc Synth & Impl async_fifo_tx U0 EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx/async_fifo_tx/async_fifo_tx.xdc 3 async_fifo_tx_clocks.xdc Synth & Impl async_fifo_tx U0 LATE d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx/async_fifo_tx/async_fifo_tx_clocks.xdc ---------------------------------------------------------- | Compile Order for Out-of-Context BlockSet: 'async_fifo_rx' | Top Module: 'async_fifo_rx' ---------------------------------------------------------- Source compile order for 'synthesis' with fileset 'async_fifo_rx' in source management mode 'All': Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name ----- ---------------------------------- ------- --------- ---------------------- ----------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 1 blk_mem_gen_v8_3_vhsyn_rfs.vhd Synth VHDL blk_mem_gen_v8_3_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx/blk_mem_gen_v8_3_1/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd 2 blk_mem_gen_v8_3.vhd Synth VHDL blk_mem_gen_v8_3_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx/blk_mem_gen_v8_3_1/hdl/blk_mem_gen_v8_3.vhd 3 fifo_generator_v13_0_vhsyn_rfs.vhd Synth VHDL fifo_generator_v13_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx/fifo_generator_v13_0_1/hdl/fifo_generator_v13_0_vhsyn_rfs.vhd 4 fifo_generator_v13_0.vhd Synth VHDL fifo_generator_v13_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx/fifo_generator_v13_0_1/hdl/fifo_generator_v13_0.vhd 5 async_fifo_rx.vhd Synth VHDL xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx/synth/async_fifo_rx.vhd Source compile order for 'simulation' with fileset 'async_fifo_rx' in source management mode 'All' and simulation language 'Mixed': Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name ----- ---------------------------- ------- --------- ---------------------- ----------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 1 fifo_generator_vhdl_beh.vhd Sim VHDL fifo_generator_v13_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx/fifo_generator_v13_0_1/simulation/fifo_generator_vhdl_beh.vhd 2 fifo_generator_v13_0_rfs.vhd Sim VHDL fifo_generator_v13_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx/fifo_generator_v13_0_1/hdl/fifo_generator_v13_0_rfs.vhd 3 async_fifo_rx.vhd Sim VHDL xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx/sim/async_fifo_rx.vhd Constraint evaluation order for 'synthesis' with fileset 'async_fifo_rx': Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name ----- ------------------------ ------------ ------------- --------------- ---------------- -------------- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 1 async_fifo_rx_ooc.xdc Synth & Impl async_fifo_rx U0 EARLY yes d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx/async_fifo_rx_ooc.xdc 2 async_fifo_rx.xdc Synth & Impl async_fifo_rx U0 EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx/async_fifo_rx/async_fifo_rx.xdc 3 async_fifo_rx_clocks.xdc Synth & Impl async_fifo_rx U0 LATE d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx/async_fifo_rx/async_fifo_rx_clocks.xdc Constraint evaluation order for 'implementation' with fileset 'async_fifo_rx': Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name ----- ------------------------ ------------ ------------- --------------- ---------------- -------------- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 1 async_fifo_rx_ooc.xdc Synth & Impl async_fifo_rx U0 EARLY yes d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx/async_fifo_rx_ooc.xdc 2 async_fifo_rx.xdc Synth & Impl async_fifo_rx U0 EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx/async_fifo_rx/async_fifo_rx.xdc 3 async_fifo_rx_clocks.xdc Synth & Impl async_fifo_rx U0 LATE d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx/async_fifo_rx/async_fifo_rx_clocks.xdc ---------------------------------------------------------- | Compile Order for Out-of-Context BlockSet: 'clk_dis' | Top Module: 'clk_dis' ---------------------------------------------------------- Source compile order for 'synthesis' with fileset 'clk_dis' in source management mode 'All': Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name ----- ----------------- ----------- --------- -------------- ----------- ----------------------------------------------------------------------------------------------------------------------------------------------------------- 1 clk_dis_clk_wiz.v Synth & Sim Verilog xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis/clk_dis_clk_wiz.v 2 clk_dis.v Synth & Sim Verilog xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis/clk_dis.v Source compile order for 'simulation' with fileset 'clk_dis' in source management mode 'All' and simulation language 'Mixed': Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name ----- ----------------- ----------- --------- -------------- ----------- ----------------------------------------------------------------------------------------------------------------------------------------------------------- 1 clk_dis_clk_wiz.v Synth & Sim Verilog xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis/clk_dis_clk_wiz.v 2 clk_dis.v Synth & Sim Verilog xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis/clk_dis.v Constraint evaluation order for 'synthesis' with fileset 'clk_dis': Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name ----- ----------------- ------------ ------------- --------------- ---------------- -------------- ----------------------------------------------------------------------------------------------------------------------------------------------------------- 1 clk_dis_ooc.xdc Synth & Impl clk_dis inst EARLY yes d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis/clk_dis_ooc.xdc 2 clk_dis_board.xdc Synth & Impl clk_dis inst EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis/clk_dis_board.xdc 3 clk_dis.xdc Synth & Impl clk_dis inst EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis/clk_dis.xdc Constraint evaluation order for 'implementation' with fileset 'clk_dis': Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name ----- ----------------- ------------ ------------- --------------- ---------------- -------------- ----------------------------------------------------------------------------------------------------------------------------------------------------------- 1 clk_dis_ooc.xdc Synth & Impl clk_dis inst EARLY yes d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis/clk_dis_ooc.xdc 2 clk_dis_board.xdc Synth & Impl clk_dis inst EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis/clk_dis_board.xdc 3 clk_dis.xdc Synth & Impl clk_dis inst EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis/clk_dis.xdc ---------------------------------------------------------- | Compile Order for Out-of-Context BlockSet: 'async_fifo_tx_SPI' | Top Module: 'async_fifo_tx_SPI' ---------------------------------------------------------- Source compile order for 'synthesis' with fileset 'async_fifo_tx_SPI' in source management mode 'All': Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name ----- ---------------------------------- ------- --------- ---------------------- ----------- ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 1 blk_mem_gen_v8_3_vhsyn_rfs.vhd Synth VHDL blk_mem_gen_v8_3_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx_SPI/blk_mem_gen_v8_3_1/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd 2 blk_mem_gen_v8_3.vhd Synth VHDL blk_mem_gen_v8_3_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx_SPI/blk_mem_gen_v8_3_1/hdl/blk_mem_gen_v8_3.vhd 3 fifo_generator_v13_0_vhsyn_rfs.vhd Synth VHDL fifo_generator_v13_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx_SPI/fifo_generator_v13_0_1/hdl/fifo_generator_v13_0_vhsyn_rfs.vhd 4 fifo_generator_v13_0.vhd Synth VHDL fifo_generator_v13_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx_SPI/fifo_generator_v13_0_1/hdl/fifo_generator_v13_0.vhd 5 async_fifo_tx_SPI.vhd Synth VHDL xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx_SPI/synth/async_fifo_tx_SPI.vhd Source compile order for 'simulation' with fileset 'async_fifo_tx_SPI' in source management mode 'All' and simulation language 'Mixed': Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name ----- ---------------------------- ------- --------- ---------------------- ----------- ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 1 fifo_generator_vhdl_beh.vhd Sim VHDL fifo_generator_v13_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx_SPI/fifo_generator_v13_0_1/simulation/fifo_generator_vhdl_beh.vhd 2 fifo_generator_v13_0_rfs.vhd Sim VHDL fifo_generator_v13_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx_SPI/fifo_generator_v13_0_1/hdl/fifo_generator_v13_0_rfs.vhd 3 async_fifo_tx_SPI.vhd Sim VHDL xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx_SPI/sim/async_fifo_tx_SPI.vhd Constraint evaluation order for 'synthesis' with fileset 'async_fifo_tx_SPI': Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name ----- ------------------------- ------------ ----------------- --------------- ---------------- -------------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 1 async_fifo_tx_SPI_ooc.xdc Synth & Impl async_fifo_tx_SPI U0 EARLY yes d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx_SPI/async_fifo_tx_SPI_ooc.xdc 2 async_fifo_tx_SPI.xdc Synth & Impl async_fifo_tx_SPI U0 EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx_SPI/async_fifo_tx_SPI/async_fifo_tx_SPI.xdc Constraint evaluation order for 'implementation' with fileset 'async_fifo_tx_SPI': Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name ----- ------------------------- ------------ ----------------- --------------- ---------------- -------------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 1 async_fifo_tx_SPI_ooc.xdc Synth & Impl async_fifo_tx_SPI U0 EARLY yes d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx_SPI/async_fifo_tx_SPI_ooc.xdc 2 async_fifo_tx_SPI.xdc Synth & Impl async_fifo_tx_SPI U0 EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx_SPI/async_fifo_tx_SPI/async_fifo_tx_SPI.xdc ---------------------------------------------------------- | Compile Order for Out-of-Context BlockSet: 'async_fifo_rx_SPI' | Top Module: 'async_fifo_rx_SPI' ---------------------------------------------------------- Source compile order for 'synthesis' with fileset 'async_fifo_rx_SPI' in source management mode 'All': Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name ----- ---------------------------------- ------- --------- ---------------------- ----------- ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 1 blk_mem_gen_v8_3_vhsyn_rfs.vhd Synth VHDL blk_mem_gen_v8_3_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx_SPI/blk_mem_gen_v8_3_1/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd 2 blk_mem_gen_v8_3.vhd Synth VHDL blk_mem_gen_v8_3_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx_SPI/blk_mem_gen_v8_3_1/hdl/blk_mem_gen_v8_3.vhd 3 fifo_generator_v13_0_vhsyn_rfs.vhd Synth VHDL fifo_generator_v13_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx_SPI/fifo_generator_v13_0_1/hdl/fifo_generator_v13_0_vhsyn_rfs.vhd 4 fifo_generator_v13_0.vhd Synth VHDL fifo_generator_v13_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx_SPI/fifo_generator_v13_0_1/hdl/fifo_generator_v13_0.vhd 5 async_fifo_rx_SPI.vhd Synth VHDL xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx_SPI/synth/async_fifo_rx_SPI.vhd Source compile order for 'simulation' with fileset 'async_fifo_rx_SPI' in source management mode 'All' and simulation language 'Mixed': Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name ----- ---------------------------- ------- --------- ---------------------- ----------- ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 1 fifo_generator_vhdl_beh.vhd Sim VHDL fifo_generator_v13_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx_SPI/fifo_generator_v13_0_1/simulation/fifo_generator_vhdl_beh.vhd 2 fifo_generator_v13_0_rfs.vhd Sim VHDL fifo_generator_v13_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx_SPI/fifo_generator_v13_0_1/hdl/fifo_generator_v13_0_rfs.vhd 3 async_fifo_rx_SPI.vhd Sim VHDL xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx_SPI/sim/async_fifo_rx_SPI.vhd Constraint evaluation order for 'synthesis' with fileset 'async_fifo_rx_SPI': Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name ----- ------------------------- ------------ ----------------- --------------- ---------------- -------------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 1 async_fifo_rx_SPI_ooc.xdc Synth & Impl async_fifo_rx_SPI U0 EARLY yes d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx_SPI/async_fifo_rx_SPI_ooc.xdc 2 async_fifo_rx_SPI.xdc Synth & Impl async_fifo_rx_SPI U0 EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx_SPI/async_fifo_rx_SPI/async_fifo_rx_SPI.xdc Constraint evaluation order for 'implementation' with fileset 'async_fifo_rx_SPI': Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name ----- ------------------------- ------------ ----------------- --------------- ---------------- -------------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 1 async_fifo_rx_SPI_ooc.xdc Synth & Impl async_fifo_rx_SPI U0 EARLY yes d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx_SPI/async_fifo_rx_SPI_ooc.xdc 2 async_fifo_rx_SPI.xdc Synth & Impl async_fifo_rx_SPI U0 EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx_SPI/async_fifo_rx_SPI/async_fifo_rx_SPI.xdc ---------------------------------------------------------- | Compile Order for Out-of-Context BlockSet: 'clk_dis1' | Top Module: 'clk_dis1' ---------------------------------------------------------- Source compile order for 'synthesis' with fileset 'clk_dis1' in source management mode 'All': Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name ----- ------------------ ----------- --------- -------------- ----------- ------------------------------------------------------------------------------------------------------------------------------------------------------------- 1 clk_dis1_clk_wiz.v Synth & Sim Verilog xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis1/clk_dis1_clk_wiz.v 2 clk_dis1.v Synth & Sim Verilog xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis1/clk_dis1.v Source compile order for 'simulation' with fileset 'clk_dis1' in source management mode 'All' and simulation language 'Mixed': Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name ----- ------------------ ----------- --------- -------------- ----------- ------------------------------------------------------------------------------------------------------------------------------------------------------------- 1 clk_dis1_clk_wiz.v Synth & Sim Verilog xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis1/clk_dis1_clk_wiz.v 2 clk_dis1.v Synth & Sim Verilog xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis1/clk_dis1.v Constraint evaluation order for 'synthesis' with fileset 'clk_dis1': Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name ----- ------------------ ------------ ------------- --------------- ---------------- -------------- ------------------------------------------------------------------------------------------------------------------------------------------------------------- 1 clk_dis1_ooc.xdc Synth & Impl clk_dis1 inst EARLY yes d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis1/clk_dis1_ooc.xdc 2 clk_dis1_board.xdc Synth & Impl clk_dis1 inst EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis1/clk_dis1_board.xdc 3 clk_dis1.xdc Synth & Impl clk_dis1 inst EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis1/clk_dis1.xdc Constraint evaluation order for 'implementation' with fileset 'clk_dis1': Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name ----- ------------------ ------------ ------------- --------------- ---------------- -------------- ------------------------------------------------------------------------------------------------------------------------------------------------------------- 1 clk_dis1_ooc.xdc Synth & Impl clk_dis1 inst EARLY yes d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis1/clk_dis1_ooc.xdc 2 clk_dis1_board.xdc Synth & Impl clk_dis1 inst EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis1/clk_dis1_board.xdc 3 clk_dis1.xdc Synth & Impl clk_dis1 inst EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis1/clk_dis1.xdc ---------------------------------------------------------- | Compile Order for Out-of-Context BlockSet: 'floating_multi' | Top Module: 'floating_multi' ---------------------------------------------------------- Source compile order for 'synthesis' with fileset 'floating_multi' in source management mode 'All': Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name ----- ---------------------------------- ----------- --------- ------------------------- ----------- ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 1 xbip_utils_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_utils_v3_0_5 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/xbip_utils_v3_0_5/hdl/xbip_utils_v3_0_vh_rfs.vhd 2 axi_utils_v2_0_vh_rfs.vhd Synth & Sim VHDL axi_utils_v2_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/axi_utils_v2_0_1/hdl/axi_utils_v2_0_vh_rfs.vhd 3 xbip_pipe_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_pipe_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0_vh_rfs.vhd 4 xbip_pipe_v3_0.vhd Synth & Sim VHDL xbip_pipe_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0.vhd 5 xbip_dsp48_wrapper_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_wrapper_v3_0_4 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/xbip_dsp48_wrapper_v3_0_4/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd 6 xbip_dsp48_addsub_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_addsub_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/xbip_dsp48_addsub_v3_0_1/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd 7 xbip_dsp48_addsub_v3_0.vhd Synth & Sim VHDL xbip_dsp48_addsub_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/xbip_dsp48_addsub_v3_0_1/hdl/xbip_dsp48_addsub_v3_0.vhd 8 xbip_dsp48_multadd_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_multadd_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd 9 xbip_dsp48_multadd_v3_0.vhd Synth & Sim VHDL xbip_dsp48_multadd_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0.vhd 10 xbip_bram18k_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_bram18k_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/xbip_bram18k_v3_0_1/hdl/xbip_bram18k_v3_0_vh_rfs.vhd 11 xbip_bram18k_v3_0.vhd Synth & Sim VHDL xbip_bram18k_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/xbip_bram18k_v3_0_1/hdl/xbip_bram18k_v3_0.vhd 12 mult_gen_v12_0_vh_rfs.vhd Synth & Sim VHDL mult_gen_v12_0_10 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/mult_gen_v12_0_10/hdl/mult_gen_v12_0_vh_rfs.vhd 13 mult_gen_v12_0.vhd Synth & Sim VHDL mult_gen_v12_0_10 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/mult_gen_v12_0_10/hdl/mult_gen_v12_0.vhd 14 floating_point_v7_1_vh_rfs.vhd Synth & Sim VHDL floating_point_v7_1_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/floating_point_v7_1_1/hdl/floating_point_v7_1_vh_rfs.vhd 15 floating_multi.vhd Synth VHDL xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/synth/floating_multi.vhd Source compile order for 'simulation' with fileset 'floating_multi' in source management mode 'All' and simulation language 'Mixed': Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name ----- ---------------------------------- ----------- --------- ------------------------- ----------- ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 1 xbip_utils_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_utils_v3_0_5 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/xbip_utils_v3_0_5/hdl/xbip_utils_v3_0_vh_rfs.vhd 2 axi_utils_v2_0_vh_rfs.vhd Synth & Sim VHDL axi_utils_v2_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/axi_utils_v2_0_1/hdl/axi_utils_v2_0_vh_rfs.vhd 3 xbip_pipe_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_pipe_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0_vh_rfs.vhd 4 xbip_pipe_v3_0.vhd Synth & Sim VHDL xbip_pipe_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0.vhd 5 xbip_dsp48_wrapper_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_wrapper_v3_0_4 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/xbip_dsp48_wrapper_v3_0_4/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd 6 xbip_dsp48_addsub_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_addsub_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/xbip_dsp48_addsub_v3_0_1/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd 7 xbip_dsp48_addsub_v3_0.vhd Synth & Sim VHDL xbip_dsp48_addsub_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/xbip_dsp48_addsub_v3_0_1/hdl/xbip_dsp48_addsub_v3_0.vhd 8 xbip_dsp48_multadd_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_multadd_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd 9 xbip_dsp48_multadd_v3_0.vhd Synth & Sim VHDL xbip_dsp48_multadd_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0.vhd 10 xbip_bram18k_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_bram18k_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/xbip_bram18k_v3_0_1/hdl/xbip_bram18k_v3_0_vh_rfs.vhd 11 xbip_bram18k_v3_0.vhd Synth & Sim VHDL xbip_bram18k_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/xbip_bram18k_v3_0_1/hdl/xbip_bram18k_v3_0.vhd 12 mult_gen_v12_0_vh_rfs.vhd Synth & Sim VHDL mult_gen_v12_0_10 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/mult_gen_v12_0_10/hdl/mult_gen_v12_0_vh_rfs.vhd 13 mult_gen_v12_0.vhd Synth & Sim VHDL mult_gen_v12_0_10 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/mult_gen_v12_0_10/hdl/mult_gen_v12_0.vhd 14 floating_point_v7_1_vh_rfs.vhd Synth & Sim VHDL floating_point_v7_1_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/floating_point_v7_1_1/hdl/floating_point_v7_1_vh_rfs.vhd 15 floating_multi.vhd Sim VHDL xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/sim/floating_multi.vhd Constraint evaluation order for 'synthesis' with fileset 'floating_multi': Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name ----- ---------------------- ------------ -------------- --------------- ---------------- -------------- ----------------------------------------------------------------------------------------------------------------------------------------------------------------------- 1 floating_multi_ooc.xdc Synth & Impl floating_multi U0 EARLY yes d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/floating_multi_ooc.xdc Constraint evaluation order for 'implementation' with fileset 'floating_multi': Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name ----- ---------------------- ------------ -------------- --------------- ---------------- -------------- ----------------------------------------------------------------------------------------------------------------------------------------------------------------------- 1 floating_multi_ooc.xdc Synth & Impl floating_multi U0 EARLY yes d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/floating_multi_ooc.xdc ---------------------------------------------------------- | Compile Order for Out-of-Context BlockSet: 'floating_add' | Top Module: 'floating_add' ---------------------------------------------------------- Source compile order for 'synthesis' with fileset 'floating_add' in source management mode 'All': Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name ----- ---------------------------------- ----------- --------- ------------------------- ----------- --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 1 xbip_utils_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_utils_v3_0_5 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/xbip_utils_v3_0_5/hdl/xbip_utils_v3_0_vh_rfs.vhd 2 axi_utils_v2_0_vh_rfs.vhd Synth & Sim VHDL axi_utils_v2_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/axi_utils_v2_0_1/hdl/axi_utils_v2_0_vh_rfs.vhd 3 xbip_pipe_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_pipe_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0_vh_rfs.vhd 4 xbip_pipe_v3_0.vhd Synth & Sim VHDL xbip_pipe_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0.vhd 5 xbip_dsp48_wrapper_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_wrapper_v3_0_4 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/xbip_dsp48_wrapper_v3_0_4/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd 6 xbip_dsp48_addsub_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_addsub_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/xbip_dsp48_addsub_v3_0_1/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd 7 xbip_dsp48_addsub_v3_0.vhd Synth & Sim VHDL xbip_dsp48_addsub_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/xbip_dsp48_addsub_v3_0_1/hdl/xbip_dsp48_addsub_v3_0.vhd 8 xbip_dsp48_multadd_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_multadd_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd 9 xbip_dsp48_multadd_v3_0.vhd Synth & Sim VHDL xbip_dsp48_multadd_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0.vhd 10 xbip_bram18k_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_bram18k_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/xbip_bram18k_v3_0_1/hdl/xbip_bram18k_v3_0_vh_rfs.vhd 11 xbip_bram18k_v3_0.vhd Synth & Sim VHDL xbip_bram18k_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/xbip_bram18k_v3_0_1/hdl/xbip_bram18k_v3_0.vhd 12 mult_gen_v12_0_vh_rfs.vhd Synth & Sim VHDL mult_gen_v12_0_10 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/mult_gen_v12_0_10/hdl/mult_gen_v12_0_vh_rfs.vhd 13 mult_gen_v12_0.vhd Synth & Sim VHDL mult_gen_v12_0_10 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/mult_gen_v12_0_10/hdl/mult_gen_v12_0.vhd 14 floating_point_v7_1_vh_rfs.vhd Synth & Sim VHDL floating_point_v7_1_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/floating_point_v7_1_1/hdl/floating_point_v7_1_vh_rfs.vhd 15 floating_add.vhd Synth VHDL xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/synth/floating_add.vhd Source compile order for 'simulation' with fileset 'floating_add' in source management mode 'All' and simulation language 'Mixed': Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name ----- ---------------------------------- ----------- --------- ------------------------- ----------- --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 1 xbip_utils_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_utils_v3_0_5 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/xbip_utils_v3_0_5/hdl/xbip_utils_v3_0_vh_rfs.vhd 2 axi_utils_v2_0_vh_rfs.vhd Synth & Sim VHDL axi_utils_v2_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/axi_utils_v2_0_1/hdl/axi_utils_v2_0_vh_rfs.vhd 3 xbip_pipe_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_pipe_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0_vh_rfs.vhd 4 xbip_pipe_v3_0.vhd Synth & Sim VHDL xbip_pipe_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0.vhd 5 xbip_dsp48_wrapper_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_wrapper_v3_0_4 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/xbip_dsp48_wrapper_v3_0_4/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd 6 xbip_dsp48_addsub_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_addsub_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/xbip_dsp48_addsub_v3_0_1/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd 7 xbip_dsp48_addsub_v3_0.vhd Synth & Sim VHDL xbip_dsp48_addsub_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/xbip_dsp48_addsub_v3_0_1/hdl/xbip_dsp48_addsub_v3_0.vhd 8 xbip_dsp48_multadd_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_multadd_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd 9 xbip_dsp48_multadd_v3_0.vhd Synth & Sim VHDL xbip_dsp48_multadd_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0.vhd 10 xbip_bram18k_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_bram18k_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/xbip_bram18k_v3_0_1/hdl/xbip_bram18k_v3_0_vh_rfs.vhd 11 xbip_bram18k_v3_0.vhd Synth & Sim VHDL xbip_bram18k_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/xbip_bram18k_v3_0_1/hdl/xbip_bram18k_v3_0.vhd 12 mult_gen_v12_0_vh_rfs.vhd Synth & Sim VHDL mult_gen_v12_0_10 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/mult_gen_v12_0_10/hdl/mult_gen_v12_0_vh_rfs.vhd 13 mult_gen_v12_0.vhd Synth & Sim VHDL mult_gen_v12_0_10 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/mult_gen_v12_0_10/hdl/mult_gen_v12_0.vhd 14 floating_point_v7_1_vh_rfs.vhd Synth & Sim VHDL floating_point_v7_1_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/floating_point_v7_1_1/hdl/floating_point_v7_1_vh_rfs.vhd 15 floating_add.vhd Sim VHDL xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/sim/floating_add.vhd Constraint evaluation order for 'synthesis' with fileset 'floating_add': Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name ----- -------------------- ------------ ------------- --------------- ---------------- -------------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------- 1 floating_add_ooc.xdc Synth & Impl floating_add U0 EARLY yes d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/floating_add_ooc.xdc Constraint evaluation order for 'implementation' with fileset 'floating_add': Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name ----- -------------------- ------------ ------------- --------------- ---------------- -------------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------- 1 floating_add_ooc.xdc Synth & Impl floating_add U0 EARLY yes d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/floating_add_ooc.xdc ---------------------------------------------------------- | Compile Order for Out-of-Context BlockSet: 'floating_float' | Top Module: 'floating_float' ---------------------------------------------------------- Source compile order for 'synthesis' with fileset 'floating_float' in source management mode 'All': Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name ----- ---------------------------------- ----------- --------- ------------------------- ----------- ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 1 xbip_utils_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_utils_v3_0_5 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/xbip_utils_v3_0_5/hdl/xbip_utils_v3_0_vh_rfs.vhd 2 axi_utils_v2_0_vh_rfs.vhd Synth & Sim VHDL axi_utils_v2_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/axi_utils_v2_0_1/hdl/axi_utils_v2_0_vh_rfs.vhd 3 xbip_pipe_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_pipe_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0_vh_rfs.vhd 4 xbip_pipe_v3_0.vhd Synth & Sim VHDL xbip_pipe_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0.vhd 5 xbip_dsp48_wrapper_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_wrapper_v3_0_4 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/xbip_dsp48_wrapper_v3_0_4/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd 6 xbip_dsp48_addsub_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_addsub_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/xbip_dsp48_addsub_v3_0_1/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd 7 xbip_dsp48_addsub_v3_0.vhd Synth & Sim VHDL xbip_dsp48_addsub_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/xbip_dsp48_addsub_v3_0_1/hdl/xbip_dsp48_addsub_v3_0.vhd 8 xbip_dsp48_multadd_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_multadd_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd 9 xbip_dsp48_multadd_v3_0.vhd Synth & Sim VHDL xbip_dsp48_multadd_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0.vhd 10 xbip_bram18k_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_bram18k_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/xbip_bram18k_v3_0_1/hdl/xbip_bram18k_v3_0_vh_rfs.vhd 11 xbip_bram18k_v3_0.vhd Synth & Sim VHDL xbip_bram18k_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/xbip_bram18k_v3_0_1/hdl/xbip_bram18k_v3_0.vhd 12 mult_gen_v12_0_vh_rfs.vhd Synth & Sim VHDL mult_gen_v12_0_10 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/mult_gen_v12_0_10/hdl/mult_gen_v12_0_vh_rfs.vhd 13 mult_gen_v12_0.vhd Synth & Sim VHDL mult_gen_v12_0_10 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/mult_gen_v12_0_10/hdl/mult_gen_v12_0.vhd 14 floating_point_v7_1_vh_rfs.vhd Synth & Sim VHDL floating_point_v7_1_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/floating_point_v7_1_1/hdl/floating_point_v7_1_vh_rfs.vhd 15 floating_float.vhd Synth VHDL xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/synth/floating_float.vhd Source compile order for 'simulation' with fileset 'floating_float' in source management mode 'All' and simulation language 'Mixed': Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name ----- ---------------------------------- ----------- --------- ------------------------- ----------- ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 1 xbip_utils_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_utils_v3_0_5 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/xbip_utils_v3_0_5/hdl/xbip_utils_v3_0_vh_rfs.vhd 2 axi_utils_v2_0_vh_rfs.vhd Synth & Sim VHDL axi_utils_v2_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/axi_utils_v2_0_1/hdl/axi_utils_v2_0_vh_rfs.vhd 3 xbip_pipe_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_pipe_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0_vh_rfs.vhd 4 xbip_pipe_v3_0.vhd Synth & Sim VHDL xbip_pipe_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0.vhd 5 xbip_dsp48_wrapper_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_wrapper_v3_0_4 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/xbip_dsp48_wrapper_v3_0_4/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd 6 xbip_dsp48_addsub_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_addsub_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/xbip_dsp48_addsub_v3_0_1/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd 7 xbip_dsp48_addsub_v3_0.vhd Synth & Sim VHDL xbip_dsp48_addsub_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/xbip_dsp48_addsub_v3_0_1/hdl/xbip_dsp48_addsub_v3_0.vhd 8 xbip_dsp48_multadd_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_multadd_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd 9 xbip_dsp48_multadd_v3_0.vhd Synth & Sim VHDL xbip_dsp48_multadd_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0.vhd 10 xbip_bram18k_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_bram18k_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/xbip_bram18k_v3_0_1/hdl/xbip_bram18k_v3_0_vh_rfs.vhd 11 xbip_bram18k_v3_0.vhd Synth & Sim VHDL xbip_bram18k_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/xbip_bram18k_v3_0_1/hdl/xbip_bram18k_v3_0.vhd 12 mult_gen_v12_0_vh_rfs.vhd Synth & Sim VHDL mult_gen_v12_0_10 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/mult_gen_v12_0_10/hdl/mult_gen_v12_0_vh_rfs.vhd 13 mult_gen_v12_0.vhd Synth & Sim VHDL mult_gen_v12_0_10 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/mult_gen_v12_0_10/hdl/mult_gen_v12_0.vhd 14 floating_point_v7_1_vh_rfs.vhd Synth & Sim VHDL floating_point_v7_1_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/floating_point_v7_1_1/hdl/floating_point_v7_1_vh_rfs.vhd 15 floating_float.vhd Sim VHDL xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/sim/floating_float.vhd Constraint evaluation order for 'synthesis' with fileset 'floating_float': Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name ----- ---------------------- ------------ -------------- --------------- ---------------- -------------- ----------------------------------------------------------------------------------------------------------------------------------------------------------------------- 1 floating_float_ooc.xdc Synth & Impl floating_float U0 EARLY yes d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/floating_float_ooc.xdc Constraint evaluation order for 'implementation' with fileset 'floating_float': Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name ----- ---------------------- ------------ -------------- --------------- ---------------- -------------- ----------------------------------------------------------------------------------------------------------------------------------------------------------------------- 1 floating_float_ooc.xdc Synth & Impl floating_float U0 EARLY yes d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/floating_float_ooc.xdc ---------------------------------------------------------- | Compile Order for Out-of-Context BlockSet: 'floating_fixed' | Top Module: 'floating_fixed' ---------------------------------------------------------- Source compile order for 'synthesis' with fileset 'floating_fixed' in source management mode 'All': Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name ----- ---------------------------------- ----------- --------- ------------------------- ----------- ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 1 xbip_utils_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_utils_v3_0_5 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/xbip_utils_v3_0_5/hdl/xbip_utils_v3_0_vh_rfs.vhd 2 axi_utils_v2_0_vh_rfs.vhd Synth & Sim VHDL axi_utils_v2_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/axi_utils_v2_0_1/hdl/axi_utils_v2_0_vh_rfs.vhd 3 xbip_pipe_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_pipe_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0_vh_rfs.vhd 4 xbip_pipe_v3_0.vhd Synth & Sim VHDL xbip_pipe_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0.vhd 5 xbip_dsp48_wrapper_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_wrapper_v3_0_4 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/xbip_dsp48_wrapper_v3_0_4/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd 6 xbip_dsp48_addsub_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_addsub_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/xbip_dsp48_addsub_v3_0_1/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd 7 xbip_dsp48_addsub_v3_0.vhd Synth & Sim VHDL xbip_dsp48_addsub_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/xbip_dsp48_addsub_v3_0_1/hdl/xbip_dsp48_addsub_v3_0.vhd 8 xbip_dsp48_multadd_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_multadd_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd 9 xbip_dsp48_multadd_v3_0.vhd Synth & Sim VHDL xbip_dsp48_multadd_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0.vhd 10 xbip_bram18k_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_bram18k_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/xbip_bram18k_v3_0_1/hdl/xbip_bram18k_v3_0_vh_rfs.vhd 11 xbip_bram18k_v3_0.vhd Synth & Sim VHDL xbip_bram18k_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/xbip_bram18k_v3_0_1/hdl/xbip_bram18k_v3_0.vhd 12 mult_gen_v12_0_vh_rfs.vhd Synth & Sim VHDL mult_gen_v12_0_10 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/mult_gen_v12_0_10/hdl/mult_gen_v12_0_vh_rfs.vhd 13 mult_gen_v12_0.vhd Synth & Sim VHDL mult_gen_v12_0_10 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/mult_gen_v12_0_10/hdl/mult_gen_v12_0.vhd 14 floating_point_v7_1_vh_rfs.vhd Synth & Sim VHDL floating_point_v7_1_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/floating_point_v7_1_1/hdl/floating_point_v7_1_vh_rfs.vhd 15 floating_fixed.vhd Synth VHDL xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/synth/floating_fixed.vhd Source compile order for 'simulation' with fileset 'floating_fixed' in source management mode 'All' and simulation language 'Mixed': Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name ----- ---------------------------------- ----------- --------- ------------------------- ----------- ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 1 xbip_utils_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_utils_v3_0_5 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/xbip_utils_v3_0_5/hdl/xbip_utils_v3_0_vh_rfs.vhd 2 axi_utils_v2_0_vh_rfs.vhd Synth & Sim VHDL axi_utils_v2_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/axi_utils_v2_0_1/hdl/axi_utils_v2_0_vh_rfs.vhd 3 xbip_pipe_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_pipe_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0_vh_rfs.vhd 4 xbip_pipe_v3_0.vhd Synth & Sim VHDL xbip_pipe_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0.vhd 5 xbip_dsp48_wrapper_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_wrapper_v3_0_4 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/xbip_dsp48_wrapper_v3_0_4/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd 6 xbip_dsp48_addsub_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_addsub_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/xbip_dsp48_addsub_v3_0_1/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd 7 xbip_dsp48_addsub_v3_0.vhd Synth & Sim VHDL xbip_dsp48_addsub_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/xbip_dsp48_addsub_v3_0_1/hdl/xbip_dsp48_addsub_v3_0.vhd 8 xbip_dsp48_multadd_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_multadd_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd 9 xbip_dsp48_multadd_v3_0.vhd Synth & Sim VHDL xbip_dsp48_multadd_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0.vhd 10 xbip_bram18k_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_bram18k_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/xbip_bram18k_v3_0_1/hdl/xbip_bram18k_v3_0_vh_rfs.vhd 11 xbip_bram18k_v3_0.vhd Synth & Sim VHDL xbip_bram18k_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/xbip_bram18k_v3_0_1/hdl/xbip_bram18k_v3_0.vhd 12 mult_gen_v12_0_vh_rfs.vhd Synth & Sim VHDL mult_gen_v12_0_10 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/mult_gen_v12_0_10/hdl/mult_gen_v12_0_vh_rfs.vhd 13 mult_gen_v12_0.vhd Synth & Sim VHDL mult_gen_v12_0_10 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/mult_gen_v12_0_10/hdl/mult_gen_v12_0.vhd 14 floating_point_v7_1_vh_rfs.vhd Synth & Sim VHDL floating_point_v7_1_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/floating_point_v7_1_1/hdl/floating_point_v7_1_vh_rfs.vhd 15 floating_fixed.vhd Sim VHDL xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/sim/floating_fixed.vhd Constraint evaluation order for 'synthesis' with fileset 'floating_fixed': Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name ----- ---------------------- ------------ -------------- --------------- ---------------- -------------- ----------------------------------------------------------------------------------------------------------------------------------------------------------------------- 1 floating_fixed_ooc.xdc Synth & Impl floating_fixed U0 EARLY yes d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/floating_fixed_ooc.xdc Constraint evaluation order for 'implementation' with fileset 'floating_fixed': Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name ----- ---------------------- ------------ -------------- --------------- ---------------- -------------- ----------------------------------------------------------------------------------------------------------------------------------------------------------------------- 1 floating_fixed_ooc.xdc Synth & Impl floating_fixed U0 EARLY yes d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/floating_fixed_ooc.xdc