commit b8b4ea895d02fe501f8c94b8b8a1a40fe9a1a175 Author: lihansani Date: Mon Jul 13 17:55:17 2026 +0800 first commit diff --git a/txt解析版/config.txt b/txt解析版/config.txt new file mode 100644 index 0000000..4f206eb --- /dev/null +++ b/txt解析版/config.txt @@ -0,0 +1,6 @@ +# 支持的文件类型（不区分大小写） +# 每行一个后缀 +.v +.vhd +.vh +.vhdl \ No newline at end of file diff --git a/txt解析版/txt版/Copy_Files_20251219_17.txt b/txt解析版/txt版/Copy_Files_20251219_17.txt new file mode 100644 index 0000000..e767ead --- /dev/null +++ b/txt解析版/txt版/Copy_Files_20251219_17.txt @@ -0,0 +1,543 @@ +Source compile order for 'synthesis' with fileset 'sources_1' in source management mode 'All': +Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name +----- ------------------------ ----------- --------- -------------- ----------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +1 async_fifo_tx.dcp Synth DCP xil_defaultlib d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx/async_fifo_tx.dcp +2 async_fifo_rx.dcp Synth DCP xil_defaultlib d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx/async_fifo_rx.dcp +3 floating_multi.dcp Synth DCP xil_defaultlib d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/floating_multi.dcp +4 floating_float.dcp Synth DCP xil_defaultlib d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/floating_float.dcp +5 floating_fixed.dcp Synth DCP xil_defaultlib d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/floating_fixed.dcp +6 floating_add.dcp Synth DCP xil_defaultlib d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/floating_add.dcp +7 async_fifo_tx_SPI.dcp Synth DCP xil_defaultlib d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx_SPI/async_fifo_tx_SPI.dcp +8 async_fifo_rx_SPI.dcp Synth DCP xil_defaultlib d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx_SPI/async_fifo_rx_SPI.dcp +9 clk_dis1.dcp Synth DCP xil_defaultlib d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis1/clk_dis1.dcp +10 clk_dis.dcp Synth DCP xil_defaultlib d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis/clk_dis.dcp +11 uart_tx.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/LBC_UART/uart_tx.v +12 uart_rx.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/LBC_UART/uart_rx.v +13 uart_tx_top.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/LBC_UART/uart_tx_top.v +14 uart_rx_top.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/LBC_UART/uart_rx_top.v +15 uart_intr_ctrl.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/LBC_UART/uart_intr_ctrl.v +16 ABI_Recognition.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/ABI_Recognition.v +17 ABI_Process2.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/ABI_Process2.v +18 ABI_Process1.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/ABI_Process1.v +19 uart_regfile.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/LBC_UART/uart_regfile.v +20 RS422_RXTX.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/imports/new/RS422_RXTX.v +21 SSI_Zero_Pos.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/SSI_Zero_Pos.v +22 SSI_Transfer.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/SSI_Transfer.v +23 SSI_Speed_Estimate.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/SSI_Speed_Estimate.v +24 SSI_RST.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/SSI_RST.v +25 SSI_Collection.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/SSI_Collection.v +26 SPIxIF.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/LBC_SPI/SPIxIF.v +27 RS422_RXTX2.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/imports/new/RS422_RXTX2.v +28 L297.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/L297.v +29 FSM_CMD1.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/imports/new/FSM_CMD1.v +30 FSM_CMD.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/imports/new/FSM_CMD.v +31 ABDecoder.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/ABDecoder.v +32 Temperature_Collection.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/Temperature_Collection.v +33 spi_regfile.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/LBC_SPI/spi_regfile.v +34 UART_LBC.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/LBC_UART/UART_LBC.v +35 Time_Caculation.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/new/Time_Caculation.v +36 SSI_Model.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/SSI_Model.v +37 SSI_Guangshan_Transfer.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/new/SSI_Guangshan_Transfer.v +38 SPI_TOP.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/LBC_SPI/SPI_TOP.v +39 sja1000t.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/sja1000t.v +40 pwm_module.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/pwm_module.v +41 L297_Model.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/L297_Model.v +42 FT2000_HW_CFG_NEW2.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/FT2000_HW_CFG_NEW2.v +43 FSM_model2.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/new/FSM_model2.v +44 FSM_model.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/imports/new/FSM_model.v +45 ABI_Model.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/ABI_Model.v +46 Temperature_Model.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/logic_ip/Temperature_Model.v +47 TOP.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/new/TOP.v + + +Source compile order for 'simulation' with fileset 'sim_1' in source management mode 'All' and simulation language 'Mixed': +Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name +----- ------------ ----------- --------- -------------- ----------- ---------------------------------------------------------------------------------------------------------------------------------------------------- +1 FSM_CMD.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/imports/new/FSM_CMD.v +2 tb_FSM_CMD.v Synth & Sim Verilog xil_defaultlib No D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sim_1/new/tb_FSM_CMD.v + + +Constraint evaluation order for 'synthesis' with fileset 'sources_1' & with fileset 'constrs_1': +Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name +----- --------------- ------------ ------------- --------------- ---------------- -------------- -------------------------------------------------------------------------------------------------------------------------------------------------- +1 FT2000A2_K7.xdc Synth & Impl NORMAL D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/constrs_1/new/FT2000A2_K7.xdc + + +Constraint evaluation order for 'implementation' with fileset 'sources_1' & with fileset 'constrs_1': +Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name +----- ------------------------ ------------ ----------------- --------------- ---------------- -------------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +1 async_fifo_tx.xdc Synth & Impl async_fifo_tx U0 EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx/async_fifo_tx/async_fifo_tx.xdc +2 async_fifo_rx.xdc Synth & Impl async_fifo_rx U0 EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx/async_fifo_rx/async_fifo_rx.xdc +3 clk_dis_board.xdc Synth & Impl clk_dis inst EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis/clk_dis_board.xdc +4 clk_dis.xdc Synth & Impl clk_dis inst EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis/clk_dis.xdc +5 async_fifo_tx_SPI.xdc Synth & Impl async_fifo_tx_SPI U0 EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx_SPI/async_fifo_tx_SPI/async_fifo_tx_SPI.xdc +6 async_fifo_rx_SPI.xdc Synth & Impl async_fifo_rx_SPI U0 EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx_SPI/async_fifo_rx_SPI/async_fifo_rx_SPI.xdc +7 clk_dis1_board.xdc Synth & Impl clk_dis1 inst EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis1/clk_dis1_board.xdc +8 clk_dis1.xdc Synth & Impl clk_dis1 inst EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis1/clk_dis1.xdc +9 FT2000A2_K7.xdc Synth & Impl NORMAL D:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/constrs_1/new/FT2000A2_K7.xdc +10 async_fifo_tx_clocks.xdc Synth & Impl async_fifo_tx U0 LATE d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx/async_fifo_tx/async_fifo_tx_clocks.xdc +11 async_fifo_rx_clocks.xdc Synth & Impl async_fifo_rx U0 LATE d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx/async_fifo_rx/async_fifo_rx_clocks.xdc + + +Missing instances for 'synthesis' with fileset 'sources_1': +Index Instance Path File Path Line +----- ------------- --------- ---- +< empty > + + +Missing instances for 'simulation' with fileset 'sim_1': +Index Instance Path File Path Line +----- ------------- --------- ---- +< empty > + + +---------------------------------------------------------- +| Compile Order for Out-of-Context BlockSet: 'async_fifo_tx' +| Top Module: 'async_fifo_tx' +---------------------------------------------------------- + +Source compile order for 'synthesis' with fileset 'async_fifo_tx' in source management mode 'All': +Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name +----- ---------------------------------- ------- --------- ---------------------- ----------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +1 blk_mem_gen_v8_3_vhsyn_rfs.vhd Synth VHDL blk_mem_gen_v8_3_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx/blk_mem_gen_v8_3_1/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd +2 blk_mem_gen_v8_3.vhd Synth VHDL blk_mem_gen_v8_3_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx/blk_mem_gen_v8_3_1/hdl/blk_mem_gen_v8_3.vhd +3 fifo_generator_v13_0_vhsyn_rfs.vhd Synth VHDL fifo_generator_v13_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx/fifo_generator_v13_0_1/hdl/fifo_generator_v13_0_vhsyn_rfs.vhd +4 fifo_generator_v13_0.vhd Synth VHDL fifo_generator_v13_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx/fifo_generator_v13_0_1/hdl/fifo_generator_v13_0.vhd +5 async_fifo_tx.vhd Synth VHDL xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx/synth/async_fifo_tx.vhd + + +Source compile order for 'simulation' with fileset 'async_fifo_tx' in source management mode 'All' and simulation language 'Mixed': +Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name +----- ---------------------------- ------- --------- ---------------------- ----------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +1 fifo_generator_vhdl_beh.vhd Sim VHDL fifo_generator_v13_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx/fifo_generator_v13_0_1/simulation/fifo_generator_vhdl_beh.vhd +2 fifo_generator_v13_0_rfs.vhd Sim VHDL fifo_generator_v13_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx/fifo_generator_v13_0_1/hdl/fifo_generator_v13_0_rfs.vhd +3 async_fifo_tx.vhd Sim VHDL xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx/sim/async_fifo_tx.vhd + + +Constraint evaluation order for 'synthesis' with fileset 'async_fifo_tx': +Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name +----- ------------------------ ------------ ------------- --------------- ---------------- -------------- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +1 async_fifo_tx_ooc.xdc Synth & Impl async_fifo_tx U0 EARLY yes d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx/async_fifo_tx_ooc.xdc +2 async_fifo_tx.xdc Synth & Impl async_fifo_tx U0 EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx/async_fifo_tx/async_fifo_tx.xdc +3 async_fifo_tx_clocks.xdc Synth & Impl async_fifo_tx U0 LATE d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx/async_fifo_tx/async_fifo_tx_clocks.xdc + + +Constraint evaluation order for 'implementation' with fileset 'async_fifo_tx': +Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name +----- ------------------------ ------------ ------------- --------------- ---------------- -------------- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +1 async_fifo_tx_ooc.xdc Synth & Impl async_fifo_tx U0 EARLY yes d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx/async_fifo_tx_ooc.xdc +2 async_fifo_tx.xdc Synth & Impl async_fifo_tx U0 EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx/async_fifo_tx/async_fifo_tx.xdc +3 async_fifo_tx_clocks.xdc Synth & Impl async_fifo_tx U0 LATE d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx/async_fifo_tx/async_fifo_tx_clocks.xdc + + +---------------------------------------------------------- +| Compile Order for Out-of-Context BlockSet: 'async_fifo_rx' +| Top Module: 'async_fifo_rx' +---------------------------------------------------------- + +Source compile order for 'synthesis' with fileset 'async_fifo_rx' in source management mode 'All': +Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name +----- ---------------------------------- ------- --------- ---------------------- ----------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +1 blk_mem_gen_v8_3_vhsyn_rfs.vhd Synth VHDL blk_mem_gen_v8_3_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx/blk_mem_gen_v8_3_1/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd +2 blk_mem_gen_v8_3.vhd Synth VHDL blk_mem_gen_v8_3_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx/blk_mem_gen_v8_3_1/hdl/blk_mem_gen_v8_3.vhd +3 fifo_generator_v13_0_vhsyn_rfs.vhd Synth VHDL fifo_generator_v13_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx/fifo_generator_v13_0_1/hdl/fifo_generator_v13_0_vhsyn_rfs.vhd +4 fifo_generator_v13_0.vhd Synth VHDL fifo_generator_v13_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx/fifo_generator_v13_0_1/hdl/fifo_generator_v13_0.vhd +5 async_fifo_rx.vhd Synth VHDL xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx/synth/async_fifo_rx.vhd + + +Source compile order for 'simulation' with fileset 'async_fifo_rx' in source management mode 'All' and simulation language 'Mixed': +Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name +----- ---------------------------- ------- --------- ---------------------- ----------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +1 fifo_generator_vhdl_beh.vhd Sim VHDL fifo_generator_v13_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx/fifo_generator_v13_0_1/simulation/fifo_generator_vhdl_beh.vhd +2 fifo_generator_v13_0_rfs.vhd Sim VHDL fifo_generator_v13_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx/fifo_generator_v13_0_1/hdl/fifo_generator_v13_0_rfs.vhd +3 async_fifo_rx.vhd Sim VHDL xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx/sim/async_fifo_rx.vhd + + +Constraint evaluation order for 'synthesis' with fileset 'async_fifo_rx': +Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name +----- ------------------------ ------------ ------------- --------------- ---------------- -------------- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +1 async_fifo_rx_ooc.xdc Synth & Impl async_fifo_rx U0 EARLY yes d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx/async_fifo_rx_ooc.xdc +2 async_fifo_rx.xdc Synth & Impl async_fifo_rx U0 EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx/async_fifo_rx/async_fifo_rx.xdc +3 async_fifo_rx_clocks.xdc Synth & Impl async_fifo_rx U0 LATE d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx/async_fifo_rx/async_fifo_rx_clocks.xdc + + +Constraint evaluation order for 'implementation' with fileset 'async_fifo_rx': +Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name +----- ------------------------ ------------ ------------- --------------- ---------------- -------------- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +1 async_fifo_rx_ooc.xdc Synth & Impl async_fifo_rx U0 EARLY yes d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx/async_fifo_rx_ooc.xdc +2 async_fifo_rx.xdc Synth & Impl async_fifo_rx U0 EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx/async_fifo_rx/async_fifo_rx.xdc +3 async_fifo_rx_clocks.xdc Synth & Impl async_fifo_rx U0 LATE d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx/async_fifo_rx/async_fifo_rx_clocks.xdc + + +---------------------------------------------------------- +| Compile Order for Out-of-Context BlockSet: 'clk_dis' +| Top Module: 'clk_dis' +---------------------------------------------------------- + +Source compile order for 'synthesis' with fileset 'clk_dis' in source management mode 'All': +Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name +----- ----------------- ----------- --------- -------------- ----------- ----------------------------------------------------------------------------------------------------------------------------------------------------------- +1 clk_dis_clk_wiz.v Synth & Sim Verilog xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis/clk_dis_clk_wiz.v +2 clk_dis.v Synth & Sim Verilog xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis/clk_dis.v + + +Source compile order for 'simulation' with fileset 'clk_dis' in source management mode 'All' and simulation language 'Mixed': +Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name +----- ----------------- ----------- --------- -------------- ----------- ----------------------------------------------------------------------------------------------------------------------------------------------------------- +1 clk_dis_clk_wiz.v Synth & Sim Verilog xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis/clk_dis_clk_wiz.v +2 clk_dis.v Synth & Sim Verilog xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis/clk_dis.v + + +Constraint evaluation order for 'synthesis' with fileset 'clk_dis': +Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name +----- ----------------- ------------ ------------- --------------- ---------------- -------------- ----------------------------------------------------------------------------------------------------------------------------------------------------------- +1 clk_dis_ooc.xdc Synth & Impl clk_dis inst EARLY yes d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis/clk_dis_ooc.xdc +2 clk_dis_board.xdc Synth & Impl clk_dis inst EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis/clk_dis_board.xdc +3 clk_dis.xdc Synth & Impl clk_dis inst EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis/clk_dis.xdc + + +Constraint evaluation order for 'implementation' with fileset 'clk_dis': +Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name +----- ----------------- ------------ ------------- --------------- ---------------- -------------- ----------------------------------------------------------------------------------------------------------------------------------------------------------- +1 clk_dis_ooc.xdc Synth & Impl clk_dis inst EARLY yes d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis/clk_dis_ooc.xdc +2 clk_dis_board.xdc Synth & Impl clk_dis inst EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis/clk_dis_board.xdc +3 clk_dis.xdc Synth & Impl clk_dis inst EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis/clk_dis.xdc + + +---------------------------------------------------------- +| Compile Order for Out-of-Context BlockSet: 'async_fifo_tx_SPI' +| Top Module: 'async_fifo_tx_SPI' +---------------------------------------------------------- + +Source compile order for 'synthesis' with fileset 'async_fifo_tx_SPI' in source management mode 'All': +Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name +----- ---------------------------------- ------- --------- ---------------------- ----------- ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +1 blk_mem_gen_v8_3_vhsyn_rfs.vhd Synth VHDL blk_mem_gen_v8_3_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx_SPI/blk_mem_gen_v8_3_1/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd +2 blk_mem_gen_v8_3.vhd Synth VHDL blk_mem_gen_v8_3_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx_SPI/blk_mem_gen_v8_3_1/hdl/blk_mem_gen_v8_3.vhd +3 fifo_generator_v13_0_vhsyn_rfs.vhd Synth VHDL fifo_generator_v13_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx_SPI/fifo_generator_v13_0_1/hdl/fifo_generator_v13_0_vhsyn_rfs.vhd +4 fifo_generator_v13_0.vhd Synth VHDL fifo_generator_v13_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx_SPI/fifo_generator_v13_0_1/hdl/fifo_generator_v13_0.vhd +5 async_fifo_tx_SPI.vhd Synth VHDL xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx_SPI/synth/async_fifo_tx_SPI.vhd + + +Source compile order for 'simulation' with fileset 'async_fifo_tx_SPI' in source management mode 'All' and simulation language 'Mixed': +Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name +----- ---------------------------- ------- --------- ---------------------- ----------- ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +1 fifo_generator_vhdl_beh.vhd Sim VHDL fifo_generator_v13_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx_SPI/fifo_generator_v13_0_1/simulation/fifo_generator_vhdl_beh.vhd +2 fifo_generator_v13_0_rfs.vhd Sim VHDL fifo_generator_v13_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx_SPI/fifo_generator_v13_0_1/hdl/fifo_generator_v13_0_rfs.vhd +3 async_fifo_tx_SPI.vhd Sim VHDL xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx_SPI/sim/async_fifo_tx_SPI.vhd + + +Constraint evaluation order for 'synthesis' with fileset 'async_fifo_tx_SPI': +Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name +----- ------------------------- ------------ ----------------- --------------- ---------------- -------------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +1 async_fifo_tx_SPI_ooc.xdc Synth & Impl async_fifo_tx_SPI U0 EARLY yes d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx_SPI/async_fifo_tx_SPI_ooc.xdc +2 async_fifo_tx_SPI.xdc Synth & Impl async_fifo_tx_SPI U0 EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx_SPI/async_fifo_tx_SPI/async_fifo_tx_SPI.xdc + + +Constraint evaluation order for 'implementation' with fileset 'async_fifo_tx_SPI': +Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name +----- ------------------------- ------------ ----------------- --------------- ---------------- -------------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +1 async_fifo_tx_SPI_ooc.xdc Synth & Impl async_fifo_tx_SPI U0 EARLY yes d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx_SPI/async_fifo_tx_SPI_ooc.xdc +2 async_fifo_tx_SPI.xdc Synth & Impl async_fifo_tx_SPI U0 EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_tx_SPI/async_fifo_tx_SPI/async_fifo_tx_SPI.xdc + + +---------------------------------------------------------- +| Compile Order for Out-of-Context BlockSet: 'async_fifo_rx_SPI' +| Top Module: 'async_fifo_rx_SPI' +---------------------------------------------------------- + +Source compile order for 'synthesis' with fileset 'async_fifo_rx_SPI' in source management mode 'All': +Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name +----- ---------------------------------- ------- --------- ---------------------- ----------- ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +1 blk_mem_gen_v8_3_vhsyn_rfs.vhd Synth VHDL blk_mem_gen_v8_3_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx_SPI/blk_mem_gen_v8_3_1/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd +2 blk_mem_gen_v8_3.vhd Synth VHDL blk_mem_gen_v8_3_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx_SPI/blk_mem_gen_v8_3_1/hdl/blk_mem_gen_v8_3.vhd +3 fifo_generator_v13_0_vhsyn_rfs.vhd Synth VHDL fifo_generator_v13_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx_SPI/fifo_generator_v13_0_1/hdl/fifo_generator_v13_0_vhsyn_rfs.vhd +4 fifo_generator_v13_0.vhd Synth VHDL fifo_generator_v13_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx_SPI/fifo_generator_v13_0_1/hdl/fifo_generator_v13_0.vhd +5 async_fifo_rx_SPI.vhd Synth VHDL xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx_SPI/synth/async_fifo_rx_SPI.vhd + + +Source compile order for 'simulation' with fileset 'async_fifo_rx_SPI' in source management mode 'All' and simulation language 'Mixed': +Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name +----- ---------------------------- ------- --------- ---------------------- ----------- ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +1 fifo_generator_vhdl_beh.vhd Sim VHDL fifo_generator_v13_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx_SPI/fifo_generator_v13_0_1/simulation/fifo_generator_vhdl_beh.vhd +2 fifo_generator_v13_0_rfs.vhd Sim VHDL fifo_generator_v13_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx_SPI/fifo_generator_v13_0_1/hdl/fifo_generator_v13_0_rfs.vhd +3 async_fifo_rx_SPI.vhd Sim VHDL xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx_SPI/sim/async_fifo_rx_SPI.vhd + + +Constraint evaluation order for 'synthesis' with fileset 'async_fifo_rx_SPI': +Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name +----- ------------------------- ------------ ----------------- --------------- ---------------- -------------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +1 async_fifo_rx_SPI_ooc.xdc Synth & Impl async_fifo_rx_SPI U0 EARLY yes d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx_SPI/async_fifo_rx_SPI_ooc.xdc +2 async_fifo_rx_SPI.xdc Synth & Impl async_fifo_rx_SPI U0 EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx_SPI/async_fifo_rx_SPI/async_fifo_rx_SPI.xdc + + +Constraint evaluation order for 'implementation' with fileset 'async_fifo_rx_SPI': +Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name +----- ------------------------- ------------ ----------------- --------------- ---------------- -------------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +1 async_fifo_rx_SPI_ooc.xdc Synth & Impl async_fifo_rx_SPI U0 EARLY yes d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx_SPI/async_fifo_rx_SPI_ooc.xdc +2 async_fifo_rx_SPI.xdc Synth & Impl async_fifo_rx_SPI U0 EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/async_fifo_rx_SPI/async_fifo_rx_SPI/async_fifo_rx_SPI.xdc + + +---------------------------------------------------------- +| Compile Order for Out-of-Context BlockSet: 'clk_dis1' +| Top Module: 'clk_dis1' +---------------------------------------------------------- + +Source compile order for 'synthesis' with fileset 'clk_dis1' in source management mode 'All': +Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name +----- ------------------ ----------- --------- -------------- ----------- ------------------------------------------------------------------------------------------------------------------------------------------------------------- +1 clk_dis1_clk_wiz.v Synth & Sim Verilog xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis1/clk_dis1_clk_wiz.v +2 clk_dis1.v Synth & Sim Verilog xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis1/clk_dis1.v + + +Source compile order for 'simulation' with fileset 'clk_dis1' in source management mode 'All' and simulation language 'Mixed': +Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name +----- ------------------ ----------- --------- -------------- ----------- ------------------------------------------------------------------------------------------------------------------------------------------------------------- +1 clk_dis1_clk_wiz.v Synth & Sim Verilog xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis1/clk_dis1_clk_wiz.v +2 clk_dis1.v Synth & Sim Verilog xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis1/clk_dis1.v + + +Constraint evaluation order for 'synthesis' with fileset 'clk_dis1': +Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name +----- ------------------ ------------ ------------- --------------- ---------------- -------------- ------------------------------------------------------------------------------------------------------------------------------------------------------------- +1 clk_dis1_ooc.xdc Synth & Impl clk_dis1 inst EARLY yes d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis1/clk_dis1_ooc.xdc +2 clk_dis1_board.xdc Synth & Impl clk_dis1 inst EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis1/clk_dis1_board.xdc +3 clk_dis1.xdc Synth & Impl clk_dis1 inst EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis1/clk_dis1.xdc + + +Constraint evaluation order for 'implementation' with fileset 'clk_dis1': +Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name +----- ------------------ ------------ ------------- --------------- ---------------- -------------- ------------------------------------------------------------------------------------------------------------------------------------------------------------- +1 clk_dis1_ooc.xdc Synth & Impl clk_dis1 inst EARLY yes d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis1/clk_dis1_ooc.xdc +2 clk_dis1_board.xdc Synth & Impl clk_dis1 inst EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis1/clk_dis1_board.xdc +3 clk_dis1.xdc Synth & Impl clk_dis1 inst EARLY d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/clk_dis1/clk_dis1.xdc + + +---------------------------------------------------------- +| Compile Order for Out-of-Context BlockSet: 'floating_multi' +| Top Module: 'floating_multi' +---------------------------------------------------------- + +Source compile order for 'synthesis' with fileset 'floating_multi' in source management mode 'All': +Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name +----- ---------------------------------- ----------- --------- ------------------------- ----------- ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +1 xbip_utils_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_utils_v3_0_5 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/xbip_utils_v3_0_5/hdl/xbip_utils_v3_0_vh_rfs.vhd +2 axi_utils_v2_0_vh_rfs.vhd Synth & Sim VHDL axi_utils_v2_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/axi_utils_v2_0_1/hdl/axi_utils_v2_0_vh_rfs.vhd +3 xbip_pipe_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_pipe_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0_vh_rfs.vhd +4 xbip_pipe_v3_0.vhd Synth & Sim VHDL xbip_pipe_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0.vhd +5 xbip_dsp48_wrapper_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_wrapper_v3_0_4 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/xbip_dsp48_wrapper_v3_0_4/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd +6 xbip_dsp48_addsub_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_addsub_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/xbip_dsp48_addsub_v3_0_1/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd +7 xbip_dsp48_addsub_v3_0.vhd Synth & Sim VHDL xbip_dsp48_addsub_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/xbip_dsp48_addsub_v3_0_1/hdl/xbip_dsp48_addsub_v3_0.vhd +8 xbip_dsp48_multadd_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_multadd_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd +9 xbip_dsp48_multadd_v3_0.vhd Synth & Sim VHDL xbip_dsp48_multadd_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0.vhd +10 xbip_bram18k_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_bram18k_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/xbip_bram18k_v3_0_1/hdl/xbip_bram18k_v3_0_vh_rfs.vhd +11 xbip_bram18k_v3_0.vhd Synth & Sim VHDL xbip_bram18k_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/xbip_bram18k_v3_0_1/hdl/xbip_bram18k_v3_0.vhd +12 mult_gen_v12_0_vh_rfs.vhd Synth & Sim VHDL mult_gen_v12_0_10 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/mult_gen_v12_0_10/hdl/mult_gen_v12_0_vh_rfs.vhd +13 mult_gen_v12_0.vhd Synth & Sim VHDL mult_gen_v12_0_10 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/mult_gen_v12_0_10/hdl/mult_gen_v12_0.vhd +14 floating_point_v7_1_vh_rfs.vhd Synth & Sim VHDL floating_point_v7_1_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/floating_point_v7_1_1/hdl/floating_point_v7_1_vh_rfs.vhd +15 floating_multi.vhd Synth VHDL xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/synth/floating_multi.vhd + + +Source compile order for 'simulation' with fileset 'floating_multi' in source management mode 'All' and simulation language 'Mixed': +Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name +----- ---------------------------------- ----------- --------- ------------------------- ----------- ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +1 xbip_utils_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_utils_v3_0_5 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/xbip_utils_v3_0_5/hdl/xbip_utils_v3_0_vh_rfs.vhd +2 axi_utils_v2_0_vh_rfs.vhd Synth & Sim VHDL axi_utils_v2_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/axi_utils_v2_0_1/hdl/axi_utils_v2_0_vh_rfs.vhd +3 xbip_pipe_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_pipe_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0_vh_rfs.vhd +4 xbip_pipe_v3_0.vhd Synth & Sim VHDL xbip_pipe_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0.vhd +5 xbip_dsp48_wrapper_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_wrapper_v3_0_4 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/xbip_dsp48_wrapper_v3_0_4/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd +6 xbip_dsp48_addsub_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_addsub_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/xbip_dsp48_addsub_v3_0_1/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd +7 xbip_dsp48_addsub_v3_0.vhd Synth & Sim VHDL xbip_dsp48_addsub_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/xbip_dsp48_addsub_v3_0_1/hdl/xbip_dsp48_addsub_v3_0.vhd +8 xbip_dsp48_multadd_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_multadd_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd +9 xbip_dsp48_multadd_v3_0.vhd Synth & Sim VHDL xbip_dsp48_multadd_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0.vhd +10 xbip_bram18k_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_bram18k_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/xbip_bram18k_v3_0_1/hdl/xbip_bram18k_v3_0_vh_rfs.vhd +11 xbip_bram18k_v3_0.vhd Synth & Sim VHDL xbip_bram18k_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/xbip_bram18k_v3_0_1/hdl/xbip_bram18k_v3_0.vhd +12 mult_gen_v12_0_vh_rfs.vhd Synth & Sim VHDL mult_gen_v12_0_10 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/mult_gen_v12_0_10/hdl/mult_gen_v12_0_vh_rfs.vhd +13 mult_gen_v12_0.vhd Synth & Sim VHDL mult_gen_v12_0_10 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/mult_gen_v12_0_10/hdl/mult_gen_v12_0.vhd +14 floating_point_v7_1_vh_rfs.vhd Synth & Sim VHDL floating_point_v7_1_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/floating_point_v7_1_1/hdl/floating_point_v7_1_vh_rfs.vhd +15 floating_multi.vhd Sim VHDL xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/sim/floating_multi.vhd + + +Constraint evaluation order for 'synthesis' with fileset 'floating_multi': +Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name +----- ---------------------- ------------ -------------- --------------- ---------------- -------------- ----------------------------------------------------------------------------------------------------------------------------------------------------------------------- +1 floating_multi_ooc.xdc Synth & Impl floating_multi U0 EARLY yes d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/floating_multi_ooc.xdc + + +Constraint evaluation order for 'implementation' with fileset 'floating_multi': +Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name +----- ---------------------- ------------ -------------- --------------- ---------------- -------------- ----------------------------------------------------------------------------------------------------------------------------------------------------------------------- +1 floating_multi_ooc.xdc Synth & Impl floating_multi U0 EARLY yes d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_multi/floating_multi_ooc.xdc + + +---------------------------------------------------------- +| Compile Order for Out-of-Context BlockSet: 'floating_add' +| Top Module: 'floating_add' +---------------------------------------------------------- + +Source compile order for 'synthesis' with fileset 'floating_add' in source management mode 'All': +Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name +----- ---------------------------------- ----------- --------- ------------------------- ----------- --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +1 xbip_utils_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_utils_v3_0_5 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/xbip_utils_v3_0_5/hdl/xbip_utils_v3_0_vh_rfs.vhd +2 axi_utils_v2_0_vh_rfs.vhd Synth & Sim VHDL axi_utils_v2_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/axi_utils_v2_0_1/hdl/axi_utils_v2_0_vh_rfs.vhd +3 xbip_pipe_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_pipe_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0_vh_rfs.vhd +4 xbip_pipe_v3_0.vhd Synth & Sim VHDL xbip_pipe_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0.vhd +5 xbip_dsp48_wrapper_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_wrapper_v3_0_4 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/xbip_dsp48_wrapper_v3_0_4/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd +6 xbip_dsp48_addsub_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_addsub_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/xbip_dsp48_addsub_v3_0_1/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd +7 xbip_dsp48_addsub_v3_0.vhd Synth & Sim VHDL xbip_dsp48_addsub_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/xbip_dsp48_addsub_v3_0_1/hdl/xbip_dsp48_addsub_v3_0.vhd +8 xbip_dsp48_multadd_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_multadd_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd +9 xbip_dsp48_multadd_v3_0.vhd Synth & Sim VHDL xbip_dsp48_multadd_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0.vhd +10 xbip_bram18k_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_bram18k_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/xbip_bram18k_v3_0_1/hdl/xbip_bram18k_v3_0_vh_rfs.vhd +11 xbip_bram18k_v3_0.vhd Synth & Sim VHDL xbip_bram18k_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/xbip_bram18k_v3_0_1/hdl/xbip_bram18k_v3_0.vhd +12 mult_gen_v12_0_vh_rfs.vhd Synth & Sim VHDL mult_gen_v12_0_10 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/mult_gen_v12_0_10/hdl/mult_gen_v12_0_vh_rfs.vhd +13 mult_gen_v12_0.vhd Synth & Sim VHDL mult_gen_v12_0_10 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/mult_gen_v12_0_10/hdl/mult_gen_v12_0.vhd +14 floating_point_v7_1_vh_rfs.vhd Synth & Sim VHDL floating_point_v7_1_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/floating_point_v7_1_1/hdl/floating_point_v7_1_vh_rfs.vhd +15 floating_add.vhd Synth VHDL xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/synth/floating_add.vhd + + +Source compile order for 'simulation' with fileset 'floating_add' in source management mode 'All' and simulation language 'Mixed': +Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name +----- ---------------------------------- ----------- --------- ------------------------- ----------- --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +1 xbip_utils_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_utils_v3_0_5 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/xbip_utils_v3_0_5/hdl/xbip_utils_v3_0_vh_rfs.vhd +2 axi_utils_v2_0_vh_rfs.vhd Synth & Sim VHDL axi_utils_v2_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/axi_utils_v2_0_1/hdl/axi_utils_v2_0_vh_rfs.vhd +3 xbip_pipe_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_pipe_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0_vh_rfs.vhd +4 xbip_pipe_v3_0.vhd Synth & Sim VHDL xbip_pipe_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0.vhd +5 xbip_dsp48_wrapper_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_wrapper_v3_0_4 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/xbip_dsp48_wrapper_v3_0_4/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd +6 xbip_dsp48_addsub_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_addsub_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/xbip_dsp48_addsub_v3_0_1/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd +7 xbip_dsp48_addsub_v3_0.vhd Synth & Sim VHDL xbip_dsp48_addsub_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/xbip_dsp48_addsub_v3_0_1/hdl/xbip_dsp48_addsub_v3_0.vhd +8 xbip_dsp48_multadd_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_multadd_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd +9 xbip_dsp48_multadd_v3_0.vhd Synth & Sim VHDL xbip_dsp48_multadd_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0.vhd +10 xbip_bram18k_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_bram18k_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/xbip_bram18k_v3_0_1/hdl/xbip_bram18k_v3_0_vh_rfs.vhd +11 xbip_bram18k_v3_0.vhd Synth & Sim VHDL xbip_bram18k_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/xbip_bram18k_v3_0_1/hdl/xbip_bram18k_v3_0.vhd +12 mult_gen_v12_0_vh_rfs.vhd Synth & Sim VHDL mult_gen_v12_0_10 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/mult_gen_v12_0_10/hdl/mult_gen_v12_0_vh_rfs.vhd +13 mult_gen_v12_0.vhd Synth & Sim VHDL mult_gen_v12_0_10 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/mult_gen_v12_0_10/hdl/mult_gen_v12_0.vhd +14 floating_point_v7_1_vh_rfs.vhd Synth & Sim VHDL floating_point_v7_1_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/floating_point_v7_1_1/hdl/floating_point_v7_1_vh_rfs.vhd +15 floating_add.vhd Sim VHDL xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/sim/floating_add.vhd + + +Constraint evaluation order for 'synthesis' with fileset 'floating_add': +Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name +----- -------------------- ------------ ------------- --------------- ---------------- -------------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------- +1 floating_add_ooc.xdc Synth & Impl floating_add U0 EARLY yes d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/floating_add_ooc.xdc + + +Constraint evaluation order for 'implementation' with fileset 'floating_add': +Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name +----- -------------------- ------------ ------------- --------------- ---------------- -------------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------- +1 floating_add_ooc.xdc Synth & Impl floating_add U0 EARLY yes d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_add/floating_add_ooc.xdc + + +---------------------------------------------------------- +| Compile Order for Out-of-Context BlockSet: 'floating_float' +| Top Module: 'floating_float' +---------------------------------------------------------- + +Source compile order for 'synthesis' with fileset 'floating_float' in source management mode 'All': +Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name +----- ---------------------------------- ----------- --------- ------------------------- ----------- ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +1 xbip_utils_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_utils_v3_0_5 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/xbip_utils_v3_0_5/hdl/xbip_utils_v3_0_vh_rfs.vhd +2 axi_utils_v2_0_vh_rfs.vhd Synth & Sim VHDL axi_utils_v2_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/axi_utils_v2_0_1/hdl/axi_utils_v2_0_vh_rfs.vhd +3 xbip_pipe_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_pipe_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0_vh_rfs.vhd +4 xbip_pipe_v3_0.vhd Synth & Sim VHDL xbip_pipe_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0.vhd +5 xbip_dsp48_wrapper_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_wrapper_v3_0_4 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/xbip_dsp48_wrapper_v3_0_4/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd +6 xbip_dsp48_addsub_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_addsub_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/xbip_dsp48_addsub_v3_0_1/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd +7 xbip_dsp48_addsub_v3_0.vhd Synth & Sim VHDL xbip_dsp48_addsub_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/xbip_dsp48_addsub_v3_0_1/hdl/xbip_dsp48_addsub_v3_0.vhd +8 xbip_dsp48_multadd_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_multadd_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd +9 xbip_dsp48_multadd_v3_0.vhd Synth & Sim VHDL xbip_dsp48_multadd_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0.vhd +10 xbip_bram18k_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_bram18k_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/xbip_bram18k_v3_0_1/hdl/xbip_bram18k_v3_0_vh_rfs.vhd +11 xbip_bram18k_v3_0.vhd Synth & Sim VHDL xbip_bram18k_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/xbip_bram18k_v3_0_1/hdl/xbip_bram18k_v3_0.vhd +12 mult_gen_v12_0_vh_rfs.vhd Synth & Sim VHDL mult_gen_v12_0_10 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/mult_gen_v12_0_10/hdl/mult_gen_v12_0_vh_rfs.vhd +13 mult_gen_v12_0.vhd Synth & Sim VHDL mult_gen_v12_0_10 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/mult_gen_v12_0_10/hdl/mult_gen_v12_0.vhd +14 floating_point_v7_1_vh_rfs.vhd Synth & Sim VHDL floating_point_v7_1_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/floating_point_v7_1_1/hdl/floating_point_v7_1_vh_rfs.vhd +15 floating_float.vhd Synth VHDL xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/synth/floating_float.vhd + + +Source compile order for 'simulation' with fileset 'floating_float' in source management mode 'All' and simulation language 'Mixed': +Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name +----- ---------------------------------- ----------- --------- ------------------------- ----------- ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +1 xbip_utils_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_utils_v3_0_5 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/xbip_utils_v3_0_5/hdl/xbip_utils_v3_0_vh_rfs.vhd +2 axi_utils_v2_0_vh_rfs.vhd Synth & Sim VHDL axi_utils_v2_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/axi_utils_v2_0_1/hdl/axi_utils_v2_0_vh_rfs.vhd +3 xbip_pipe_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_pipe_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0_vh_rfs.vhd +4 xbip_pipe_v3_0.vhd Synth & Sim VHDL xbip_pipe_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0.vhd +5 xbip_dsp48_wrapper_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_wrapper_v3_0_4 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/xbip_dsp48_wrapper_v3_0_4/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd +6 xbip_dsp48_addsub_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_addsub_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/xbip_dsp48_addsub_v3_0_1/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd +7 xbip_dsp48_addsub_v3_0.vhd Synth & Sim VHDL xbip_dsp48_addsub_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/xbip_dsp48_addsub_v3_0_1/hdl/xbip_dsp48_addsub_v3_0.vhd +8 xbip_dsp48_multadd_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_multadd_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd +9 xbip_dsp48_multadd_v3_0.vhd Synth & Sim VHDL xbip_dsp48_multadd_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0.vhd +10 xbip_bram18k_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_bram18k_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/xbip_bram18k_v3_0_1/hdl/xbip_bram18k_v3_0_vh_rfs.vhd +11 xbip_bram18k_v3_0.vhd Synth & Sim VHDL xbip_bram18k_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/xbip_bram18k_v3_0_1/hdl/xbip_bram18k_v3_0.vhd +12 mult_gen_v12_0_vh_rfs.vhd Synth & Sim VHDL mult_gen_v12_0_10 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/mult_gen_v12_0_10/hdl/mult_gen_v12_0_vh_rfs.vhd +13 mult_gen_v12_0.vhd Synth & Sim VHDL mult_gen_v12_0_10 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/mult_gen_v12_0_10/hdl/mult_gen_v12_0.vhd +14 floating_point_v7_1_vh_rfs.vhd Synth & Sim VHDL floating_point_v7_1_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/floating_point_v7_1_1/hdl/floating_point_v7_1_vh_rfs.vhd +15 floating_float.vhd Sim VHDL xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/sim/floating_float.vhd + + +Constraint evaluation order for 'synthesis' with fileset 'floating_float': +Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name +----- ---------------------- ------------ -------------- --------------- ---------------- -------------- ----------------------------------------------------------------------------------------------------------------------------------------------------------------------- +1 floating_float_ooc.xdc Synth & Impl floating_float U0 EARLY yes d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/floating_float_ooc.xdc + + +Constraint evaluation order for 'implementation' with fileset 'floating_float': +Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name +----- ---------------------- ------------ -------------- --------------- ---------------- -------------- ----------------------------------------------------------------------------------------------------------------------------------------------------------------------- +1 floating_float_ooc.xdc Synth & Impl floating_float U0 EARLY yes d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_float/floating_float_ooc.xdc + + +---------------------------------------------------------- +| Compile Order for Out-of-Context BlockSet: 'floating_fixed' +| Top Module: 'floating_fixed' +---------------------------------------------------------- + +Source compile order for 'synthesis' with fileset 'floating_fixed' in source management mode 'All': +Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name +----- ---------------------------------- ----------- --------- ------------------------- ----------- ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +1 xbip_utils_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_utils_v3_0_5 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/xbip_utils_v3_0_5/hdl/xbip_utils_v3_0_vh_rfs.vhd +2 axi_utils_v2_0_vh_rfs.vhd Synth & Sim VHDL axi_utils_v2_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/axi_utils_v2_0_1/hdl/axi_utils_v2_0_vh_rfs.vhd +3 xbip_pipe_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_pipe_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0_vh_rfs.vhd +4 xbip_pipe_v3_0.vhd Synth & Sim VHDL xbip_pipe_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0.vhd +5 xbip_dsp48_wrapper_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_wrapper_v3_0_4 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/xbip_dsp48_wrapper_v3_0_4/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd +6 xbip_dsp48_addsub_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_addsub_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/xbip_dsp48_addsub_v3_0_1/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd +7 xbip_dsp48_addsub_v3_0.vhd Synth & Sim VHDL xbip_dsp48_addsub_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/xbip_dsp48_addsub_v3_0_1/hdl/xbip_dsp48_addsub_v3_0.vhd +8 xbip_dsp48_multadd_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_multadd_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd +9 xbip_dsp48_multadd_v3_0.vhd Synth & Sim VHDL xbip_dsp48_multadd_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0.vhd +10 xbip_bram18k_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_bram18k_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/xbip_bram18k_v3_0_1/hdl/xbip_bram18k_v3_0_vh_rfs.vhd +11 xbip_bram18k_v3_0.vhd Synth & Sim VHDL xbip_bram18k_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/xbip_bram18k_v3_0_1/hdl/xbip_bram18k_v3_0.vhd +12 mult_gen_v12_0_vh_rfs.vhd Synth & Sim VHDL mult_gen_v12_0_10 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/mult_gen_v12_0_10/hdl/mult_gen_v12_0_vh_rfs.vhd +13 mult_gen_v12_0.vhd Synth & Sim VHDL mult_gen_v12_0_10 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/mult_gen_v12_0_10/hdl/mult_gen_v12_0.vhd +14 floating_point_v7_1_vh_rfs.vhd Synth & Sim VHDL floating_point_v7_1_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/floating_point_v7_1_1/hdl/floating_point_v7_1_vh_rfs.vhd +15 floating_fixed.vhd Synth VHDL xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/synth/floating_fixed.vhd + + +Source compile order for 'simulation' with fileset 'floating_fixed' in source management mode 'All' and simulation language 'Mixed': +Index File Name Used_In File_Type Library Ngc Wrapper Full Path Name +----- ---------------------------------- ----------- --------- ------------------------- ----------- ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +1 xbip_utils_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_utils_v3_0_5 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/xbip_utils_v3_0_5/hdl/xbip_utils_v3_0_vh_rfs.vhd +2 axi_utils_v2_0_vh_rfs.vhd Synth & Sim VHDL axi_utils_v2_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/axi_utils_v2_0_1/hdl/axi_utils_v2_0_vh_rfs.vhd +3 xbip_pipe_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_pipe_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0_vh_rfs.vhd +4 xbip_pipe_v3_0.vhd Synth & Sim VHDL xbip_pipe_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0.vhd +5 xbip_dsp48_wrapper_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_wrapper_v3_0_4 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/xbip_dsp48_wrapper_v3_0_4/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd +6 xbip_dsp48_addsub_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_addsub_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/xbip_dsp48_addsub_v3_0_1/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd +7 xbip_dsp48_addsub_v3_0.vhd Synth & Sim VHDL xbip_dsp48_addsub_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/xbip_dsp48_addsub_v3_0_1/hdl/xbip_dsp48_addsub_v3_0.vhd +8 xbip_dsp48_multadd_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_dsp48_multadd_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd +9 xbip_dsp48_multadd_v3_0.vhd Synth & Sim VHDL xbip_dsp48_multadd_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0.vhd +10 xbip_bram18k_v3_0_vh_rfs.vhd Synth & Sim VHDL xbip_bram18k_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/xbip_bram18k_v3_0_1/hdl/xbip_bram18k_v3_0_vh_rfs.vhd +11 xbip_bram18k_v3_0.vhd Synth & Sim VHDL xbip_bram18k_v3_0_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/xbip_bram18k_v3_0_1/hdl/xbip_bram18k_v3_0.vhd +12 mult_gen_v12_0_vh_rfs.vhd Synth & Sim VHDL mult_gen_v12_0_10 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/mult_gen_v12_0_10/hdl/mult_gen_v12_0_vh_rfs.vhd +13 mult_gen_v12_0.vhd Synth & Sim VHDL mult_gen_v12_0_10 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/mult_gen_v12_0_10/hdl/mult_gen_v12_0.vhd +14 floating_point_v7_1_vh_rfs.vhd Synth & Sim VHDL floating_point_v7_1_1 No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/floating_point_v7_1_1/hdl/floating_point_v7_1_vh_rfs.vhd +15 floating_fixed.vhd Sim VHDL xil_defaultlib No d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/sim/floating_fixed.vhd + + +Constraint evaluation order for 'synthesis' with fileset 'floating_fixed': +Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name +----- ---------------------- ------------ -------------- --------------- ---------------- -------------- ----------------------------------------------------------------------------------------------------------------------------------------------------------------------- +1 floating_fixed_ooc.xdc Synth & Impl floating_fixed U0 EARLY yes d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/floating_fixed_ooc.xdc + + +Constraint evaluation order for 'implementation' with fileset 'floating_fixed': +Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context Full Path Name +----- ---------------------- ------------ -------------- --------------- ---------------- -------------- ----------------------------------------------------------------------------------------------------------------------------------------------------------------------- +1 floating_fixed_ooc.xdc Synth & Impl floating_fixed U0 EARLY yes d:/0_2024/F2416_LYDG_wengsl_20240417/F2416_LYDG_wengsl_20240417/17-logic-20241108/17-logic-20241108/FT2000A2_K7.srcs/sources_1/ip/floating_fixed/floating_fixed_ooc.xdc + + diff --git a/txt解析版/txt版/config.txt b/txt解析版/txt版/config.txt new file mode 100644 index 0000000..4f206eb --- /dev/null +++ b/txt解析版/txt版/config.txt @@ -0,0 +1,6 @@ +# 支持的文件类型（不区分大小写） +# 每行一个后缀 +.v +.vhd +.vh +.vhdl \ No newline at end of file diff --git a/txt解析版/txt版/txt解析.exe b/txt解析版/txt版/txt解析.exe new file mode 100644 index 0000000..8689fff Binary files /dev/null and b/txt解析版/txt版/txt解析.exe differ diff --git a/txt解析版/txt版/使用说明.md b/txt解析版/txt版/使用说明.md new file mode 100644 index 0000000..cf21577 --- /dev/null +++ b/txt解析版/txt版/使用说明.md @@ -0,0 +1,3 @@ +将report_compile_order -file compile_order.txt命令生成的txt文件放入此目录（对txt文件名没有要求） +双击 txt解析.exe +脚本自动复制源代码文件到此目录下 \ No newline at end of file diff --git a/txt解析版/txt解析.py b/txt解析版/txt解析.py new file mode 100644 index 0000000..b2009c2 --- /dev/null +++ b/txt解析版/txt解析.py @@ -0,0 +1,176 @@ +import os +import shutil +import re +from datetime import datetime +import time + + +def find_latest_txt_file(): + """ + 在当前运行目录下查找最新修改的 .txt 文件，排除 config.txt + """ + cwd = os.getcwd() + txt_files = [ + os.path.join(cwd, f) + for f in os.listdir(cwd) + if f.lower().endswith(".txt") and not f.lower().startswith("config") + ] + + if not txt_files: + raise FileNotFoundError("当前目录下未找到任何非config的 .txt 文件") + + latest_txt = max(txt_files, key=os.path.getmtime) + return latest_txt + + +def load_extensions(config_path): + """ + 从 config.txt 读取需要的文件后缀集合 + """ + exts = set() + with open(config_path, "r", encoding="utf-8") as f: + for line in f: + line = line.strip().lower() + if not line or line.startswith("#"): + continue + if not line.startswith("."): + line = "." + line + exts.add(line) + return exts + + +def extract_and_copy_files(compile_order_path): + """ + 从 report_compile_order 输出文件中： + - 提取 Source Compile Order（Design Sources）第一个段落 + - 只保留 config.txt 中指定的需要的文件类型 + - 按完整路径复制文件 + """ + + try: + # 读取 config.txt 中需要的文件后缀 + config_path = os.path.join(os.getcwd(), "config.txt") + if not os.path.exists(config_path): + raise FileNotFoundError("当前目录下未找到 config.txt") + + include_exts = load_extensions(config_path) + print(f"从 config.txt 加载需要的文件后缀: {include_exts}") + + # ---------- 读取文件 ---------- + with open(compile_order_path, "r", encoding="utf-8") as f: + lines = f.readlines() + + # ---------- 定位 Source Compile Order 段落 ---------- + start_idx = None + end_idx = None + + for i, line in enumerate(lines): + if line.startswith("Source compile order for 'synthesis'"): + start_idx = i + continue + + if start_idx is not None and line.strip() == "": + end_idx = i + break + + if start_idx is None: + raise RuntimeError("未找到 Source compile order for 'synthesis' 段落") + + if end_idx is None: + end_idx = len(lines) + + section = lines[start_idx:end_idx] + + # ---------- 跳过标题 + 表头 ---------- + data_lines = section[2:] + + extracted_paths = [] + + for line in data_lines: + line = line.rstrip() + if not line: + continue + + # 行首必须是索引号 + if not re.match(r"\s*\d+\s+", line): + continue + + # 用 2 个及以上空格分割，最后一列一定是完整路径 + parts = re.split(r"\s{2,}", line) + if not parts: + continue + + full_path = parts[-1] + + # ---------- 只保留 config.txt 中指定的需要的文件类型 ---------- + file_ext = os.path.splitext(full_path)[1].lower() + if include_exts and file_ext not in include_exts: + continue + + extracted_paths.append(full_path) + + print(f"提取到 {len(extracted_paths)} 个需要的文件") + + # ---------- 创建输出目录 ---------- + now = datetime.now() + out_dir = now.strftime("Copy_Files_%Y%m%d_%H%M%S") + os.makedirs(out_dir) + print(f"创建输出目录: {out_dir}") + + # ---------- 复制文件 ---------- + copied = 0 + skipped = 0 + + for src in extracted_paths: + if not os.path.exists(src): + print(f"文件不存在，跳过: {src}") + skipped += 1 + continue + + base = os.path.basename(src) + dst = os.path.join(out_dir, base) + + # 避免重名覆盖 + if os.path.exists(dst): + name, ext = os.path.splitext(base) + idx = 1 + while True: + new_dst = os.path.join(out_dir, f"{name}_{idx}{ext}") + if not os.path.exists(new_dst): + dst = new_dst + break + idx += 1 + + shutil.copy2(src, dst) + copied += 1 + + print("\n复制完成") + print(f" 成功复制: {copied}") + print(f" 跳过文件: {skipped}") + print(f" 输出目录: {os.path.abspath(out_dir)}") + + return extracted_paths + + except Exception as e: + print("处理过程中发生错误:") + print(e) + return None + + +if __name__ == "__main__": + try: + input_file = find_latest_txt_file() + print(f"使用最新的 txt 文件: {input_file}") + + result = extract_and_copy_files(input_file) + + if not result: + print("未提取到任何文件") + + + except Exception as e: + print("程序异常退出:") + print(e) + + finally: + input("\n按回车键关闭窗口...") \ No newline at end of file diff --git a/txt解析版/使用说明.md b/txt解析版/使用说明.md new file mode 100644 index 0000000..088ce55 --- /dev/null +++ b/txt解析版/使用说明.md @@ -0,0 +1,3 @@ +将report_compile_order -file compile_order.txt命令生成的txt文件放入此目录（对txt文件名没有要求） +双击 源代码提取脚本.exe +脚本自动复制源代码文件到此目录下 \ No newline at end of file diff --git a/xpr解析版/README.md b/xpr解析版/README.md new file mode 100644 index 0000000..2e2c979 --- /dev/null +++ b/xpr解析版/README.md @@ -0,0 +1,99 @@ +# FPGA 项目源代码提取工具 + +从 Vivado/ISE 项目中自动提取**实际参与编译**的源代码文件。 + +--- + +## 功能说明 + +自动按优先级检测并提取： + +``` +.xpr (Vivado) → .xise (ISE) → .syr (ISE 综合报告) +``` + +- **只提取参与综合/synthesis/Implementation 的文件** +- 自动识别 testbench 并单独放入 `tb文件/` 子目录 +- 自动防重名覆盖（重名文件自动加 `_1`, `_2` 后缀） +- 输出目录带时间戳 `Copy_Files_YYYYMMDD_HHMMSS` + +--- + +## 使用方式 + +1. 在 `config.txt` 中配置**需要提取的文件后缀**（每行一个），例如： +``` +v +vhd +sv +vh +xdc +``` + +2. 运行脚本： +```bash +python xpr解析.py +``` + +3. 输入**项目根目录**路径（可以直接从资源管理器拖拽进来，自动去除引号） + +4. 脚本自动检测： + - 有 `.xpr` → 按 Vivado 解析 + - 无 `.xpr` 但有 `.xise` → 列出所有 `.xise`，让你选一个，然后按 ISE 解析 + - 无 `.xpr` 和 `.xise` 但有 `.syr` → 列出所有 `.syr`，让你选一个，然后按综合报告解析 + - 都没有 → 输出提示后退出 + +--- + +## ⚠️ 重要说明 + +> **项目根目录下必须要有 `.xpr` / `.xise` / `.syr` 其中之一才能提取**。 + +如果你的项目只有 `.ise`（二进制）： +- 请在 ISE 中打开 → `File → Save Project As` → 另存为 `.xise` 格式 +- 或者用已经跑过综合生成的 `.syr` 文件提取 + +--- + +## 路径解析规则 + +### Vivado (.xpr) +- `$PPRDIR/xxx/yyy.v` → 直接拼接 `项目根目录/xxx/yyy.v` +- `$PSRCDIR/xxx/yyy.v` → 优先在 `项目名.srcs/` 目录模糊匹配，找不到再全局搜索 + +### ISE (.xise) +- 路径都是相对项目根目录 → 直接拼接即可 +- 只要有 `` 就提取 + +### ISE (.syr) +- 正则匹配 `Compiling ... file "path/to/file.v"` 提取引号中的路径 +- 绝对路径存在就直接用，不存在则提取文件名去项目根目录找 +- 相对路径/纯文件名 → 模糊搜索 + +--- + +## 输出说明 + +输出目录 `Copy_Files_YYYYMMDD_HHMMSS`： +``` +Copy_Files_20260703_143025/ +├── top.v +├── uart.vhd +├── ... +└── tb文件/ + ├── tb_top.v + └── ... +``` + +程序末尾会打印统计信息： +- 成功复制数量 +- 跳过（文件不存在）数量 +- 未找到（解析到路径但定位失败）列表 +- 最终输出目录绝对路径 + +如果识别到 testbench 文件，会打印醒目的提醒： +``` +！！！！！！！！！！！！！！！！！！ +识别到项目中存在testbench文件,请在vivado中检查是否为源代码 +！！！！！！！！！！！！！！！！！！ +``` \ No newline at end of file diff --git a/xpr解析版/config.txt b/xpr解析版/config.txt new file mode 100644 index 0000000..4f206eb --- /dev/null +++ b/xpr解析版/config.txt @@ -0,0 +1,6 @@ +# 支持的文件类型（不区分大小写） +# 每行一个后缀 +.v +.vhd +.vh +.vhdl \ No newline at end of file diff --git a/xpr解析版/xpr版/config.txt b/xpr解析版/xpr版/config.txt new file mode 100644 index 0000000..4f206eb --- /dev/null +++ b/xpr解析版/xpr版/config.txt @@ -0,0 +1,6 @@ +# 支持的文件类型（不区分大小写） +# 每行一个后缀 +.v +.vhd +.vh +.vhdl \ No newline at end of file diff --git a/xpr解析版/xpr版/xpr解析.exe b/xpr解析版/xpr版/xpr解析.exe new file mode 100644 index 0000000..94a6f42 Binary files /dev/null and b/xpr解析版/xpr版/xpr解析.exe differ diff --git a/xpr解析版/xpr版/使用说明.md b/xpr解析版/xpr版/使用说明.md new file mode 100644 index 0000000..d363dd2 --- /dev/null +++ b/xpr解析版/xpr版/使用说明.md @@ -0,0 +1,2 @@ +双击 xpr解析.exe +将源代码所在项目的根目录路径输入到窗口，点击回车 (等待结果) diff --git a/xpr解析版/xpr解析.py b/xpr解析版/xpr解析.py new file mode 100644 index 0000000..5ee982d --- /dev/null +++ b/xpr解析版/xpr解析.py @@ -0,0 +1,339 @@ +import os +import shutil +import re +import xml.etree.ElementTree as ET +from pathlib import Path +from datetime import datetime + + +# ================================================= +# 用户配置区（唯一需要用户关心的地方） +# ================================================= +def get_project_root(): + """ + 获取用户输入的项目根目录，并验证路径是否存在 + """ + while True: + project_root = input("请输入你的工程根目录路径: ").strip() + if not project_root: + print("路径不能为空，请重新输入。") + continue + + # 处理路径中的引号 + if project_root.startswith('"') and project_root.endswith('"'): + project_root = project_root[1:-1] + elif project_root.startswith("'") and project_root.endswith("'"): + project_root = project_root[1:-1] + + # 检查路径是否存在 + if os.path.isdir(project_root): + return project_root + else: + print(f"错误: 路径 '{project_root}' 不存在，请重新输入。") + + + +# ================================================= +# Testbench 命名规则 +# ================================================= +TB_PATTERN = re.compile(r'(^tb_)|(_tb_)|(_tb\.)', re.IGNORECASE) + + +# ================================================= +# 通用工具函数 +# ================================================= + +def find_latest_xpr_in_dir(search_dir): + """ + 在指定目录下查找最新修改的 xpr 文件 + """ + files = [ + os.path.join(search_dir, f) + for f in os.listdir(search_dir) + if f.lower().endswith('.xpr') + ] + if not files: + raise FileNotFoundError(f"在目录 {search_dir} 下未找到 .xpr 文件") + return max(files, key=os.path.getmtime) + + +def load_extensions(config_path): + """ + 从 config.txt 读取需要的文件后缀集合 + """ + exts = set() + with open(config_path, "r", encoding="utf-8") as f: + for line in f: + line = line.strip().lower() + if not line or line.startswith("#"): + continue + if not line.startswith("."): + line = "." + line + exts.add(line) + return exts + + +def is_testbench_filename(file_path): + """ + 根据文件名判断是否是 testbench + """ + return bool(TB_PATTERN.search(Path(file_path).name.lower())) + + +# ================================================= +# 模糊路径解析（核心） +# ================================================= + +def extract_tail_from_psrcdir(path_str): + """ + 从 $PSRCDIR/xxx/yyy 提取 xxx/yyy + """ + marker = "$PSRCDIR/" + if marker not in path_str: + raise ValueError(f"路径中不包含 $PSRCDIR: {path_str}") + + return path_str.split(marker, 1)[1].replace("\\", "/") + + +def find_file_by_tail(root_dir, tail_path): + """ + 在 root_dir 下递归搜索， + 找到唯一一个以 tail_path 结尾的文件 + """ + matches = [] + tail_path = tail_path.replace("/", os.sep) + + for dirpath, _, filenames in os.walk(root_dir): + for name in filenames: + full_path = os.path.join(dirpath, name) + if full_path.endswith(tail_path): + matches.append(full_path) + + if not matches: + # 如果没找到文件，返回 None 表示未找到 + return None + + if len(matches) > 1: + # 如果找到多个匹配，返回第一个，但打印警告 + print(f"警告: 发现多个匹配文件，将使用第一个:\n" + "\n".join(matches)) + return matches[0] + + return matches[0] + + +def resolve_xpr_path(path_str, project_root, xpr_file_path): + """ + 将 xpr 中的 $PSRCDIR/... 解析为真实绝对路径 + 优先在与xpr文件同名的.srcs文件夹中查找，如果找不到再在根目录下进行全局匹配 + """ + if "$PSRCDIR/" not in path_str: + # 如果不包含 $PSRCDIR/ 标记，返回 None + return None + + tail = extract_tail_from_psrcdir(path_str) + + # 获取xpr文件名（不含扩展名）来构造.srcs目录名 + xpr_filename = os.path.splitext(os.path.basename(xpr_file_path))[0] + srcs_dir = os.path.join(project_root, xpr_filename + ".srcs") + + # 优先在.srcs目录中查找 + if os.path.isdir(srcs_dir): + real_path = find_file_by_tail(srcs_dir, tail) + if real_path is not None: + return real_path + + # 如果在.srcs目录中没找到，则在根目录下进行全局匹配 + return find_file_by_tail(project_root, tail) + + +# ================================================= +# 核心逻辑 +# ================================================= + +def extract_from_xpr_and_copy(xpr_path, config_path, project_root): + """ + 从 xpr 中解析 DesignSrcs + synthesis 文件集合， + 使用模糊匹配解析真实路径并复制 + """ + + include_exts = load_extensions(config_path) + + tree = ET.parse(xpr_path) + root = tree.getroot() + + result_files = [] + tb_files = [] + failed_files = [] # 记录未找到的文件 + + # 只遍历 DesignSrcs + for fileset in root.iter("FileSet"): + if fileset.get("Type") != "DesignSrcs": + continue + + for file_elem in fileset.findall("File"): + file_path = file_elem.get("Path") + if not file_path: + continue + + # config.txt 后缀过滤 - 排除不需要的文件 + suffix = Path(file_path).suffix.lower() + if include_exts and suffix not in include_exts: + continue + + # testbench 命名判断 + is_tb = is_testbench_filename(file_path) + + fileinfo = file_elem.find("FileInfo") + if fileinfo is None: + continue + + used_in_synth = False + auto_disabled = False + user_disabled = False + + for attr in fileinfo.findall("Attr"): + name = attr.get("Name") + val = (attr.get("Val") or "").lower() + + if name == "UsedIn" and val == "synthesis": + used_in_synth = True + elif name == "AutoDisabled" and val in ("1", "true"): + auto_disabled = True + elif name == "UserDisabled" and val in ("1", "true"): + user_disabled = True + + if used_in_synth and not auto_disabled and not user_disabled: + real_path = resolve_xpr_path(file_path, project_root, xpr_path) + if real_path is not None: + if is_tb: + tb_files.append(real_path) + else: + result_files.append(real_path) + else: + failed_files.append(file_path) # 记录未找到的文件路径 + + print(f"解析并定位到 {len(result_files)} 个非testbench文件") + print(f"解析并定位到 {len(tb_files)} 个testbench文件") + if failed_files: + print(f"未能找到 {len(failed_files)} 个文件") + + # ------------------------------------------------- + # 创建输出目录（秒级时间戳） + # ------------------------------------------------- + out_dir = datetime.now().strftime("Copy_Files_%Y%m%d_%H%M%S") + os.makedirs(out_dir) + print(f"创建输出目录: {out_dir}") + + # ------------------------------------------------- + # 创建tb文件目录（如果存在tb文件） + # ------------------------------------------------- + tb_out_dir = None + if tb_files: + tb_out_dir = os.path.join(out_dir, "tb文件") + os.makedirs(tb_out_dir) + print(f"创建testbench输出目录: {tb_out_dir}") + + # ------------------------------------------------- + # 复制非testbench文件 + # ------------------------------------------------- + copied_normal = 0 + skipped_normal = 0 + + for src in result_files: + if not os.path.exists(src): + print(f"文件不存在，跳过: {src}") + skipped_normal += 1 + continue + + base = os.path.basename(src) + dst = os.path.join(out_dir, base) + + # 防止重名覆盖 + if os.path.exists(dst): + name, ext = os.path.splitext(base) + idx = 1 + while True: + new_dst = os.path.join(out_dir, f"{name}_{idx}{ext}") + if not os.path.exists(new_dst): + dst = new_dst + break + idx += 1 + + shutil.copy2(src, dst) + copied_normal += 1 + + # ------------------------------------------------- + # 复制testbench文件 + # ------------------------------------------------- + copied_tb = 0 + skipped_tb = 0 + + for src in tb_files: + if not os.path.exists(src): + print(f"testbench文件不存在，跳过: {src}") + skipped_tb += 1 + continue + + base = os.path.basename(src) + dst = os.path.join(tb_out_dir, base) if tb_out_dir else os.path.join(out_dir, base) + + # 防止重名覆盖 + if os.path.exists(dst): + name, ext = os.path.splitext(base) + idx = 1 + while True: + new_dst = os.path.join(tb_out_dir, f"{name}_{idx}{ext}") if tb_out_dir else os.path.join(out_dir, f"{name}_{idx}{ext}") + if not os.path.exists(new_dst): + dst = new_dst + break + idx += 1 + + shutil.copy2(src, dst) + copied_tb += 1 + + print("复制完成") + print(f" 非testbench文件:") + print(f" 成功复制: {copied_normal}") + print(f" 跳过文件: {skipped_normal}") + + print(f" 未找到文件: {len(failed_files)}") + if failed_files: + print(" 未找到的文件列表:") + for failed_file in failed_files: + print(f" - {failed_file}") + print(f" 输出目录: {os.path.abspath(out_dir)}") + if tb_files: + print("\n！！！！！！！！！！！！！！！！！！") + print("识别到项目中存在testbench文件,请在vivado中检查是否为源代码") + print("！！！！！！！！！！！！！！！！！！") + + + +# ================================================= +# main +# ================================================= + +if __name__ == "__main__": + try: + PROJECT_ROOT = get_project_root() + if not os.path.isdir(PROJECT_ROOT): + raise RuntimeError(f"PROJECT_ROOT 不存在: {PROJECT_ROOT}") + + xpr_file = find_latest_xpr_in_dir(PROJECT_ROOT) + config_file = os.path.join(os.getcwd(), "config.txt") + + if not os.path.exists(config_file): + raise FileNotFoundError("当前目录下未找到 config.txt") + + print(f"使用 xpr 文件 : {xpr_file}") + print(f"使用 config 文件: {config_file}") + print(f"项目根目录 : {PROJECT_ROOT}") + + extract_from_xpr_and_copy(xpr_file, config_file, PROJECT_ROOT) + + except Exception as e: + print("程序执行失败:") + print(e) + + finally: + input("\n按回车键关闭窗口...") \ No newline at end of file diff --git a/xpr解析版/使用说明.md b/xpr解析版/使用说明.md new file mode 100644 index 0000000..4aed0da --- /dev/null +++ b/xpr解析版/使用说明.md @@ -0,0 +1,16 @@ +1. 在 `config.txt` 中配置**需要提取的文件后缀**（每行一个），例如： +``` +.v +.vhd +.vh +.vhdl +``` + +2. 运行脚本： +``` +双击 源代码提取.exe +将源代码所在项目的根目录路径输入到窗口，点击回车 (等待结果) +**项目根目录下必须要有 `.xpr` / `.xise` / `.syr` 其中之一才能提取**。 + +若项目根目录存在多个.xise或.syr文件，需要用户根据窗口提示选择正确的一个 +``` \ No newline at end of file diff --git a/xpr解析版/源代码提取.py b/xpr解析版/源代码提取.py new file mode 100644 index 0000000..0776100 --- /dev/null +++ b/xpr解析版/源代码提取.py @@ -0,0 +1,713 @@ +import os +import shutil +import re +import xml.etree.ElementTree as ET +from pathlib import Path +from datetime import datetime + + +# ================================================= +# 用户配置区（唯一需要用户关心的地方） +# ================================================= +def get_project_root(): + """ + 获取用户输入的项目根目录，并验证路径是否存在 + """ + while True: + project_root = input("请输入你的工程根目录路径: ").strip() + if not project_root: + print("路径不能为空，请重新输入。") + continue + + # 处理路径中的引号 + if project_root.startswith('"') and project_root.endswith('"'): + project_root = project_root[1:-1] + elif project_root.startswith("'") and project_root.endswith("'"): + project_root = project_root[1:-1] + + # 检查路径是否存在 + if os.path.isdir(project_root): + return project_root + else: + print(f"错误: 路径 '{project_root}' 不存在，请重新输入。") + + + +# ================================================= +# Testbench 命名规则 +# ================================================= +TB_PATTERN = re.compile(r'(^tb_)|(_tb_)|(_tb\.)', re.IGNORECASE) + + +# ================================================= +# 通用工具函数 +# ================================================= + +def find_latest_xpr_in_dir(search_dir): + """ + 在指定目录下查找最新修改的 xpr 文件，未找到返回 None + """ + files = [ + os.path.join(search_dir, f) + for f in os.listdir(search_dir) + if f.lower().endswith('.xpr') + ] + if not files: + return None + return max(files, key=os.path.getmtime) + + +def find_latest_file_in_dir(search_dir, extension): + """ + 在指定目录下查找最新修改的指定扩展名文件，未找到返回 None + """ + if not extension.startswith("."): + extension = "." + extension + files = [ + os.path.join(search_dir, f) + for f in os.listdir(search_dir) + if f.lower().endswith(extension.lower()) + ] + if not files: + return None + return max(files, key=os.path.getmtime) + + +def find_all_files_in_dir(search_dir, extension): + """ + 在指定目录下查找所有指定扩展名的文件，按修改时间降序排列 + """ + if not extension.startswith("."): + extension = "." + extension + files = [ + os.path.join(search_dir, f) + for f in os.listdir(search_dir) + if f.lower().endswith(extension.lower()) + ] + files.sort(key=os.path.getmtime, reverse=True) + return files + + +def user_select_file(files, file_type): + """ + 让用户从文件列表中选择一个，返回选中的文件路径 + 如果只有一个文件则自动选择 + """ + if len(files) == 1: + print(f"找到 1 个 {file_type} 文件，自动选择: {os.path.basename(files[0])}") + return files[0] + + print(f"请选择需要解析的 {file_type} 文件：") + for i, f in enumerate(files, 1): + print(f" {i} {os.path.basename(f)}") + + while True: + try: + choice = input("请输入对应编号: ").strip() + idx = int(choice) + if 1 <= idx <= len(files): + return files[idx - 1] + print(f"编号超出范围，请输入 1 ~ {len(files)}") + except ValueError: + print("输入无效，请输入数字编号") + + +def load_extensions(config_path): + """ + 从 config.txt 读取需要的文件后缀集合 + """ + exts = set() + with open(config_path, "r", encoding="utf-8") as f: + for line in f: + line = line.strip().lower() + if not line or line.startswith("#"): + continue + if not line.startswith("."): + line = "." + line + exts.add(line) + return exts + + +def is_testbench_filename(file_path): + """ + 根据文件名判断是否是 testbench + """ + return bool(TB_PATTERN.search(Path(file_path).name.lower())) + + +# ================================================= +# 模糊路径解析（核心） +# ================================================= + +def extract_tail_from_psrcdir(path_str): + """ + 从 $PSRCDIR/xxx/yyy 提取 xxx/yyy + """ + marker = "$PSRCDIR/" + if marker not in path_str: + raise ValueError(f"路径中不包含 $PSRCDIR: {path_str}") + + return path_str.split(marker, 1)[1].replace("\\", "/") + + +def find_file_by_tail(root_dir, tail_path): + """ + 在 root_dir 下递归搜索， + 找到唯一一个以 tail_path 结尾的文件 + """ + matches = [] + tail_path = tail_path.replace("/", os.sep) + + for dirpath, _, filenames in os.walk(root_dir): + for name in filenames: + full_path = os.path.join(dirpath, name) + if full_path.endswith(tail_path): + matches.append(full_path) + + if not matches: + # 如果没找到文件，返回 None 表示未找到 + return None + + if len(matches) > 1: + # 如果找到多个匹配，返回第一个，但打印警告 + print(f"警告: 发现多个匹配文件，将使用第一个:\n" + "\n".join(matches)) + return matches[0] + + return matches[0] + + +def resolve_xpr_path(path_str, project_root, xpr_file_path): + """ + 将 xpr 中的路径解析为真实绝对路径 + 支持 $PSRCDIR/ 和 $PPRDIR/ 两种 Vivado 路径变量 + """ + # 处理 $PPRDIR/ 路径（项目根目录下的相对路径） + if "$PPRDIR/" in path_str: + tail = path_str.split("$PPRDIR/", 1)[1].replace("\\", "/") + direct_path = os.path.normpath(os.path.join(project_root, tail)) + if os.path.exists(direct_path): + return direct_path + return find_file_by_tail(project_root, tail) + + # 处理 $PSRCDIR/ 路径（原有逻辑不变） + if "$PSRCDIR/" not in path_str: + return None + + tail = extract_tail_from_psrcdir(path_str) + + xpr_filename = os.path.splitext(os.path.basename(xpr_file_path))[0] + srcs_dir = os.path.join(project_root, xpr_filename + ".srcs") + + if os.path.isdir(srcs_dir): + real_path = find_file_by_tail(srcs_dir, tail) + if real_path is not None: + return real_path + + return find_file_by_tail(project_root, tail) + + +# ================================================= +# 通用 XML 工具 +# ================================================= + +def _get_attr_local(element, local_name): + """ + 忽略命名空间，按属性本地名获取值 + （同时兼容带命名空间和不带命名空间的 XML） + """ + for key, value in element.attrib.items(): + if key == local_name or key.endswith("}" + local_name): + return value + return None + + +def _get_tag_local(element): + """ + 忽略命名空间，返回标签的本地名 + """ + tag = element.tag + return tag.split("}")[-1] if "}" in tag else tag + + +# ================================================= +# 共享复制逻辑 +# ================================================= + +def _copy_extracted_files(result_files, tb_files, failed_files): + """ + 将解析出的文件列表复制到输出目录（公共逻辑） + """ + # 创建输出目录 + out_dir = datetime.now().strftime("Copy_Files_%Y%m%d_%H%M%S") + os.makedirs(out_dir) + print(f"创建输出目录: {out_dir}") + + tb_out_dir = None + if tb_files: + tb_out_dir = os.path.join(out_dir, "tb文件") + os.makedirs(tb_out_dir) + print(f"创建testbench输出目录: {tb_out_dir}") + + copied_normal = 0 + skipped_normal = 0 + + for src in result_files: + if not os.path.exists(src): + print(f"文件不存在，跳过: {src}") + skipped_normal += 1 + continue + + base = os.path.basename(src) + dst = os.path.join(out_dir, base) + + if os.path.exists(dst): + name, ext = os.path.splitext(base) + idx = 1 + while True: + new_dst = os.path.join(out_dir, f"{name}_{idx}{ext}") + if not os.path.exists(new_dst): + dst = new_dst + break + idx += 1 + + shutil.copy2(src, dst) + copied_normal += 1 + + copied_tb = 0 + skipped_tb = 0 + + for src in tb_files: + if not os.path.exists(src): + print(f"testbench文件不存在，跳过: {src}") + skipped_tb += 1 + continue + + base = os.path.basename(src) + dst = os.path.join(tb_out_dir, base) if tb_out_dir else os.path.join(out_dir, base) + + if os.path.exists(dst): + name, ext = os.path.splitext(base) + idx = 1 + while True: + new_dst = os.path.join(tb_out_dir, f"{name}_{idx}{ext}") if tb_out_dir else os.path.join(out_dir, f"{name}_{idx}{ext}") + if not os.path.exists(new_dst): + dst = new_dst + break + idx += 1 + + shutil.copy2(src, dst) + copied_tb += 1 + + print("复制完成") + print(f" 非testbench文件:") + print(f" 成功复制: {copied_normal}") + print(f" 跳过文件: {skipped_normal}") + print(f" testbench文件:") + print(f" 成功复制: {copied_tb}") + print(f" 跳过文件: {skipped_tb}") + print(f" 未找到文件: {len(failed_files)}") + if failed_files: + print(" 未找到的文件列表:") + for failed_file in failed_files: + print(f" - {failed_file}") + print(f" 输出目录: {os.path.abspath(out_dir)}") + if tb_files: + print("\n！！！！！！！！！！！！！！！！！！") + print("识别到项目中存在testbench文件,请在vivado中检查是否为源代码") + print("！！！！！！！！！！！！！！！！！！") + + +# ================================================= +# 核心逻辑 +# ================================================= + +def extract_from_xpr_and_copy(xpr_path, config_path, project_root): + """ + 从 xpr 中解析 DesignSrcs + synthesis 文件集合， + 使用模糊匹配解析真实路径并复制 + """ + + include_exts = load_extensions(config_path) + + tree = ET.parse(xpr_path) + root = tree.getroot() + + result_files = [] + tb_files = [] + failed_files = [] # 记录未找到的文件 + + # 只遍历 DesignSrcs + for fileset in root.iter("FileSet"): + if fileset.get("Type") != "DesignSrcs": + continue + + for file_elem in fileset.findall("File"): + file_path = file_elem.get("Path") + if not file_path: + continue + + # config.txt 后缀过滤 - 排除不需要的文件 + suffix = Path(file_path).suffix.lower() + if include_exts and suffix not in include_exts: + continue + + # testbench 命名判断 + is_tb = is_testbench_filename(file_path) + + fileinfo = file_elem.find("FileInfo") + if fileinfo is None: + continue + + used_in_synth = False + auto_disabled = False + user_disabled = False + + for attr in fileinfo.findall("Attr"): + name = attr.get("Name") + val = (attr.get("Val") or "").lower() + + if name == "UsedIn" and val == "synthesis": + used_in_synth = True + elif name == "AutoDisabled" and val in ("1", "true"): + auto_disabled = True + elif name == "UserDisabled" and val in ("1", "true"): + user_disabled = True + + if used_in_synth and not auto_disabled and not user_disabled: + real_path = resolve_xpr_path(file_path, project_root, xpr_path) + if real_path is not None: + if is_tb: + tb_files.append(real_path) + else: + result_files.append(real_path) + else: + failed_files.append(file_path) # 记录未找到的文件路径 + + print(f"解析并定位到 {len(result_files)} 个非testbench文件") + print(f"解析并定位到 {len(tb_files)} 个testbench文件") + if failed_files: + print(f"未能找到 {len(failed_files)} 个文件") + + _copy_extracted_files(result_files, tb_files, failed_files) + + +# ================================================= +# ISE (.xise) 解析 +# ================================================= + +def extract_from_xise_and_copy(xise_path, config_path, project_root): + """ + 从 .xise 中解析参与 Implementation 的源文件， + 如果存在 .syr 文件，取 (.xise ∩ .syr) 交集，只保留同时出现在两个列表中的文件 + """ + include_exts = load_extensions(config_path) + + tree = ET.parse(xise_path) + root = tree.getroot() + + # xise 解析结果：存原始路径（可能是相对也可能是绝对） + 解析后的绝对路径 + xise_result = [] # 原始路径（来自 xise 文件） + xise_abs_map = {} # 原始路径 → 解析后的绝对路径（用于复制） + xise_tb = [] + xise_tb_abs = {} + xise_library = [] # 带 标签的文件，始终保留 + xise_library_abs = {} + xise_failed = [] + + for file_elem in root.iter(): + if _get_tag_local(file_elem) != "file": + continue + + file_path = _get_attr_local(file_elem, "name") + if not file_path: + continue + + suffix = Path(file_path).suffix.lower() + if include_exts and suffix not in include_exts: + continue + + is_tb = is_testbench_filename(file_path) + + has_impl = False + has_library = False + for elem in file_elem.iter(): + tag = _get_tag_local(elem) + if tag == "association": + if _get_attr_local(elem, "name") == "Implementation": + has_impl = True + elif tag == "library": + has_library = True + + if not has_impl: + continue + + raw_path = file_path.replace("\\", "/") + # 尝试用 project_root 拼接解析（相对路径和绝对路径都能处理） + real_path = os.path.normpath(os.path.join(project_root, raw_path)) + if not os.path.exists(real_path): + # 可能是从其他电脑拷过来的绝对路径，用文件名在 project_root 下搜索 + real_path = find_file_by_tail(project_root, os.path.basename(raw_path)) + + if real_path and os.path.exists(real_path): + if is_tb: + xise_tb.append(raw_path) + xise_tb_abs[raw_path] = real_path + else: + xise_result.append(raw_path) + xise_abs_map[raw_path] = real_path + if has_library: + xise_library.append(raw_path) + xise_library_abs[raw_path] = real_path + else: + xise_failed.append(raw_path) + + print(f"从 .xise 解析到 {len(xise_result)} 个非testbench文件") + print(f"从 .xise 解析到 {len(xise_tb)} 个testbench文件") + if xise_library: + print(f"其中 {len(xise_library)} 个带 标签，将始终保留") + + # 查找 .syr 文件，如果有则提取并取交集 + syr_files = find_all_files_in_dir(project_root, ".syr") + if syr_files: + print(f"在项目根目录找到 {len(syr_files)} 个 .syr 文件") + chosen_syr = user_select_file(syr_files, ".syr") + print(f"使用 syr 文件进行二次过滤: {chosen_syr}") + syr_result, syr_tb, syr_failed = _parse_syr(chosen_syr, config_path, project_root) + + result_files = [] # 交集结果：xise 原始路径 + tb_files = [] + + # 第一阶段：严格匹配 —— 双方解析后的绝对路径做 normcase 比较 + syr_all_norm = set(os.path.normcase(f) for f in syr_result + syr_tb) + for raw_path in xise_result: + abs_path = xise_abs_map.get(raw_path) + if abs_path and os.path.normcase(abs_path) in syr_all_norm: + result_files.append(raw_path) + for raw_path in xise_tb: + abs_path = xise_tb_abs.get(raw_path) + if abs_path and os.path.normcase(abs_path) in syr_all_norm: + tb_files.append(raw_path) + + # 第二阶段：尾部组件匹配（补配因绝对/相对路径差异导致未匹配的文件） + # 注意：syr_all 必须包含 syr_failed 中的原始路径 —— + # syr 里来自其他电脑的绝对路径 resolve 失败后进了 syr_failed， + # 但它们的尾部仍然能和 xise 相对路径匹配上，必须参与比较 + xise_remaining = [f for f in xise_result if f not in result_files] + xise_tb_remaining = [f for f in xise_tb if f not in tb_files] + + if xise_remaining or xise_tb_remaining: + syr_all = syr_result + syr_tb + syr_failed + tail_matched = [] + matched_syr_failed = set() + for raw_path in xise_remaining: + for syr_path in syr_all: + if paths_match_tail(raw_path, syr_path): + result_files.append(raw_path) + tail_matched.append(raw_path) + if syr_path in syr_failed: + matched_syr_failed.add(syr_path) + break + for raw_path in xise_tb_remaining: + for syr_path in syr_all: + if paths_match_tail(raw_path, syr_path): + tb_files.append(raw_path) + tail_matched.append(raw_path) + if syr_path in syr_failed: + matched_syr_failed.add(syr_path) + break + if tail_matched: + print(f"尾部匹配补配 {len(tail_matched)} 个文件（绝对/相对路径差异）") + + # 已匹配的 syr 路径从失败列表中移除，避免误导 + failed_files = xise_failed + [f for f in syr_failed if f not in matched_syr_failed] + + print(f"\n交集后保留 {len(result_files)} 个非testbench文件") + print(f"交集后保留 {len(tb_files)} 个testbench文件") + else: + result_files = xise_result + tb_files = xise_tb + failed_files = xise_failed + print("项目根目录未找到 .syr 文件，直接使用 .xise 结果") + + if failed_files: + print(f"未能找到 {len(failed_files)} 个文件") + + # 用 xise 侧映射重建绝对路径用于复制（xise/syr 中的绝对路径可能来自其他电脑，不可信） + def _resolve_xise(raw_path, abs_map): + if raw_path in abs_map: + return abs_map[raw_path] + # 兜底：直接用 project_root 拼接 + return os.path.normpath(os.path.join(project_root, raw_path.replace("\\", "/"))) + + result_files_abs = [_resolve_xise(f, xise_abs_map) for f in result_files] + tb_files_abs = [_resolve_xise(f, xise_tb_abs) for f in tb_files] + + # 合并带 标签的文件（始终保留） + for raw_path in xise_library: + abs_path = _resolve_xise(raw_path, xise_library_abs) + if abs_path not in result_files_abs and abs_path not in tb_files_abs: + result_files_abs.append(abs_path) + + _copy_extracted_files(result_files_abs, tb_files_abs, failed_files) + + +# ================================================= +# ISE (.syr) 解析 +# ================================================= + +SYR_PATTERN = re.compile(r'Compiling\s+\w+\s+file\s+"([^"]+)"', re.IGNORECASE) + + +def paths_match_tail(path_a, path_b): + """ + 判断两个路径的尾部组件是否匹配。 + 将路径拆分为组件列表，检查较短列表是否为较长列表的后缀。 + 无论绝对/相对路径、正斜杠/反斜杠、盘符差异，都能正确匹配。 + + 例: ../src/pro/xxx.v vs C:/Users/.../src/pro/xxx.v → 匹配（尾部 src/pro/xxx.v 相同） + ./xxx.v vs F:/project/xxx.v → 匹配 + xxx.v vs F:/project/xxx.v → 匹配 + """ + def _normalize_parts(p): + p = p.replace("\\", "/").lower() + if len(p) >= 2 and p[1] == ":": + p = p[2:] + while p.startswith("../"): + p = p[3:] + while p.startswith("./"): + p = p[2:] + p = p.strip("/") + return p.split("/") if p else [] + + parts_a = _normalize_parts(path_a) + parts_b = _normalize_parts(path_b) + + if not parts_a or not parts_b: + return False + + if len(parts_a) <= len(parts_b): + return parts_a == parts_b[-len(parts_a):] + else: + return parts_b == parts_a[-len(parts_b):] + + +def resolve_syr_path(extracted_path, project_root): + """ + 从 .syr 中提取的路径解析为真实绝对路径 + 支持绝对路径 / 相对路径 / 纯文件名 + """ + extracted_path = extracted_path.replace("\\", "/").strip() + + if os.path.isabs(extracted_path): + if os.path.exists(extracted_path): + return os.path.normpath(extracted_path) + filename = os.path.basename(extracted_path) + if os.path.exists(os.path.join(project_root, filename)): + return os.path.normpath(os.path.join(project_root, filename)) + + # 相对路径：和 xise 一样用 os.path.join + normpath，保留完整目录结构 + real_path = os.path.normpath(os.path.join(project_root, extracted_path)) + if os.path.exists(real_path): + return real_path + + # 回退：用文件名模糊搜索 + tail = os.path.basename(extracted_path) + return find_file_by_tail(project_root, tail) + + +def _parse_syr(syr_path, config_path, project_root): + """ + 从 .syr 综合报告中解析源文件，返回 (result_files, tb_files, failed_files) + 不执行复制，供内部调用做交集等操作 + """ + include_exts = load_extensions(config_path) + + result_files = [] + tb_files = [] + failed_files = [] + seen_paths = set() + + with open(syr_path, "r", encoding="utf-8", errors="ignore") as f: + for line in f: + matches = SYR_PATTERN.findall(line) + for extracted_path in matches: + if extracted_path in seen_paths: + continue + seen_paths.add(extracted_path) + + suffix = Path(extracted_path).suffix.lower() + if include_exts and suffix not in include_exts: + continue + + is_tb = is_testbench_filename(extracted_path) + + real_path = resolve_syr_path(extracted_path, project_root) + if real_path is not None and os.path.exists(real_path): + if is_tb: + tb_files.append(real_path) + else: + result_files.append(real_path) + else: + failed_files.append(extracted_path) + + return result_files, tb_files, failed_files + + +def extract_from_syr_and_copy(syr_path, config_path, project_root): + """ + 从 .syr 综合报告中解析源文件并复制 + 匹配模式: Compiling vhdl file "path/to/file.vhd" in Library work + """ + result_files, tb_files, failed_files = _parse_syr(syr_path, config_path, project_root) + + print(f"解析并定位到 {len(result_files)} 个非testbench文件") + print(f"解析并定位到 {len(tb_files)} 个testbench文件") + if failed_files: + print(f"未能找到 {len(failed_files)} 个文件") + + _copy_extracted_files(result_files, tb_files, failed_files) + + +# ================================================= +# main +# ================================================= + +if __name__ == "__main__": + try: + PROJECT_ROOT = get_project_root() + if not os.path.isdir(PROJECT_ROOT): + raise RuntimeError(f"PROJECT_ROOT 不存在: {PROJECT_ROOT}") + + config_file = os.path.join(os.getcwd(), "config.txt") + if not os.path.exists(config_file): + raise FileNotFoundError("当前目录下未找到 config.txt") + + print(f"使用 config 文件: {config_file}") + print(f"项目根目录 : {PROJECT_ROOT}") + + # 优先级: .xpr → .xise → .syr + xpr_file = find_latest_xpr_in_dir(PROJECT_ROOT) + if xpr_file: + print(f"使用 xpr 文件 : {xpr_file}") + extract_from_xpr_and_copy(xpr_file, config_file, PROJECT_ROOT) + else: + xise_files = find_all_files_in_dir(PROJECT_ROOT, ".xise") + if xise_files: + chosen_xise = user_select_file(xise_files, ".xise") + print(f"使用 xise 文件 : {chosen_xise}") + extract_from_xise_and_copy(chosen_xise, config_file, PROJECT_ROOT) + else: + syr_files = find_all_files_in_dir(PROJECT_ROOT, ".syr") + if syr_files: + chosen_syr = user_select_file(syr_files, ".syr") + print(f"使用 syr 文件 : {chosen_syr}") + extract_from_syr_and_copy(chosen_syr, config_file, PROJECT_ROOT) + else: + print("当前项目下没有能提取源代码的文件依据") + + except Exception as e: + print("程序执行失败:") + print(e) + + finally: + input("\n按回车键关闭窗口...") \ No newline at end of file diff --git a/杂交版/config.txt b/杂交版/config.txt new file mode 100644 index 0000000..4f206eb --- /dev/null +++ b/杂交版/config.txt @@ -0,0 +1,6 @@ +# 支持的文件类型（不区分大小写） +# 每行一个后缀 +.v +.vhd +.vh +.vhdl \ No newline at end of file diff --git a/杂交版/使用说明.md b/杂交版/使用说明.md new file mode 100644 index 0000000..09a4f87 --- /dev/null +++ b/杂交版/使用说明.md @@ -0,0 +1,22 @@ +1. 在 `config.txt` 中配置**需要提取的文件后缀**（每行一个），例如： +``` +.v +.vhd +.vh +.vhdl +``` + +2. 运行脚本： +``` +双击 源代码提取.exe +将源代码所在项目的根目录路径输入到窗口，点击回车 (等待结果) +**项目根目录下必须要有 `.xpr` / `.xise` / `.syr` 其中之一才能提取**。 + +!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! 若项目为ise项目，根据.syr项目提取出的源代码可能包含IP文件,需要人工进行辨别 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + +!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! 若项目为ise项目，根据.syr项目提取出的源代码可能包含IP文件,需要人工进行辨别 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + +!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! 若项目为ise项目，根据.syr项目提取出的源代码可能包含IP文件,需要人工进行辨别 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + +若项目根目录存在多个.xise或.syr文件，用户需要根据窗口提示选择正确的一个 +``` \ No newline at end of file diff --git a/杂交版/源代码提取.py b/杂交版/源代码提取.py new file mode 100644 index 0000000..0776100 --- /dev/null +++ b/杂交版/源代码提取.py @@ -0,0 +1,713 @@ +import os +import shutil +import re +import xml.etree.ElementTree as ET +from pathlib import Path +from datetime import datetime + + +# ================================================= +# 用户配置区（唯一需要用户关心的地方） +# ================================================= +def get_project_root(): + """ + 获取用户输入的项目根目录，并验证路径是否存在 + """ + while True: + project_root = input("请输入你的工程根目录路径: ").strip() + if not project_root: + print("路径不能为空，请重新输入。") + continue + + # 处理路径中的引号 + if project_root.startswith('"') and project_root.endswith('"'): + project_root = project_root[1:-1] + elif project_root.startswith("'") and project_root.endswith("'"): + project_root = project_root[1:-1] + + # 检查路径是否存在 + if os.path.isdir(project_root): + return project_root + else: + print(f"错误: 路径 '{project_root}' 不存在，请重新输入。") + + + +# ================================================= +# Testbench 命名规则 +# ================================================= +TB_PATTERN = re.compile(r'(^tb_)|(_tb_)|(_tb\.)', re.IGNORECASE) + + +# ================================================= +# 通用工具函数 +# ================================================= + +def find_latest_xpr_in_dir(search_dir): + """ + 在指定目录下查找最新修改的 xpr 文件，未找到返回 None + """ + files = [ + os.path.join(search_dir, f) + for f in os.listdir(search_dir) + if f.lower().endswith('.xpr') + ] + if not files: + return None + return max(files, key=os.path.getmtime) + + +def find_latest_file_in_dir(search_dir, extension): + """ + 在指定目录下查找最新修改的指定扩展名文件，未找到返回 None + """ + if not extension.startswith("."): + extension = "." + extension + files = [ + os.path.join(search_dir, f) + for f in os.listdir(search_dir) + if f.lower().endswith(extension.lower()) + ] + if not files: + return None + return max(files, key=os.path.getmtime) + + +def find_all_files_in_dir(search_dir, extension): + """ + 在指定目录下查找所有指定扩展名的文件，按修改时间降序排列 + """ + if not extension.startswith("."): + extension = "." + extension + files = [ + os.path.join(search_dir, f) + for f in os.listdir(search_dir) + if f.lower().endswith(extension.lower()) + ] + files.sort(key=os.path.getmtime, reverse=True) + return files + + +def user_select_file(files, file_type): + """ + 让用户从文件列表中选择一个，返回选中的文件路径 + 如果只有一个文件则自动选择 + """ + if len(files) == 1: + print(f"找到 1 个 {file_type} 文件，自动选择: {os.path.basename(files[0])}") + return files[0] + + print(f"请选择需要解析的 {file_type} 文件：") + for i, f in enumerate(files, 1): + print(f" {i} {os.path.basename(f)}") + + while True: + try: + choice = input("请输入对应编号: ").strip() + idx = int(choice) + if 1 <= idx <= len(files): + return files[idx - 1] + print(f"编号超出范围，请输入 1 ~ {len(files)}") + except ValueError: + print("输入无效，请输入数字编号") + + +def load_extensions(config_path): + """ + 从 config.txt 读取需要的文件后缀集合 + """ + exts = set() + with open(config_path, "r", encoding="utf-8") as f: + for line in f: + line = line.strip().lower() + if not line or line.startswith("#"): + continue + if not line.startswith("."): + line = "." + line + exts.add(line) + return exts + + +def is_testbench_filename(file_path): + """ + 根据文件名判断是否是 testbench + """ + return bool(TB_PATTERN.search(Path(file_path).name.lower())) + + +# ================================================= +# 模糊路径解析（核心） +# ================================================= + +def extract_tail_from_psrcdir(path_str): + """ + 从 $PSRCDIR/xxx/yyy 提取 xxx/yyy + """ + marker = "$PSRCDIR/" + if marker not in path_str: + raise ValueError(f"路径中不包含 $PSRCDIR: {path_str}") + + return path_str.split(marker, 1)[1].replace("\\", "/") + + +def find_file_by_tail(root_dir, tail_path): + """ + 在 root_dir 下递归搜索， + 找到唯一一个以 tail_path 结尾的文件 + """ + matches = [] + tail_path = tail_path.replace("/", os.sep) + + for dirpath, _, filenames in os.walk(root_dir): + for name in filenames: + full_path = os.path.join(dirpath, name) + if full_path.endswith(tail_path): + matches.append(full_path) + + if not matches: + # 如果没找到文件，返回 None 表示未找到 + return None + + if len(matches) > 1: + # 如果找到多个匹配，返回第一个，但打印警告 + print(f"警告: 发现多个匹配文件，将使用第一个:\n" + "\n".join(matches)) + return matches[0] + + return matches[0] + + +def resolve_xpr_path(path_str, project_root, xpr_file_path): + """ + 将 xpr 中的路径解析为真实绝对路径 + 支持 $PSRCDIR/ 和 $PPRDIR/ 两种 Vivado 路径变量 + """ + # 处理 $PPRDIR/ 路径（项目根目录下的相对路径） + if "$PPRDIR/" in path_str: + tail = path_str.split("$PPRDIR/", 1)[1].replace("\\", "/") + direct_path = os.path.normpath(os.path.join(project_root, tail)) + if os.path.exists(direct_path): + return direct_path + return find_file_by_tail(project_root, tail) + + # 处理 $PSRCDIR/ 路径（原有逻辑不变） + if "$PSRCDIR/" not in path_str: + return None + + tail = extract_tail_from_psrcdir(path_str) + + xpr_filename = os.path.splitext(os.path.basename(xpr_file_path))[0] + srcs_dir = os.path.join(project_root, xpr_filename + ".srcs") + + if os.path.isdir(srcs_dir): + real_path = find_file_by_tail(srcs_dir, tail) + if real_path is not None: + return real_path + + return find_file_by_tail(project_root, tail) + + +# ================================================= +# 通用 XML 工具 +# ================================================= + +def _get_attr_local(element, local_name): + """ + 忽略命名空间，按属性本地名获取值 + （同时兼容带命名空间和不带命名空间的 XML） + """ + for key, value in element.attrib.items(): + if key == local_name or key.endswith("}" + local_name): + return value + return None + + +def _get_tag_local(element): + """ + 忽略命名空间，返回标签的本地名 + """ + tag = element.tag + return tag.split("}")[-1] if "}" in tag else tag + + +# ================================================= +# 共享复制逻辑 +# ================================================= + +def _copy_extracted_files(result_files, tb_files, failed_files): + """ + 将解析出的文件列表复制到输出目录（公共逻辑） + """ + # 创建输出目录 + out_dir = datetime.now().strftime("Copy_Files_%Y%m%d_%H%M%S") + os.makedirs(out_dir) + print(f"创建输出目录: {out_dir}") + + tb_out_dir = None + if tb_files: + tb_out_dir = os.path.join(out_dir, "tb文件") + os.makedirs(tb_out_dir) + print(f"创建testbench输出目录: {tb_out_dir}") + + copied_normal = 0 + skipped_normal = 0 + + for src in result_files: + if not os.path.exists(src): + print(f"文件不存在，跳过: {src}") + skipped_normal += 1 + continue + + base = os.path.basename(src) + dst = os.path.join(out_dir, base) + + if os.path.exists(dst): + name, ext = os.path.splitext(base) + idx = 1 + while True: + new_dst = os.path.join(out_dir, f"{name}_{idx}{ext}") + if not os.path.exists(new_dst): + dst = new_dst + break + idx += 1 + + shutil.copy2(src, dst) + copied_normal += 1 + + copied_tb = 0 + skipped_tb = 0 + + for src in tb_files: + if not os.path.exists(src): + print(f"testbench文件不存在，跳过: {src}") + skipped_tb += 1 + continue + + base = os.path.basename(src) + dst = os.path.join(tb_out_dir, base) if tb_out_dir else os.path.join(out_dir, base) + + if os.path.exists(dst): + name, ext = os.path.splitext(base) + idx = 1 + while True: + new_dst = os.path.join(tb_out_dir, f"{name}_{idx}{ext}") if tb_out_dir else os.path.join(out_dir, f"{name}_{idx}{ext}") + if not os.path.exists(new_dst): + dst = new_dst + break + idx += 1 + + shutil.copy2(src, dst) + copied_tb += 1 + + print("复制完成") + print(f" 非testbench文件:") + print(f" 成功复制: {copied_normal}") + print(f" 跳过文件: {skipped_normal}") + print(f" testbench文件:") + print(f" 成功复制: {copied_tb}") + print(f" 跳过文件: {skipped_tb}") + print(f" 未找到文件: {len(failed_files)}") + if failed_files: + print(" 未找到的文件列表:") + for failed_file in failed_files: + print(f" - {failed_file}") + print(f" 输出目录: {os.path.abspath(out_dir)}") + if tb_files: + print("\n！！！！！！！！！！！！！！！！！！") + print("识别到项目中存在testbench文件,请在vivado中检查是否为源代码") + print("！！！！！！！！！！！！！！！！！！") + + +# ================================================= +# 核心逻辑 +# ================================================= + +def extract_from_xpr_and_copy(xpr_path, config_path, project_root): + """ + 从 xpr 中解析 DesignSrcs + synthesis 文件集合， + 使用模糊匹配解析真实路径并复制 + """ + + include_exts = load_extensions(config_path) + + tree = ET.parse(xpr_path) + root = tree.getroot() + + result_files = [] + tb_files = [] + failed_files = [] # 记录未找到的文件 + + # 只遍历 DesignSrcs + for fileset in root.iter("FileSet"): + if fileset.get("Type") != "DesignSrcs": + continue + + for file_elem in fileset.findall("File"): + file_path = file_elem.get("Path") + if not file_path: + continue + + # config.txt 后缀过滤 - 排除不需要的文件 + suffix = Path(file_path).suffix.lower() + if include_exts and suffix not in include_exts: + continue + + # testbench 命名判断 + is_tb = is_testbench_filename(file_path) + + fileinfo = file_elem.find("FileInfo") + if fileinfo is None: + continue + + used_in_synth = False + auto_disabled = False + user_disabled = False + + for attr in fileinfo.findall("Attr"): + name = attr.get("Name") + val = (attr.get("Val") or "").lower() + + if name == "UsedIn" and val == "synthesis": + used_in_synth = True + elif name == "AutoDisabled" and val in ("1", "true"): + auto_disabled = True + elif name == "UserDisabled" and val in ("1", "true"): + user_disabled = True + + if used_in_synth and not auto_disabled and not user_disabled: + real_path = resolve_xpr_path(file_path, project_root, xpr_path) + if real_path is not None: + if is_tb: + tb_files.append(real_path) + else: + result_files.append(real_path) + else: + failed_files.append(file_path) # 记录未找到的文件路径 + + print(f"解析并定位到 {len(result_files)} 个非testbench文件") + print(f"解析并定位到 {len(tb_files)} 个testbench文件") + if failed_files: + print(f"未能找到 {len(failed_files)} 个文件") + + _copy_extracted_files(result_files, tb_files, failed_files) + + +# ================================================= +# ISE (.xise) 解析 +# ================================================= + +def extract_from_xise_and_copy(xise_path, config_path, project_root): + """ + 从 .xise 中解析参与 Implementation 的源文件， + 如果存在 .syr 文件，取 (.xise ∩ .syr) 交集，只保留同时出现在两个列表中的文件 + """ + include_exts = load_extensions(config_path) + + tree = ET.parse(xise_path) + root = tree.getroot() + + # xise 解析结果：存原始路径（可能是相对也可能是绝对） + 解析后的绝对路径 + xise_result = [] # 原始路径（来自 xise 文件） + xise_abs_map = {} # 原始路径 → 解析后的绝对路径（用于复制） + xise_tb = [] + xise_tb_abs = {} + xise_library = [] # 带 标签的文件，始终保留 + xise_library_abs = {} + xise_failed = [] + + for file_elem in root.iter(): + if _get_tag_local(file_elem) != "file": + continue + + file_path = _get_attr_local(file_elem, "name") + if not file_path: + continue + + suffix = Path(file_path).suffix.lower() + if include_exts and suffix not in include_exts: + continue + + is_tb = is_testbench_filename(file_path) + + has_impl = False + has_library = False + for elem in file_elem.iter(): + tag = _get_tag_local(elem) + if tag == "association": + if _get_attr_local(elem, "name") == "Implementation": + has_impl = True + elif tag == "library": + has_library = True + + if not has_impl: + continue + + raw_path = file_path.replace("\\", "/") + # 尝试用 project_root 拼接解析（相对路径和绝对路径都能处理） + real_path = os.path.normpath(os.path.join(project_root, raw_path)) + if not os.path.exists(real_path): + # 可能是从其他电脑拷过来的绝对路径，用文件名在 project_root 下搜索 + real_path = find_file_by_tail(project_root, os.path.basename(raw_path)) + + if real_path and os.path.exists(real_path): + if is_tb: + xise_tb.append(raw_path) + xise_tb_abs[raw_path] = real_path + else: + xise_result.append(raw_path) + xise_abs_map[raw_path] = real_path + if has_library: + xise_library.append(raw_path) + xise_library_abs[raw_path] = real_path + else: + xise_failed.append(raw_path) + + print(f"从 .xise 解析到 {len(xise_result)} 个非testbench文件") + print(f"从 .xise 解析到 {len(xise_tb)} 个testbench文件") + if xise_library: + print(f"其中 {len(xise_library)} 个带 标签，将始终保留") + + # 查找 .syr 文件，如果有则提取并取交集 + syr_files = find_all_files_in_dir(project_root, ".syr") + if syr_files: + print(f"在项目根目录找到 {len(syr_files)} 个 .syr 文件") + chosen_syr = user_select_file(syr_files, ".syr") + print(f"使用 syr 文件进行二次过滤: {chosen_syr}") + syr_result, syr_tb, syr_failed = _parse_syr(chosen_syr, config_path, project_root) + + result_files = [] # 交集结果：xise 原始路径 + tb_files = [] + + # 第一阶段：严格匹配 —— 双方解析后的绝对路径做 normcase 比较 + syr_all_norm = set(os.path.normcase(f) for f in syr_result + syr_tb) + for raw_path in xise_result: + abs_path = xise_abs_map.get(raw_path) + if abs_path and os.path.normcase(abs_path) in syr_all_norm: + result_files.append(raw_path) + for raw_path in xise_tb: + abs_path = xise_tb_abs.get(raw_path) + if abs_path and os.path.normcase(abs_path) in syr_all_norm: + tb_files.append(raw_path) + + # 第二阶段：尾部组件匹配（补配因绝对/相对路径差异导致未匹配的文件） + # 注意：syr_all 必须包含 syr_failed 中的原始路径 —— + # syr 里来自其他电脑的绝对路径 resolve 失败后进了 syr_failed， + # 但它们的尾部仍然能和 xise 相对路径匹配上，必须参与比较 + xise_remaining = [f for f in xise_result if f not in result_files] + xise_tb_remaining = [f for f in xise_tb if f not in tb_files] + + if xise_remaining or xise_tb_remaining: + syr_all = syr_result + syr_tb + syr_failed + tail_matched = [] + matched_syr_failed = set() + for raw_path in xise_remaining: + for syr_path in syr_all: + if paths_match_tail(raw_path, syr_path): + result_files.append(raw_path) + tail_matched.append(raw_path) + if syr_path in syr_failed: + matched_syr_failed.add(syr_path) + break + for raw_path in xise_tb_remaining: + for syr_path in syr_all: + if paths_match_tail(raw_path, syr_path): + tb_files.append(raw_path) + tail_matched.append(raw_path) + if syr_path in syr_failed: + matched_syr_failed.add(syr_path) + break + if tail_matched: + print(f"尾部匹配补配 {len(tail_matched)} 个文件（绝对/相对路径差异）") + + # 已匹配的 syr 路径从失败列表中移除，避免误导 + failed_files = xise_failed + [f for f in syr_failed if f not in matched_syr_failed] + + print(f"\n交集后保留 {len(result_files)} 个非testbench文件") + print(f"交集后保留 {len(tb_files)} 个testbench文件") + else: + result_files = xise_result + tb_files = xise_tb + failed_files = xise_failed + print("项目根目录未找到 .syr 文件，直接使用 .xise 结果") + + if failed_files: + print(f"未能找到 {len(failed_files)} 个文件") + + # 用 xise 侧映射重建绝对路径用于复制（xise/syr 中的绝对路径可能来自其他电脑，不可信） + def _resolve_xise(raw_path, abs_map): + if raw_path in abs_map: + return abs_map[raw_path] + # 兜底：直接用 project_root 拼接 + return os.path.normpath(os.path.join(project_root, raw_path.replace("\\", "/"))) + + result_files_abs = [_resolve_xise(f, xise_abs_map) for f in result_files] + tb_files_abs = [_resolve_xise(f, xise_tb_abs) for f in tb_files] + + # 合并带 标签的文件（始终保留） + for raw_path in xise_library: + abs_path = _resolve_xise(raw_path, xise_library_abs) + if abs_path not in result_files_abs and abs_path not in tb_files_abs: + result_files_abs.append(abs_path) + + _copy_extracted_files(result_files_abs, tb_files_abs, failed_files) + + +# ================================================= +# ISE (.syr) 解析 +# ================================================= + +SYR_PATTERN = re.compile(r'Compiling\s+\w+\s+file\s+"([^"]+)"', re.IGNORECASE) + + +def paths_match_tail(path_a, path_b): + """ + 判断两个路径的尾部组件是否匹配。 + 将路径拆分为组件列表，检查较短列表是否为较长列表的后缀。 + 无论绝对/相对路径、正斜杠/反斜杠、盘符差异，都能正确匹配。 + + 例: ../src/pro/xxx.v vs C:/Users/.../src/pro/xxx.v → 匹配（尾部 src/pro/xxx.v 相同） + ./xxx.v vs F:/project/xxx.v → 匹配 + xxx.v vs F:/project/xxx.v → 匹配 + """ + def _normalize_parts(p): + p = p.replace("\\", "/").lower() + if len(p) >= 2 and p[1] == ":": + p = p[2:] + while p.startswith("../"): + p = p[3:] + while p.startswith("./"): + p = p[2:] + p = p.strip("/") + return p.split("/") if p else [] + + parts_a = _normalize_parts(path_a) + parts_b = _normalize_parts(path_b) + + if not parts_a or not parts_b: + return False + + if len(parts_a) <= len(parts_b): + return parts_a == parts_b[-len(parts_a):] + else: + return parts_b == parts_a[-len(parts_b):] + + +def resolve_syr_path(extracted_path, project_root): + """ + 从 .syr 中提取的路径解析为真实绝对路径 + 支持绝对路径 / 相对路径 / 纯文件名 + """ + extracted_path = extracted_path.replace("\\", "/").strip() + + if os.path.isabs(extracted_path): + if os.path.exists(extracted_path): + return os.path.normpath(extracted_path) + filename = os.path.basename(extracted_path) + if os.path.exists(os.path.join(project_root, filename)): + return os.path.normpath(os.path.join(project_root, filename)) + + # 相对路径：和 xise 一样用 os.path.join + normpath，保留完整目录结构 + real_path = os.path.normpath(os.path.join(project_root, extracted_path)) + if os.path.exists(real_path): + return real_path + + # 回退：用文件名模糊搜索 + tail = os.path.basename(extracted_path) + return find_file_by_tail(project_root, tail) + + +def _parse_syr(syr_path, config_path, project_root): + """ + 从 .syr 综合报告中解析源文件，返回 (result_files, tb_files, failed_files) + 不执行复制，供内部调用做交集等操作 + """ + include_exts = load_extensions(config_path) + + result_files = [] + tb_files = [] + failed_files = [] + seen_paths = set() + + with open(syr_path, "r", encoding="utf-8", errors="ignore") as f: + for line in f: + matches = SYR_PATTERN.findall(line) + for extracted_path in matches: + if extracted_path in seen_paths: + continue + seen_paths.add(extracted_path) + + suffix = Path(extracted_path).suffix.lower() + if include_exts and suffix not in include_exts: + continue + + is_tb = is_testbench_filename(extracted_path) + + real_path = resolve_syr_path(extracted_path, project_root) + if real_path is not None and os.path.exists(real_path): + if is_tb: + tb_files.append(real_path) + else: + result_files.append(real_path) + else: + failed_files.append(extracted_path) + + return result_files, tb_files, failed_files + + +def extract_from_syr_and_copy(syr_path, config_path, project_root): + """ + 从 .syr 综合报告中解析源文件并复制 + 匹配模式: Compiling vhdl file "path/to/file.vhd" in Library work + """ + result_files, tb_files, failed_files = _parse_syr(syr_path, config_path, project_root) + + print(f"解析并定位到 {len(result_files)} 个非testbench文件") + print(f"解析并定位到 {len(tb_files)} 个testbench文件") + if failed_files: + print(f"未能找到 {len(failed_files)} 个文件") + + _copy_extracted_files(result_files, tb_files, failed_files) + + +# ================================================= +# main +# ================================================= + +if __name__ == "__main__": + try: + PROJECT_ROOT = get_project_root() + if not os.path.isdir(PROJECT_ROOT): + raise RuntimeError(f"PROJECT_ROOT 不存在: {PROJECT_ROOT}") + + config_file = os.path.join(os.getcwd(), "config.txt") + if not os.path.exists(config_file): + raise FileNotFoundError("当前目录下未找到 config.txt") + + print(f"使用 config 文件: {config_file}") + print(f"项目根目录 : {PROJECT_ROOT}") + + # 优先级: .xpr → .xise → .syr + xpr_file = find_latest_xpr_in_dir(PROJECT_ROOT) + if xpr_file: + print(f"使用 xpr 文件 : {xpr_file}") + extract_from_xpr_and_copy(xpr_file, config_file, PROJECT_ROOT) + else: + xise_files = find_all_files_in_dir(PROJECT_ROOT, ".xise") + if xise_files: + chosen_xise = user_select_file(xise_files, ".xise") + print(f"使用 xise 文件 : {chosen_xise}") + extract_from_xise_and_copy(chosen_xise, config_file, PROJECT_ROOT) + else: + syr_files = find_all_files_in_dir(PROJECT_ROOT, ".syr") + if syr_files: + chosen_syr = user_select_file(syr_files, ".syr") + print(f"使用 syr 文件 : {chosen_syr}") + extract_from_syr_and_copy(chosen_syr, config_file, PROJECT_ROOT) + else: + print("当前项目下没有能提取源代码的文件依据") + + except Exception as e: + print("程序执行失败:") + print(e) + + finally: + input("\n按回车键关闭窗口...") \ No newline at end of file diff --git a/杂交版/源代码提取/config.txt b/杂交版/源代码提取/config.txt new file mode 100644 index 0000000..4f206eb --- /dev/null +++ b/杂交版/源代码提取/config.txt @@ -0,0 +1,6 @@ +# 支持的文件类型（不区分大小写） +# 每行一个后缀 +.v +.vhd +.vh +.vhdl \ No newline at end of file diff --git a/杂交版/源代码提取/使用说明.md b/杂交版/源代码提取/使用说明.md new file mode 100644 index 0000000..09a4f87 --- /dev/null +++ b/杂交版/源代码提取/使用说明.md @@ -0,0 +1,22 @@ +1. 在 `config.txt` 中配置**需要提取的文件后缀**（每行一个），例如： +``` +.v +.vhd +.vh +.vhdl +``` + +2. 运行脚本： +``` +双击 源代码提取.exe +将源代码所在项目的根目录路径输入到窗口，点击回车 (等待结果) +**项目根目录下必须要有 `.xpr` / `.xise` / `.syr` 其中之一才能提取**。 + +!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! 若项目为ise项目，根据.syr项目提取出的源代码可能包含IP文件,需要人工进行辨别 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + +!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! 若项目为ise项目，根据.syr项目提取出的源代码可能包含IP文件,需要人工进行辨别 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + +!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! 若项目为ise项目，根据.syr项目提取出的源代码可能包含IP文件,需要人工进行辨别 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + +若项目根目录存在多个.xise或.syr文件，用户需要根据窗口提示选择正确的一个 +``` \ No newline at end of file diff --git a/杂交版/源代码提取/源代码提取.exe b/杂交版/源代码提取/源代码提取.exe new file mode 100644 index 0000000..0f7ab9e Binary files /dev/null and b/杂交版/源代码提取/源代码提取.exe differ