242 lines
12 KiB
Plaintext
242 lines
12 KiB
Plaintext
*** Variables ***
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${URI} @https://dl.antmicro.com/projects/renode
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${FASTVDMA_SOCKET_LINUX} ${URI}/Vfastvdma-Linux-x86_64-12904733885-s_1651016-da5e31f75673a48f4d6fbaa5b5f21fd9190df393
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${FASTVDMA_SOCKET_WINDOWS} ${URI}/Vfastvdma-Windows-x86_64-12904733885.exe-s_3259432-da445f10460a1d6f48d470a5c631e6339a589190
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${FASTVDMA_SOCKET_MACOS} ${URI}/Vfastvdma-macOS-x86_64-12904733885-s_239216-3c4f0c697d39916c5fc14ee560385336b4fcc062
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${FASTVDMA_NATIVE_LINUX} ${URI}/libVfastvdma-Linux-x86_64-12904733885.so-s_2104432-8ec57bdee00c76a044024158525d4130af0afc1a
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${FASTVDMA_NATIVE_WINDOWS} ${URI}/libVfastvdma-Windows-x86_64-12904733885.dll-s_3265828-0e1691527cfb633cf5d8865f3445529708e73f8f
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${FASTVDMA_NATIVE_MACOS} ${URI}/libVfastvdma-macOS-x86_64-12904733885.dylib-s_239144-ebd397eb4d74c08be26cec08c022e90b78f0e020
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${RAM_SOCKET_LINUX} ${URI}/Vram-Linux-x86_64-12904733885-s_1634672-820a0d6d950a74702808d07ad15a7f8a48f86fe0
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${RAM_SOCKET_WINDOWS} ${URI}/Vram-Windows-x86_64-12904733885.exe-s_3245365-7151d2803f710e3f411483352aa822f63a3f405a
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${RAM_SOCKET_MACOS} ${URI}/Vram-macOS-x86_64-12904733885-s_222840-ef7dd5bc27d5e7b13d0444491f2f1f0fb252052e
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${RAM_NATIVE_LINUX} ${URI}/libVram-Linux-x86_64-12904733885.so-s_2088056-004e8ca045d4505d42f552b12f0408c9eb951e8a
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${RAM_NATIVE_WINDOWS} ${URI}/libVram-Windows-x86_64-12904733885.dll-s_3252274-06f5f9b70593f9d57546c9be97791d70c9762129
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${RAM_NATIVE_MACOS} ${URI}/libVram-macOS-x86_64-12904733885.dylib-s_222776-56574ab2821c56a41486c0233d494d7e841c57df
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${MAIN_LISTEN_PORT} 3335
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${ASYNC_LISTEN_PORT} 3336
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*** Keywords ***
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Create Machine
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[Arguments] ${use_socket} ${custom_ports}=False
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IF ${use_socket}
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Set Test Variable ${dma_args} ; address: "127.0.0.1"
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Set Test Variable ${fastvdma_linux} ${FASTVDMA_SOCKET_LINUX}
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Set Test Variable ${fastvdma_windows} ${FASTVDMA_SOCKET_WINDOWS}
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Set Test Variable ${fastvdma_macos} ${FASTVDMA_SOCKET_MACOS}
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Set Test Variable ${mem_args} ; address: "127.0.0.1"
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Set Test Variable ${ram_linux} ${RAM_SOCKET_LINUX}
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Set Test Variable ${ram_windows} ${RAM_SOCKET_WINDOWS}
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Set Test Variable ${ram_macos} ${RAM_SOCKET_MACOS}
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ELSE
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${dma_args}= Evaluate ""
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Set Test Variable ${fastvdma_linux} ${FASTVDMA_NATIVE_LINUX}
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Set Test Variable ${fastvdma_windows} ${FASTVDMA_NATIVE_WINDOWS}
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Set Test Variable ${fastvdma_macos} ${FASTVDMA_NATIVE_MACOS}
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${mem_args}= Evaluate ""
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Set Test Variable ${ram_linux} ${RAM_NATIVE_LINUX}
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Set Test Variable ${ram_windows} ${RAM_NATIVE_WINDOWS}
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Set Test Variable ${ram_macos} ${RAM_NATIVE_MACOS}
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END
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Execute Command using sysbus
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Execute Command mach create
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Execute Command machine LoadPlatformDescriptionFromString 'cpu: CPU.RiscV32 @ sysbus { cpuType: "rv32imaf"; timeProvider: empty }'
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IF ${custom_ports}
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Execute Command machine LoadPlatformDescriptionFromString 'dma: CoSimulated.CoSimulatedPeripheral @ sysbus <0x10000000, +0x100> { frequency: 100000; limitBuffer: 10000; timeout: 240000 ${dma_args}; mainListenPort: ${MAIN_LISTEN_PORT}; asyncListenPort: ${ASYNC_LISTEN_PORT} }'
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ELSE
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Execute Command machine LoadPlatformDescriptionFromString 'dma: CoSimulated.CoSimulatedPeripheral @ sysbus <0x10000000, +0x100> { frequency: 100000; limitBuffer: 10000; timeout: 240000 ${dma_args} }'
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END
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Execute Command machine LoadPlatformDescriptionFromString 'mem: CoSimulated.CoSimulatedPeripheral @ sysbus <0x20000000, +0x100000> { frequency: 100000; limitBuffer: 10000; timeout: 240000 ${mem_args} }'
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Execute Command machine LoadPlatformDescriptionFromString 'ram: Memory.MappedMemory @ sysbus 0xA0000000 { size: 0x06400000 }'
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Execute Command sysbus WriteDoubleWord 0xA2000000 0x10500073 # wfi
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Execute Command cpu PC 0xA2000000
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Execute Command dma SimulationFilePathLinux ${fastvdma_linux}
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Execute Command dma SimulationFilePathWindows ${fastvdma_windows}
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Execute Command dma SimulationFilePathMacOS ${fastvdma_macos}
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Execute Command mem SimulationFilePathLinux ${ram_linux}
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Execute Command mem SimulationFilePathWindows ${ram_windows}
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Execute Command mem SimulationFilePathMacOS ${ram_macos}
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Transaction Should Finish
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${val} = Execute Command dma ReadDoubleWord 0x4
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Should Contain ${val} 0x00000000
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Prepare Data
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[Arguments] ${addr}
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# dummy data for verification
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${addr} = Evaluate ${addr} + 0x0
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Execute Command sysbus WriteDoubleWord ${addr} 0xDEADBEA7
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${addr} = Evaluate ${addr} + 0x4
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Execute Command sysbus WriteDoubleWord ${addr} 0xDEADC0DE
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${addr} = Evaluate ${addr} + 0x4
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Execute Command sysbus WriteDoubleWord ${addr} 0xCAFEBABE
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${addr} = Evaluate ${addr} + 0x4
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Execute Command sysbus WriteDoubleWord ${addr} 0x5555AAAA
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Configure DMA
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[Arguments] ${src}
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... ${dst}
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# reader start address
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Execute Command dma WriteDoubleWord 0x10 ${src}
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# reader line length in 32-bit words
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Execute Command dma WriteDoubleWord 0x14 1024
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# number of lines to read
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Execute Command dma WriteDoubleWord 0x18 1
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# stride size between consecutive lines in 32-bit words
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Execute Command dma WriteDoubleWord 0x1c 0
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# writer start address
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Execute Command dma WriteDoubleWord 0x20 ${dst}
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# writer line length in 32-bit words
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Execute Command dma WriteDoubleWord 0x24 1024
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# number of lines to write
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Execute Command dma WriteDoubleWord 0x28 1
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# stride size between consecutive lines in 32-bit words
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Execute Command dma WriteDoubleWord 0x2c 0
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# do not wait fo external synchronization signal
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Execute Command dma WriteDoubleWord 0x00 0x0f
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Ensure Memory Is Clear
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[Arguments] ${periph}
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# Verify that there are 0's under the writer start address before starting the transaction
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Memory Should Contain ${periph} 0x0 0x00000000
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Memory Should Contain ${periph} 0x4 0x00000000
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Memory Should Contain ${periph} 0x8 0x00000000
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Memory Should Contain ${periph} 0xC 0x00000000
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Ensure Memory Is Written
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[Arguments] ${periph}
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# Verify data after the transaction
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Memory Should Contain ${periph} 0x0 0xDEADBEA7
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Memory Should Contain ${periph} 0x4 0xDEADC0DE
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Memory Should Contain ${periph} 0x8 0xCAFEBABE
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Memory Should Contain ${periph} 0xC 0x5555AAAA
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Memory Should Contain
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[Arguments] ${periph}
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... ${addr}
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... ${val}
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${res}= Execute Command ${periph} ReadDoubleWord ${addr}
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Should Contain ${res} ${val}
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Test Read Write Co-simulated Memory
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Ensure Memory Is Clear mem
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# Write to memory
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Prepare Data 0x20000000
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Ensure Memory Is Written mem
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Test DMA Transaction From Mapped Memory to Mapped Memory
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Prepare Data 0xA1000000
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Configure DMA 0xA1000000 0xA0000000
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Ensure Memory Is Clear ram
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Execute Command emulation RunFor "00:00:10.000000"
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Transaction Should Finish
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Ensure Memory Is Written ram
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Test DMA Transaction From Mapped Memory to Co-simulated Memory
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Prepare Data 0xA1000000
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Configure DMA 0xA1000000 0x20000000
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Ensure Memory Is Clear mem
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Execute Command emulation RunFor "00:00:10.000000"
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Transaction Should Finish
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Ensure Memory Is Written mem
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Test DMA Transaction From Co-simulated Memory to Mapped Memory
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Prepare Data 0x20080000
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Configure DMA 0x20080000 0xA0000000
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Ensure Memory Is Clear ram
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Execute Command emulation RunFor "00:00:10.000000"
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Transaction Should Finish
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Ensure Memory Is Written ram
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Test DMA Transaction From Co-simulated Memory to Co-simulated Memory
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Prepare Data 0x20080000
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Configure DMA 0x20080000 0x20000000
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Ensure Memory Is Clear mem
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Execute Command emulation RunFor "00:00:10.000000"
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Transaction Should Finish
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Ensure Memory Is Written mem
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*** Test Cases ***
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Should Read Write Co-simulated Memory Using Socket
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[Tags] skip_host_arm
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Create Machine True
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Test Read Write Co-simulated Memory
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Should Read Write Co-simulated Memory Using Socket With Custom Ports
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[Tags] skip_host_arm
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Create Machine True True
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Test Read Write Co-simulated Memory
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Should Run DMA Transaction From Mapped Memory to Mapped Memory Using Socket
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[Tags] skip_host_arm
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Create Machine True
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Test DMA Transaction From Mapped Memory to Mapped Memory
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Should Run DMA Transaction From Mapped Memory to Co-simulated Memory Using Socket
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[Tags] skip_host_arm
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Create Machine True
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Test DMA Transaction From Mapped Memory to Co-simulated Memory
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Should Run DMA Transaction From Co-simulated Memory to Mapped Memory Using Socket
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[Tags] skip_host_arm
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Create Machine True
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Test DMA Transaction From Co-simulated Memory to Mapped Memory
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Should Run DMA Transaction From Co-simulated Memory to Co-simulated Memory Using Socket
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[Tags] skip_host_arm
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Create Machine True
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Test DMA Transaction From Co-simulated Memory to Co-simulated Memory
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Should Read Write Co-simulated Memory
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[Tags] skip_osx skip_host_arm
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Create Machine False
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Test Read Write Co-simulated Memory
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Should Run DMA Transaction From Mapped Memory to Mapped Memory
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[Tags] skip_osx skip_host_arm
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Create Machine False
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Test DMA Transaction From Mapped Memory to Mapped Memory
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Should Run DMA Transaction From Mapped Memory to Co-simulated Memory
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[Tags] skip_osx skip_host_arm
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Create Machine False
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Test DMA Transaction From Mapped Memory to Co-simulated Memory
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Should Run DMA Transaction From Co-simulated Memory to Mapped Memory
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[Tags] skip_osx skip_host_arm
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Create Machine False
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Test DMA Transaction From Co-simulated Memory to Mapped Memory
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Should Run DMA Transaction From Co-simulated Memory to Co-simulated Memory
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[Tags] skip_osx skip_host_arm
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Create Machine False
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Test DMA Transaction From Co-simulated Memory to Co-simulated Memory
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