182 lines
8.2 KiB
Plaintext
182 lines
8.2 KiB
Plaintext
*** Variables ***
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${starting_pc} 0x1000
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${pc_in_loop} 0x1004
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${emulation_time} "0.00002"
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# Platform definitions
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${PLAT_ARM64} SEPARATOR=\n """
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... cpu: CPU.ARMv8A @ sysbus
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... ${SPACE*4}cpuType: "cortex-a53"
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... ${SPACE*4}genericInterruptController: gic
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...
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... gic: IRQControllers.ARM_GenericInterruptController
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... ${SPACE*4}architectureVersion: .GICv2
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... """
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${PLAT_ARMv8R} SEPARATOR=\n """
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... cpu: CPU.ARMv8R @ sysbus
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... ${SPACE*4}cpuType: "cortex-r52"
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... ${SPACE*4}genericInterruptController: gic
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...
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... gic: IRQControllers.ARM_GenericInterruptController
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... """
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${PLAT_ARM-M} SEPARATOR=\n """
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... cpu: CPU.CortexM @ sysbus
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... ${SPACE*4}cpuType: "cortex-m7"
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... ${SPACE*4}nvic: nvic
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...
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... nvic: IRQControllers.NVIC
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... """
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${PLAT_X86} SEPARATOR=\n """
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... cpu: CPU.X86 @ sysbus
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... ${SPACE*4}cpuType: "x86"
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... ${SPACE*4}lapic: lapic
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...
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... lapic: IRQControllers.LAPIC @ sysbus 0xFEE00000
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... """
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${PLAT_SPARC} "cpu: CPU.Sparc @ sysbus { cpuType: \\"leon3\\" }"
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${PLAT_POWERPC} "cpu: CPU.PowerPc @ sysbus { cpuType: \\"e200z6\\" }"
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${PLAT_ARM} 'cpu: CPU.ARMv7R @ sysbus { cpuType: "cortex-r8"}'
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${PLAT_RISCV} 'cpu: CPU.RiscV32 @ sysbus { cpuType: "rv32i"}'
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${PLAT_XTENSA} 'cpu: CPU.Xtensa @ sysbus { cpuType: "sample_controller"}'
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# Test programs for each architecture
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${PROG_RISCV} SEPARATOR=\n
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... loop:
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... nop
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... nop
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... nop
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... jal loop
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${PROG_ARM} SEPARATOR=\n
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... loop:
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... nop
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... nop
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... nop
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... b loop
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${PROG_X86} SEPARATOR=\n
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... loop:
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... nop
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... nop
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... nop
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... nop
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... jmp loop
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${PROG_SPARC} SEPARATOR=\n
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... loop:
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... nop
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... nop
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... nop
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... nop
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... bg loop
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... nop
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${PROG_POWERPC} SEPARATOR=\n
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... loop:
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... nop
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... nop
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... nop
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... nop
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... b loop
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*** Keywords ***
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Create Machine
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[Arguments] ${PLAT} ${PROG}
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Execute Command using sysbus
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Execute Command mach create
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Execute Command machine LoadPlatformDescriptionFromString ${PLAT}
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Configure Machine
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Execute Command sysbus.cpu AssembleBlock ${starting_pc} "${PROG}"
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Create Machine Xtensa
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Execute Command using sysbus
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Execute Command mach create
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Execute Command machine LoadPlatformDescriptionFromString ${PLAT_XTENSA}
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Configure Machine
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# renode-llvm-disas doesnt support Xtensa yet so the program has to be written directly to memory
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# nops
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Execute Command sysbus WriteWord 0x1000 0xF03D
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Execute Command sysbus WriteWord 0x1002 0xF03D
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Execute Command sysbus WriteWord 0x1004 0xF03D
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Execute Command sysbus WriteWord 0x1006 0xF03D
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Execute Command sysbus WriteWord 0x1008 0xF03D
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Execute Command sysbus WriteWord 0x100a 0xF03D
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# jmp back to 0x1000
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Execute Command sysbus WriteDoubleWord 0x100c 0x00FFFC06
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Configure Machine
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Execute Command machine LoadPlatformDescriptionFromString 'mem: Memory.MappedMemory @ sysbus 0x1000 { size: 0x1000000 }'
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Execute Command cpu PerformanceInMips 1
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# Needed to check PC between the blocks on a hook
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Execute Command cpu MaximumBlockSize 1
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Execute Command cpu SetHookAtBlockBegin "self.DebugLog('block started: ' + 'PC '+ str(self.PC))"
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Execute Command cpu ChainingEnabled True
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Create Log Tester 0.01 defaultPauseEmulation=true
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Execute Command logLevel -1
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Syncing Enabled Template
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[Arguments] ${PLAT} ${PROG}
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Create Machine ${PLAT} ${PROG}
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Test SyncPCEveryInstructionDisabled False
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Syncing Disabled Template
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[Arguments] ${PLAT} ${PROG}
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Create Machine ${PLAT} ${PROG}
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Test SyncPCEveryInstructionDisabled True
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# Tests run a loop of nops, after first loop translation blocks should be chained, then a hook can verify that the PC is updated between the blocks
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Test SyncPCEveryInstructionDisabled True
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Execute Command cpu PC ${starting_pc}
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Execute Command cpu SyncPCEveryInstructionDisabled true
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Execute Command emulation RunFor ${emulation_time}
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# wait for first loop
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Wait For Log Entry block started: PC ${pc_in_loop} timeout=0
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# after chaining we should expect wrong PC
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Run Keyword And Expect Error
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... *KeywordException: Expected pattern "block started: PC ${pc_in_loop}" did not appear in the log*
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... Wait For Log Entry block started: PC ${pc_in_loop} timeout=0
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# This test checks for an unwanted behavior
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Test SyncPCEveryInstructionDisabled False
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Execute Command cpu PC ${starting_pc}
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Execute Command cpu SyncPCEveryInstructionDisabled false
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Execute Command emulation RunFor ${emulation_time}
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# wait for first loop
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Wait For Log Entry block started: PC ${pc_in_loop} timeout=0
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# after chaining we still expect PC from inside loop
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Wait For Log Entry block started: PC ${pc_in_loop} timeout=0
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*** Test Cases ***
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Should Report Wrong PC Between Chained Blocks
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[Template] Syncing Disabled Template
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${PLAT_ARM} ${PROG_ARM}
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${PLAT_ARM64} ${PROG_ARM}
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${PLAT_ARMv8R} ${PROG_ARM}
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${PLAT_ARM-M} ${PROG_ARM}
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${PLAT_POWERPC} ${PROG_POWERPC}
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${PLAT_SPARC} ${PROG_SPARC}
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# PC is already updated between instructions for RISC-V, Xtensa and X86
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Should Report Correct PC Between Chained Blocks
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[Template] Syncing Enabled Template
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${PLAT_RISCV} ${PROG_RISCV}
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${PLAT_ARM} ${PROG_ARM}
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${PLAT_ARM64} ${PROG_ARM}
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${PLAT_ARMv8R} ${PROG_ARM}
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${PLAT_ARM-M} ${PROG_ARM}
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${PLAT_POWERPC} ${PROG_POWERPC}
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${PLAT_X86} ${PROG_X86}
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${PLAT_SPARC} ${PROG_SPARC}
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# Separate path for Xtensa as it's currently not supported by Renode's LLVM assembly
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Should Report Correct PC Between Chained Blocks Xtensa
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Create Machine Xtensa
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Test SyncPCEveryInstructionDisabled False
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