89 lines
3.9 KiB
Plaintext
89 lines
3.9 KiB
Plaintext
*** Variables ***
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${start_pc} 0x2000
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${trap_address} 0x4000
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${unimp_op} 0xC0001073 # CSRRW 0x, cycle, x0. Since cycle is read only, triggers illegal instruction exception
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${mret} 0x30200073 # mret
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${user_level} 0b0
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${machine_level} 0b11
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${invalidate_test_plat} SEPARATOR=\n """
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... cpu: CPU.RiscV32 @ sysbus
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... ${SPACE*4}cpuType: "rv32im_zicsr"
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...
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... ram: Memory.MappedMemory @ sysbus 0x10000
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... ${SPACE*4}size: 0x8000
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...
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... forbidden: Memory.MappedMemory @ sysbus 0x2000
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... ${SPACE*4}size: 0x2000
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... """
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${invalidate_test_elf} https://dl.antmicro.com/projects/renode/riscv-mret-test.elf-s_13308-257bec1c8918772e95eb9fdc1a432c852f052f99
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*** Keywords ***
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Create Machine
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[Arguments] ${bitness} ${privilege}
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Execute Command using sysbus
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Execute Command mach create "risc-v"
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Execute Command machine LoadPlatformDescriptionFromString "clint: IRQControllers.CoreLevelInterruptor @ sysbus 0x44000000 { frequency: 66000000 }"
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Execute Command machine LoadPlatformDescriptionFromString "cpu: CPU.RiscV${bitness} @ sysbus { timeProvider: clint; cpuType: \\"rv${bitness}gc\\"; privilegeLevels: ${privilege}; interruptMode: 1 }"
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Execute Command machine LoadPlatformDescriptionFromString "mem: Memory.MappedMemory @ sysbus 0x1000 { size: 0x40000 }"
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Execute Command cpu PC ${start_pc}
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Execute Command cpu MTVEC ${trap_address}
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Execute Command sysbus WriteDoubleWord ${start_pc} ${unimp_op}
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Execute Command sysbus WriteDoubleWord ${trap_address} ${mret}
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MPP Should Equal
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[Arguments] ${expected}
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${mstatus}= Execute Command cpu MSTATUS
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${mpp}= Evaluate (${mstatus.strip()} & (0b11 << 11)) >> 11
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Should Be Equal As numbers ${mpp} ${expected}
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Test Mret
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[Arguments] ${lowest_priv_level}
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Execute Command cpu Step
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MPP Should Equal 0b11 # Machine Level
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${pc}= Execute Command cpu PC
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Should Be Equal As Numbers ${pc} 0x4000
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Execute Command cpu Step
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${pc}= Execute Command cpu PC
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Should Be Equal As Numbers ${pc} 0x2000
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MPP Should Equal ${lowest_priv_level}
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*** Test Cases ***
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User Level Exists 64Bits
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Create Machine bitness=64 privilege=PrivilegeLevels.MachineUser
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Test Mret ${user_level}
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User Level Exists 32Bits
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Create Machine bitness=32 privilege=PrivilegeLevels.MachineUser
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Test Mret ${user_level}
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User Level Does Not Exists 64Bits
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Create Machine bitness=64 privilege=PrivilegeLevels.Machine
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Test Mret ${machine_level}
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User Level Does Not Exists 32Bits
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Create Machine bitness=32 privilege=PrivilegeLevels.Machine
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Test Mret ${machine_level}
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Should Invalidate TLB After Mode Change
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Execute Command mach create
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Execute Command machine LoadPlatformDescriptionFromString ${invalidate_test_plat}
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Execute Command sysbus LoadELF @${invalidate_test_elf}
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Execute Command cpu LogFunctionNames true
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Create Log Tester 1
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Register Failing Log String Entering function fail_loop
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Wait For Log Entry Entering function unrecoverable
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