67 lines
3.1 KiB
Plaintext
67 lines
3.1 KiB
Plaintext
*** Variables ***
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${SHARED_ADDRESS} 0x81000000
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${PC} 0x80000000
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${VARIABLE_VALUE} 0x5
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${NEW_VARIABLE_VALUE} 0xbeeeeeef
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# Registers used
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${a0} 10
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${a1} 11
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${a2} 12
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${a3} 13
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*** Keywords ***
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Add CPU ${core}
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[Arguments] ${value}
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Execute Command machine LoadPlatformDescriptionFromString "cpu_${core}: CPU.RiscV64 @ sysbus { timeProvider: empty; cpuType: \\"rv64gc\\"}"
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Execute Command cpu_${core} ExecutionMode SingleStep
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Execute Command cpu_${core} PC ${PC}
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Execute Command cpu_${core} SetRegister ${a0} ${SHARED_ADDRESS}
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Execute Command cpu_${core} SetRegister ${a2} ${value}
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*** Test Cases ***
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Should Register HST For Both CPUs When Second CPU Is Added
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# Create a very simple machine
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Execute Command mach create
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Execute Command machine LoadPlatformDescriptionFromString "ddr: Memory.MappedMemory @ sysbus 0x80000000 { size: 0x80000000 }"
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Create Log Tester 0
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Execute Command logLevel 0
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# Just in case check if store table is not allocated nor initialized at machine creation
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Should Not Be In Log Allocating store table with size
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Should Not Be In Log initialize_store_table: initializing with ptr
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# Add first CPU
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Add CPU 0 ${NEW_VARIABLE_VALUE}
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# Check if store table is not allocated nor initialized for one CPU
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Should Not Be In Log Allocating store table with size
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Should Not Be In Log initialize_store_table: initializing with ptr
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# Add second CPU
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Add CPU 1 ${VARIABLE_VALUE}
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# Now store table should be allocated
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Wait For Log Entry Store table allocated
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# Both cores should get pointers to the store table
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Wait For Log Entry cpu_0: initialize_store_table: initializing with ptr
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Wait For Log Entry cpu_1: initialize_store_table: initializing with ptr
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# Assemble LR/SC code
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${code}= catenate SEPARATOR=${\n}
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... lr.d a1, (a0);
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... sc.d a3, a2, (a0);
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Execute Command cpu_0 AssembleBlock ${PC} """${code}"""
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# Now check if store table is properly registered for cpu_0
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Execute Command sysbus WriteQuadWord ${SHARED_ADDRESS} ${VARIABLE_VALUE}
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Execute Command cpu_0 Step # LR
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Execute Command cpu_1 Step 2 # write
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Execute Command cpu_0 Step # SC
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# Check for SC failure.
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${value}= Execute Command sysbus ReadQuadWord ${SHARED_ADDRESS}
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Should Not Be Equal As Integers ${value} ${NEW_VARIABLE_VALUE} Expected value at ${SHARED_ADDRESS} to not be ${NEW_VARIABLE_VALUE} after interleaving LR/SC
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Register Should Be Equal ${a3} 1 cpuName=cpu_0
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