120 lines
3.0 KiB
Plaintext
120 lines
3.0 KiB
Plaintext
e51: CPU.RiscV64 @ sysbus
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cpuType: "rv64imac_zicsr_zifencei"
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hartId: 0
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privilegedArchitecture: PrivilegedArchitecture.Priv1_10
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timeProvider: clint
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u54_1: CPU.RiscV64 @ sysbus
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cpuType: "rv64gc_zicsr_zifencei"
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hartId: 1
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privilegedArchitecture: PrivilegedArchitecture.Priv1_10
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timeProvider: clint
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u54_2: CPU.RiscV64 @ sysbus
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cpuType: "rv64gc_zicsr_zifencei"
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hartId: 2
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privilegedArchitecture: PrivilegedArchitecture.Priv1_10
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timeProvider: clint
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u54_3: CPU.RiscV64 @ sysbus
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cpuType: "rv64gc_zicsr_zifencei"
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hartId: 3
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privilegedArchitecture: PrivilegedArchitecture.Priv1_10
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timeProvider: clint
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u54_4: CPU.RiscV64 @ sysbus
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cpuType: "rv64gc_zicsr_zifencei"
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hartId: 4
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privilegedArchitecture: PrivilegedArchitecture.Priv1_10
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timeProvider: clint
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debug: Memory.MappedMemory @sysbus 0x0
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size: 0x1000
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e51DTim: Memory.MappedMemory @ sysbus 0x01000000
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size: 0x2000
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u54Hart1ITim: Memory.MappedMemory @ sysbus 0x01808000
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size: 0x7000
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u54Hart2ITim: Memory.MappedMemory @ sysbus 0x01810000
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size: 0x7000
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u54Hart3ITim: Memory.MappedMemory @ sysbus 0x01818000
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size: 0x7000
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u54Hart4ITim: Memory.MappedMemory @ sysbus 0x01820000
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size: 0x7000
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clint: IRQControllers.CoreLevelInterruptor @ sysbus 0x2000000
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frequency: 1000000
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numberOfTargets: 5
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[0, 1] -> e51@[3, 7]
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[2, 3] -> u54_1@[3, 7]
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[4, 5] -> u54_2@[3, 7]
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[6, 7] -> u54_3@[3, 7]
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[8, 9] -> u54_4@[3, 7]
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plic: IRQControllers.PlatformLevelInterruptController @ sysbus 0xc000000
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0 -> e51@11
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[1,2] -> u54_1@[11,9]
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[3,4] -> u54_2@[11,9]
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[5,6] -> u54_3@[11,9]
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[7,8] -> u54_4@[11,9]
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numberOfSources: 53
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numberOfContexts: 9
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prioritiesEnabled : false
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uart0: UART.SiFive_UART @ sysbus 0x10010000
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IRQ -> plic@4
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uart1: UART.SiFive_UART @ sysbus 0x10011000
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IRQ -> plic@5
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gpio: GPIOPort.SiFive_GPIO @ sysbus 0x10060000
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qspi0Flash: Memory.MappedMemory @ sysbus 0x20000000
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size: 0x2000000
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ddr: Memory.MappedMemory @ sysbus 0x80000000
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size: 0x200000000
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ethernet: Network.CadenceGEM @ sysbus 0x10090000
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moduleRevision: 0x0109
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moduleId: 0x1007
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IRQ -> plic@53
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phy: Network.EthernetPhysicalLayer @ ethernet 0
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Id1: 0x0141
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Id2: 0x0e40
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BasicStatus: 0x62A4
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AutoNegotiationAdvertisement: 0x1e1
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AutoNegotiationLinkPartnerBasePageAbility: 0x1e1
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MasterSlaveControl: 0x300
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MasterSlaveStatus: 0x3000
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qspi0: SPI.HiFive_SPI @ sysbus 0x10040000
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IRQ -> plic@51
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numberOfSupportedSlaves: 1
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// The registration address value is taken from the device tree.
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// It is different in the documentation (0x10140000).
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qspi1: SPI.HiFive_SPI @ sysbus 0x10041000
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IRQ -> plic@52
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numberOfSupportedSlaves: 4
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qspi2: SPI.HiFive_SPI @ sysbus 0x10050000
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IRQ -> plic@6
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numberOfSupportedSlaves: 1
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i2c: I2C.OpenCoresI2C @ sysbus 0x10030000
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// our model does not support interrupts yet, but if it did:
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// IRQ -> plic@50
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pwm0: HiFive_PWM @ sysbus 0x10020000
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IRQ -> plic@42
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pwm1: HiFive_PWM @ sysbus 0x10021000
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IRQ -> plic@46
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