130 lines
5.8 KiB
Plaintext
130 lines
5.8 KiB
Plaintext
*** Settings ***
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Test Setup Create Machine
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Library Collections
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*** Variables ***
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${PLATFORM_PATH} ${CURDIR}${/}riscv-lr-sc-strong-atomicity.repl
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${ORDINARY_ADDRESS} 0x81000000
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${MMIO_ADDRESS} 0x00100000
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${VARIABLE_ADDRESS_CPU1} 0x81000000
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${VARIABLE_ADDRESS_CPU2} 0x81000100
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${CORE_0_PC} 0x80000000
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${CORE_1_PC} 0x80000100
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${VARIABLE_VALUE} 0x5
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${NEW_VARIABLE_VALUE} 0xbeeeeeef
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# Registers used
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${x0} 0
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${a0} 10
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${a1} 11
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${a2} 12
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${a3} 13
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${a4} 14
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*** Keywords ***
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Create Machine
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Execute Command mach create
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Execute Command machine LoadPlatformDescription "${PLATFORM_PATH}"
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Execute Command emulation SingleStepBlocking False
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Reset Program Counters
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Get Cpu On ${platform:(RV32|RV64)}
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${cpu}= Set variable if "${platform}" == "RV64"
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... cpu
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... cpu32
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[return] ${cpu}
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Get Native Access Width On ${platform:(RV32|RV64)}
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${width}= Set variable if "${platform}" == "RV64"
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... d
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... w
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[return] ${width}
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Get Supported Access Widths On ${platform:(RV32|RV64)}
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@{rv32_widths}= Create List b h w
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@{rv64_only_widths}= Create List d
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@{rv64_widths}= Combine Lists ${rv32_widths} ${rv64_only_widths}
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${widths}= Set variable if "${platform}" == "RV64"
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... ${rv64_widths}
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... ${rv32_widths}
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[return] ${widths}
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Reset Program Counters
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FOR ${platform} IN RV64 RV32
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${cpu}= Get Cpu On ${platform}
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Execute Command ${cpu}_0 PC ${CORE_0_PC}
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Execute Command ${cpu}_1 PC ${CORE_1_PC}
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END
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${platform:(RV32|RV64)} Should Invalidate Reservation On Memory Write
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# Invariant: executing `write_steps` of `write_instructions` sets memory location `shared_variable_address` to `VARIABLE_VALUE`.
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# They intentionally set it to the same value as before, since we want to check that the store itself is detected regardless of value change.
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[Arguments]
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... ${size}
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... ${shared_variable_address}
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... ${write_instructions}
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... ${write_steps}=1
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# Reset PC
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Reset Program Counters
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# Place shared value in memory.
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Execute Command sysbus WriteQuadWord ${shared_variable_address} ${VARIABLE_VALUE}
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${cpu}= Get Cpu On ${platform}
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# Prepare registers.
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FOR ${core} IN 0 1
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Execute Command ${cpu}_${core} SetRegister ${a0} ${shared_variable_address}
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Execute Command ${cpu}_${core} SetRegister ${a2} ${NEW_VARIABLE_VALUE}
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Execute Command ${cpu}_${core} SetRegister ${a4} ${VARIABLE_VALUE}
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END
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# Assemble LR/SC code for core 0.
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${core_0_code}= catenate SEPARATOR=${\n}
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... lr.${size} a1, (a0);
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... sc.${size} a3, a2, (a0);
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Execute Command ${cpu}_0 AssembleBlock ${CORE_0_PC} """${core_0_code}"""
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# Assemble memory write code for core 1.
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Execute Command ${cpu}_1 AssembleBlock ${CORE_1_PC} """${write_instructions}"""
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# Interleave core 1's write between LR and SC of core 0, which must cause invalidation.
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Execute Command ${cpu}_0 Step # LR
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Execute Command ${cpu}_1 Step ${write_steps} # write
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Execute Command ${cpu}_0 Step # SC
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# Check for SC failure.
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${value}= Execute Command sysbus ReadQuadWord ${shared_variable_address}
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Should Not Be Equal As Integers ${value} ${NEW_VARIABLE_VALUE} Expected value at ${shared_variable_address} to not be ${NEW_VARIABLE_VALUE} after interleaving LR/SC with `${write_instructions}` on ${platform}
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Register Should Be Equal ${a3} 1 cpuName=${cpu}_0
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*** Test Cases ***
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Writes To Reservation Should Cause Invalidation
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[Tags] robot:continue-on-failure
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FOR ${platform} IN RV64 RV32
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FOR ${address} IN ${ORDINARY_ADDRESS} ${MMIO_ADDRESS}
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${native_width}= Get Native Access Width On ${platform}
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${supported_widths}= Get Supported Access Widths On ${platform}
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${platform} Should Invalidate Reservation On Memory Write ${native_width} ${address}
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... lr.${native_width} a6, (a0); sc.${native_width} s2, a4, (a0);
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... write_steps=2
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${platform} Should Invalidate Reservation On Memory Write ${native_width} ${address}
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... amoswap.${native_width} s2, a4, (a0);
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${platform} Should Invalidate Reservation On Memory Write ${native_width} ${address}
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... amoadd.${native_width} a4, x0, (a0);
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FOR ${width} IN @{supported_widths}
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${platform} Should Invalidate Reservation On Memory Write ${native_width} ${address}
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... s${width} a4, (a0);
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END
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END
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END
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