83 lines
2.8 KiB
Plaintext
83 lines
2.8 KiB
Plaintext
*** Keywords ***
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Create RISC-V With ISA String
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[Arguments] ${ISAString}
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Execute Command mach create
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Execute Command logLevel 0
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Execute Command machine LoadPlatformDescriptionFromString "cpu: CPU.RiscV32 @ sysbus { cpuType: \\"${ISAString}\\"}"
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Create RISC-V64 With ISA String
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[Arguments] ${ISAString}
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Execute Command mach create
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Execute Command logLevel 0
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Execute Command machine LoadPlatformDescriptionFromString "cpu: CPU.RiscV64 @ sysbus { cpuType: \\"${ISAString}\\"}"
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Should Throw Construction Exception
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[Arguments] ${ISAString} ${exceptionMsg}
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Execute Command mach create
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Execute Command logLevel 0
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${out}= Run Keyword And Expect Error KeywordException:*
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... Execute Command machine LoadPlatformDescriptionFromString "cpu: CPU.RiscV32 @ sysbus { cpuType: \\"${ISAString}\\"}"
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Should Contain ${out} ${exceptionMsg}
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*** Test Cases ***
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Should Parse All Valid ISA Strings
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[Template] Create RISC-V With ISA String
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RV32G
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rv32gc
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rv32gc
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RV32GC
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rv32gc_xandes
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RV32GC_Xandes
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RV32GC_Zicsr_Zifencei
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RV32G_V
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rv32ia_zicsr_zifencei
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RV32IM
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RV32IMAC
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RV32IMACB_Zicsr_Zifencei
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RV32IMACFD_Zicsr
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RV32IMACFD_Zicsr_Zifencei
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rv32imac_zicsr
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RV32_IMACZicsr_Zifencei
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RV32IMAC_Zicsr_Zifencei
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RV32IMACZicsr_Zifencei
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rv32imafc_zifencei
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rv32imafdcg
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RV32IMAFDC_Zicsr
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RV32IMAFDC_Zicsr_Zifencei
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RV32IMAF_Zicsr_Zifencei
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rv32ima_zicsr_zifencei
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RV32IMC
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rv32imcb_zicsr_zifencei
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rv32imc_zicsr
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rv32imc_zicsr_zifencei
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RV32IMC_Zicsr_Zifencei_Zbs
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RV32IM_Zicsr
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rv32im_zicsr_zifencei
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RV32IZifencei_Xandes
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rv32ea_zicsr_zifencei
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RV32EM
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RV32EMAC
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rv32emac_zicsr
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RV32_EMACZicsr_Zifencei
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RV32EMAC_Zicsr_Zifencei
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RV32EMACZicsr_Zifencei
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rv32ema_zicsr_zifencei
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RV32EMC
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rv32emc_zicsr
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rv32emc_zicsr_zifencei
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RV32EMC_Zicsr_Zifencei_Zbs
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RV32EM_Zicsr
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rv32em_zicsr_zifencei
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RV32EZifencei_Xandes
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Should Handle Both 32 And 64 Bit Versions
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Create RISC-V With ISA String RV32IMAFDC_Zicsr_Zifencei
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Create RISC-V64 With ISA String RV64IMAFDC_Zicsr_Zifencei
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Should Throw Construction Exception
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[Template] Should Throw Construction Exception
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RV32IE ISA string cannot contain both I and E base instruction sets at the same time
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RV32EI ISA string cannot contain both I and E base instruction sets at the same time
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RV32EF RV32E can only have M, A and C standard extensions
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RV32FE RV32E can only have M, A and C standard extensions
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