493 lines
25 KiB
Plaintext
493 lines
25 KiB
Plaintext
*** Variables ***
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${initial_pc} 0x0
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*** Keywords ***
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# WriteDoubleWord: reversed bytes
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# Disassembly output: spaces between bytes
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DisasTest BE
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[Arguments] ${hex_code} ${mnemonic}= ${operands}= ${code_size}=4 ${hex_addr}=0 ${flags}=0
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${hex_addr}= Convert To Hex ${hex_addr} length=8 base=16
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${b1}= Get Substring ${hex_code} 0 2
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${b2}= Get Substring ${hex_code} 2 4
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${b3}= Get Substring ${hex_code} 4 6
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${b4}= Get Substring ${hex_code} 6 8
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${b_write}= Set Variable ${b4}${b3}${b2}${b1}
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${b_disas}= Set Variable ${b1}${b2}${b3}${b4}
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IF ${code_size} > 4
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${b_disas_4B+}= Write Extra Bytes BE And Return Their Expected Output ${hex_addr} ${hex_code}
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ELSE
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${b_disas_4B+}= Set Variable ${None}
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END
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${b_disas}= Set Variable If ${code_size} > 4 ${b_disas}${b_disas_4B+} ${b_disas}
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DisasTest Core ${hex_addr} ${b_write} ${b_disas} ${mnemonic} ${operands} ${code_size} ${flags}
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RoundTrip BE
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[Arguments] ${hex_code} ${mnemonic}= ${operands}= ${code_size}=4 ${hex_addr}=0 ${flags}=0 ${reverse}=True
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IF ${reverse}
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${expected}= Reverse Bytes ${{$hex_code[:int($code_size) * 2]}}
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ELSE
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${expected}= Set Variable ${hex_code}
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END
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AsTest ${expected} ${mnemonic} ${operands} ${flags} 0x${hex_addr}
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DisasTest BE ${hex_code} ${mnemonic} ${operands} ${code_size} ${hex_addr} ${flags}
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Write Extra Bytes BE And Return Their Expected Output
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[Arguments] ${hex_addr} ${hex_code}
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${int}= Convert To Integer 0x${hex_addr}
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${int}= Evaluate $int + 4
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${adjusted_addr}= Convert To Hex ${int}
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${b5}= Get Substring ${hex_code} 8 10
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${b6}= Get Substring ${hex_code} 10 12
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${b7}= Get Substring ${hex_code} 12 14
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${b8}= Get Substring ${hex_code} 14 16
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Execute Command sysbus WriteDoubleWord 0x${adjusted_addr} 0x${b8}${b7}${b6}${b5}
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Return From Keyword ${b5}${b6}${b7}${b8}
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Reverse Bytes
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[Arguments] ${hex_str} ${group_size}=${2}
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${len}= Get Length ${hex_str}
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${out}= Create List
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FOR ${i} IN RANGE 0 ${len} ${group_size}
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${byte}= Get Substring ${hex_str} ${i} ${{$i+$group_size}}
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Append To List ${out} ${byte}
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END
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Reverse List ${out}
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[Return] ${{"".join($out)}}
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# WriteDoubleWord: reversed words
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# Disassembly output: space between words
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DisasTest Thumb
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[Arguments] ${hex_code} ${mnemonic}= ${operands}= ${code_size}=4 ${hex_addr}=0
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${hex_addr}= Convert To Hex ${hex_addr} length=8 base=16
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${w1}= Get Substring ${hex_code} 0 4
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${w2}= Get Substring ${hex_code} 4
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${b_write}= Set Variable ${w2}${w1}
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${b_disas}= Set Variable ${w1}${w2}
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# `flags` is an internal parameter use by Renode in LLVMArchitectureMapping.cs:GetTripleAndModelKey to choose
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# the correct LLVM triple that represents the ARM* processor's state:
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# - bit 0 specifies whether we're in Thumb mode - both for ARMv7 and ARMv8
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# - bit 1 specifies whether we're in AArch32/32-bit mode (when set) or AArch64/64-bit mode (when unset) for ARMv8
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# Since the ARMv7 branch only checks `flags > 0` to switch to Thumb, and the ARMv8 branch _requires_ both bits
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# to be set for Thumb mode (no 64-bit Thumb), we set flags to 3 = 0b11, ie. "32-bit Thumb", to guarantee Thumb mode
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DisasTest Core ${hex_addr} ${b_write} ${b_disas} ${mnemonic} ${operands} ${code_size} flags=3
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RoundTrip Thumb
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[Arguments] ${hex_code} ${mnemonic}= ${operands}= ${code_size}=4 ${hex_addr}=0
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# For Thumb, reverse the bytes in each word
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${expected}= Reverse Bytes ${hex_code}
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${expected}= Reverse Bytes ${expected} group_size=${4}
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# See comment in `DisasTest Thumb` for meaning of flags
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AsTest ${expected} ${mnemonic} ${operands} address=0x${hex_addr} flags=3
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DisasTest Thumb ${hex_code} ${mnemonic} ${operands} ${code_size} ${hex_addr}
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DisasTest LE
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[Arguments] ${hex_code} ${mnemonic}= ${operands}= ${code_size}=4 ${hex_addr}=0
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${hex_addr}= Convert To Hex ${hex_addr} length=8 base=16
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DisasTest Core ${hex_addr} ${hex_code} ${hex_code} ${mnemonic} ${operands} ${code_size}
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RoundTrip LE
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[Arguments] ${hex_code} ${mnemonic}= ${operands}= ${code_size}=4 ${hex_addr}=0
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${expected}= Reverse Bytes ${{$hex_code[:int($code_size) * 2]}}
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AsTest ${expected} ${mnemonic} ${operands} address=0x${hex_addr}
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DisasTest LE ${hex_code} ${mnemonic} ${operands} ${code_size} ${hex_addr}
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DisasTest Core
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[Arguments] ${hex_addr} ${code_write} ${code_disas} ${mnemonic} ${operands} ${code_size} ${flags}=0
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Execute Command sysbus WriteDoubleWord 0x${hex_addr} 0x${code_write}
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${res}= Execute Command sysbus.cpu DisassembleBlock 0x${hex_addr} ${code_size} ${flags}
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# expect error if "$mnemonic" and "$operands" (without curly brackets!) are empty
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Run Keyword And Return If $mnemonic == '' and $operands == '' Should Match Regexp ${res} Disassembly error detected
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# compare DisassembleBlock output with the expected one; "(?i)" prefix causes ignoring case difference
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${escaped_mnem}= Regexp Escape ${mnemonic}
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${escaped_oper}= Regexp Escape ${operands}
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Should Match Regexp ${res} (?i)^0x${hex_addr}:\\s+${code_disas}\\s+${escaped_mnem}\\s+${escaped_oper}\\n+$
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AsTest
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[Arguments] ${expected} ${mnemonic} ${operands}= ${flags}=0 ${address}=0
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${len}= Execute Command sysbus.cpu AssembleBlock ${address} "${mnemonic} ${operands}" ${flags}
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${bytes}= Execute Command sysbus ReadBytes ${address} ${len}
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# This string is safe to eval because it's formatted as a Python list by PrintActionResult in MonitorCommands.cs
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${hex_bytes}= Evaluate "".join("%02x"%b for b in ${bytes})
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# Reverse the bytes for a big-endian bus because the expected strings in the test cases are formatted
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# as if they had been read by ReadDoubleWord
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${bus_endian}= Execute Command sysbus Endianess
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${bus_endian}= Get Line ${bus_endian} 0
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IF "${bus_endian}" == "BigEndian"
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${hex_bytes}= Reverse Bytes ${hex_bytes}
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END
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Should Be Equal ${hex_bytes} ${expected}
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Execute Instruction
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[Arguments] ${instruction}
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Execute Command cpu PC ${initial_pc}
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Execute Command cpu AssembleBlock ${initial_pc} "${instruction}"
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Execute Command cpu Step 1
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Memory Should Be Equal
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[Arguments] ${address} ${value}
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${res}= Execute Command sysbus ReadDoubleWord ${address}
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Should Be Equal As Numbers ${res} ${value}
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# Ordinary 'Register Should Be Equal ${register_number} ${value}' checks register with number one below than expected
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Xtensa Register Should Be Equal
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[Arguments] ${register} ${value} ${cpu}=cpu
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${res}= Execute Command ${cpu} GetRegister '${register}'
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Should Be Equal As Numbers ${value} ${res}
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Create Machine
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[Arguments] ${cpu} ${model}
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# "extra" will be appended to the cpu creation string after cpuType (at least it has to close curly brackets opened before cpuType)
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${extra}= Set Variable }
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${ARMv8_gic}= Set Variable genericInterruptController: gic }; gic: IRQControllers.ARM_GenericInterruptController @ { sysbus new Bus.BusMultiRegistration { address: 0x8000000; size: 0x010000; region: \\"distributor\\" }; sysbus new IRQControllers.ArmGicRedistributorRegistration { attachedCPU: cpu; address: 0x80a0000 } } { [0-1] -> cpu@[0-1]; architectureVersion: .GICv3; supportsTwoSecurityStates: true }
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# the last ${extra} field covers the "else" case, keeping the previous value of "extra"; by default, "else" case sets variables to "None"
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${extra}= Set Variable If "${cpu}" == "CortexM" ; nvic: nvic }; nvic: IRQControllers.NVIC ${extra}
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${extra}= Set Variable If "${cpu}" == "ARMv8A" ; ${ARMv8_gic} ${extra}
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${extra}= Set Variable If "${cpu}" == "ARMv8R" ; ${ARMv8_gic} ${extra}
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${extra}= Set Variable If "${cpu}" == "PowerPc64" ; endianness: Endianess.LittleEndian } ${extra}
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${extra}= Set Variable If "${cpu}" == "RiscV32" ; timeProvider: empty } ${extra}
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${extra}= Set Variable If "${cpu}" == "RiscV64" ; timeProvider: empty } ${extra}
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${extra}= Set Variable If "${cpu}" == "X86" ; lapic: empty } ${extra}
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${extra}= Set Variable If "${cpu}" == "X86_64" ; lapic: empty } ${extra}
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Execute Command mach create
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IF any(x in "${cpu}" for x in ("PowerPc", "Sparc"))
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Execute Command machine LoadPlatformDescriptionFromString "sysbus: { Endianess: Endianess.BigEndian }"
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END
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Execute Command machine LoadPlatformDescriptionFromString "cpu: CPU.${cpu} @ sysbus { cpuType: \\"${model}\\" ${extra}"
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Execute Command machine LoadPlatformDescriptionFromString "mem: Memory.MappedMemory @ sysbus 0x0 { size: 0x50000 }"
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Assemble And Disassemble RV32IMA
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[Arguments] ${compressed}=False
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# Compressed format will be generated by the assembler if the core has the C extension
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# and is only accepted by the disassembler if the core has the C extension. The disassembler
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# output doesn't explicitly indicate the compressed instruction (c.sw, c.add)
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IF ${compressed}
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RoundTrip LE c84a sw s2, 16(sp) 2 # rv32c
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RoundTrip LE 95be add a1, a1, a5 2 # rv32c
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ELSE
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RoundTrip LE 01212823 sw s2, 16(sp) # rv32i
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RoundTrip LE 00b785b3 add a1, a5, a1 # rv32i
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END
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# The uncompressed forms should be accepted by the disassembler even with the C extension
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DisasTest LE 01212823 sw s2, 16(sp) # rv32i
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DisasTest LE 00b785b3 add a1, a5, a1 # rv32i
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RoundTrip LE 00008297 auipc t0, 8 # rv32i
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RoundTrip LE 0000100f fence.i # Zifencei
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RoundTrip LE 3401f173 csrrci sp, mscratch, 3 # Zicsr
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RoundTrip LE 02ab5c33 divu s8, s6, a0 # rv32m
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RoundTrip LE 0805252f amoswap.w a0, zero, (a0) # rv32a
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Assemble And Disassemble RV32FD
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RoundTrip LE 580123d3 fsqrt.s ft7, ft2, rdn # rv32f
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RoundTrip LE 5a0123d3 fsqrt.d ft7, ft2, rdn # rv32d
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Assemble And Disassemble RV32C
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RoundTrip LE 3fed jal -6 2 # rv32c
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Assemble And Disassemble RV64IMAC
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RoundTrip LE 000a3a83 ld s5, 0(s4) # rv64i
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RoundTrip LE abcd8a9b addiw s5, s11, -1348 # rv64i
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RoundTrip LE 02ab7c3b remuw s8, s6, a0 # rv64m
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RoundTrip LE e705b52f amomaxu.d.aqrl a0, a6, (a1) # rv64a
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RoundTrip LE eabc sd a5, 80(a3) 2 # rv64c
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Assemble And Disassemble RV64FD
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RoundTrip LE d0312353 fcvt.s.lu ft6, sp, rdn # rv64f
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RoundTrip LE d2312353 fcvt.d.lu ft6, sp, rdn # rv64d
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Assemble And Disassemble RVV
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RoundTrip LE 00057757 vsetvli a4, a0, e8, m1, tu, mu # rv64v
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RoundTrip LE 03058407 vle8ff.v v8, (a1) # rv64v
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RoundTrip LE 4218a757 vfirst.m a4, v1 # rv64v
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*** Test Cases ***
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# Keywords to disassemble single instruction
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#
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# DisasTest (BE|LE|Thumb) HEX_CODE [MNEMONIC] [OPERANDS] [CODE_SIZE=4] [HEX_ADDR=00000000]
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# HEX_CODE the opcode to disassemble; don't prefix with "0x"
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# MNEMONIC, OPERANDS expected disassembly results; expect empty result if both are empty
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# CODE_SIZE in bytes; max 8B instructions are supported
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# HEX_ADDR hex address of the instruction, verified with the disassembler output but not influencing the opcode itself; don't prefix with "0x"
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Should Assemble And Disassemble ARM Cortex-A
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[Tags] basic-tests
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Create Machine ARMv7A arm926
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RoundTrip LE 32855001 addlo r5, r5, \#1 hex_addr=8000
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RoundTrip LE e1b00a00 lsls r0, r0, \#20 hex_addr=813c
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RoundTrip LE 1a00000a bne \#40
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Should Assemble And Disassemble ARM Cortex-A53
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Create Machine ARMv8A cortex-a53
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RoundTrip LE 5400f041 b.ne \#7688
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RoundTrip LE aa0603e1 mov x1, x6
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RoundTrip LE aa2c1c65 orn x5, x3, x12, lsl \#7
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Should Assemble And Disassemble ARM Cortex-M
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Create Machine CortexM cortex-m4
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RoundTrip Thumb f0230403 bic r4, r3, \#3 hex_addr=2
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RoundTrip Thumb 58c8 ldr r0, [r1, r3] 2
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RoundTrip Thumb f44f426d mov.w r2, \#60672 hex_addr=9e8
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RoundTrip Thumb 10b6 asrs r6, r6, \#2 2 ad88
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Should Assemble And Disassemble ARM Cortex-R52
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Create Machine ARMv8R cortex-r52
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RoundTrip LE e320f000 nop
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RoundTrip LE 43855040 orrmi r5, r5, #64
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RoundTrip LE e6ff3072 uxth r3, r2
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RoundTrip Thumb eb750903 sbcs.w r9, r5, r3
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RoundTrip Thumb ebb272e1 subs.w r2, r2, r1, asr #31
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RoundTrip Thumb fb821002 smull r1, r0, r2, r2
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Should Assemble And Disassemble RISCV32IMA
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[Tags] basic-tests
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Create Machine RiscV32 rv32ima
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Assemble And Disassemble RV32IMA
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Should Assemble And Disassemble RISCV32IMAC
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Create Machine RiscV32 rv32imac
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Assemble And Disassemble RV32IMA compressed=True
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Assemble And Disassemble RV32C
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Should Assemble And Disassemble RISCV32IMAFDC
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Create Machine RiscV32 rv32imafdc
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Assemble And Disassemble RV32IMA compressed=True
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Assemble And Disassemble RV32FD
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Assemble And Disassemble RV32C
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Should Assemble And Disassemble RISCV32GC
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Create Machine RiscV32 rv32gc
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Assemble And Disassemble RV32IMA compressed=True
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Assemble And Disassemble RV32FD
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Assemble And Disassemble RV32C
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Should Assemble And Disassemble RISCV32GC_XANDES
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Create Machine RiscV32 rv32gc_xandes
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Assemble And Disassemble RV32IMA compressed=True
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Assemble And Disassemble RV32FD
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Assemble And Disassemble RV32C
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Should Assemble And Disassemble RISCV32GV
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Create Machine RiscV32 rv32gv
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Assemble And Disassemble RV32IMA
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Assemble And Disassemble RVV
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Should Assemble And Disassemble RISCV64IMAC
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Create Machine RiscV64 rv64imac
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Assemble And Disassemble RV32IMA compressed=True
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Assemble And Disassemble RV64IMAC
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Should Assemble And Disassemble RISCV64IMAFDC
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Create Machine RiscV64 rv64imafdc
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Assemble And Disassemble RV32IMA compressed=True
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Assemble And Disassemble RV32FD
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Assemble And Disassemble RV64IMAC
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Assemble And Disassemble RV64FD
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Should Assemble And Disassemble RISCV64GC
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Create Machine RiscV64 rv64gc
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Assemble And Disassemble RV32IMA compressed=True
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Assemble And Disassemble RV32FD
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Assemble And Disassemble RV64IMAC
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Assemble And Disassemble RV64FD
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Should Assemble And Disassemble RISCV64GCV
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Create Machine RiscV64 rv64gcv
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Assemble And Disassemble RV64IMAC
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Assemble And Disassemble RVV
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Should Assemble And Disassemble PPC
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[Tags] basic-tests
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Create Machine PowerPc e200z6
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RoundTrip LE 4800007c b .+124
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RoundTrip LE 7f880040 cmplw 7, 8, 0 hex_addr=123
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RoundTrip LE 7ce40034 cntlzw 4, 7
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Should Assemble And Disassemble PPC64 LE
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[Tags] basic-tests
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Create Machine PowerPc64 620
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# RoundTrip BE is used because of the output formatting in DisasTest BE
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# CPU is set as LE in Renode and LLVM's LE version of ppc64 is used
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RoundTrip BE 18002389 lbz 9, 24(3)
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RoundTrip BE 40202a7c cmpld 10, 4
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RoundTrip BE 71790248 bl .+162160
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Should Assemble And Disassemble Sparc
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[Tags] basic-tests
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Create Machine Sparc leon3
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RoundTrip LE 85e8a018 restore %g2, 24, %g2 hex_addr=abc
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RoundTrip LE 01000000 nop hex_addr=abc
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RoundTrip LE 10680047 ba %xcc, 71
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Should Assemble And Disassemble X86 Using Intel Syntax
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[Tags] basic-tests
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Create Machine X86 x86
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RoundTrip BE 6b7b0c14 imul edi, dword ptr [ebx + 12], 20 flags=1 reverse=False
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RoundTrip BE 45 inc ebp 1 flags=1 reverse=False
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RoundTrip BE 0fb7c0 movzx eax, ax 3 cc flags=1 reverse=False
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RoundTrip BE 66890cc516a9fd00 mov word ptr [8*eax + 16623894], cx 8 a flags=1 reverse=False
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RoundTrip BE 0f011d5e00fc00 lidtd [16515166] 7 abd flags=1 reverse=False
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Should Assemble And Disassemble X86 Using GAS Syntax
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[Tags] basic-tests
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Create Machine X86 x86
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RoundTrip BE 6b7b0c14 imull $20, 12(%ebx), %edi reverse=False
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RoundTrip BE 45 incl %ebp 1 reverse=False
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RoundTrip BE 0fb7c0 movzwl %ax, %eax 3 cc reverse=False
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RoundTrip BE 66890cc516a9fd00 movw %cx, 16623894(,%eax,8) 8 a reverse=False
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RoundTrip BE 0f011d5e00fc00 lidtl 16515166 7 abd reverse=False
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Should Assemble And Disassemble X86_64 Using Intel Syntax
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[Tags] basic-tests
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Create Machine X86_64 x86_64
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RoundTrip BE 676b7b0c14 imul edi, dword ptr [ebx + 12], 20 5 flags=1 reverse=False
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# Only testing assembly here as the disassembly-testing keywords can handle at most 8 bytes of code.
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AsTest 48b8f0debc8a67452301 movabs rax, 81985529234382576 flags=1
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RoundTrip BE 48890cc516a9fd00 mov qword ptr [8*rax + 16623894], rcx 8 flags=1 reverse=False
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RoundTrip BE 48ffc0 inc rax 3 flags=1 reverse=False
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RoundTrip BE 65488b06 mov rax, qword ptr gs:[rsi] flags=1 reverse=False
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Should Assemble And Disassemble X86_64 Using GAS Syntax
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[Tags] basic-tests
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Create Machine X86_64 x86_64
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RoundTrip BE 676b7b0c14 imull $20, 12(%ebx), %edi 5 reverse=False
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AsTest 48b8f0debc8a67452301 movabsq $81985529234382576, %rax
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RoundTrip BE 48890cc516a9fd00 movq %rcx, 16623894(,%rax,8) 8 reverse=False
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RoundTrip BE 48ffc0 incq %rax 3 reverse=False
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RoundTrip BE 65488b06 movq %gs:(%rsi), %rax reverse=False
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Should Assemble And Disassemble Xtensa
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Create Machine Xtensa sample_controller
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RoundTrip BE 802160 abs a2, a8 3 reverse=False
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RoundTrip BE 301280 add a1, a2, a3 3 reverse=False
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RoundTrip BE f02000 nop ${EMPTY} 3 reverse=False
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RoundTrip BE 27811b bany a1, a2, . +31 3 reverse=False
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RoundTrip BE c60600 j . +31 3 reverse=False
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RoundTrip BE 050000 call0 . +4 3 reverse=False
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# Test Xtensa 'dense' option
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RoundTrip BE 1812 l32i.n a1, a2, 4 2 reverse=False
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RoundTrip BE 1922 s32i.n a1, a2, 8 2 reverse=False
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RoundTrip BE 0df0 ret.n ${EMPTY} 2 reverse=False
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RoundTrip BE 0df0 ret.n ${EMPTY} 2 reverse=False
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Should Assemble And Execute Xtensa
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Create Machine Xtensa sample_controller
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Execute Instruction movi.n a1, 0x10
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Xtensa Register Should Be Equal A1 0x10
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${A1}= Set Variable 0x1234
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${A2}= Set Variable 0x5432
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Execute Command cpu SetRegister 'A1' ${A1}
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Execute Command cpu SetRegister 'A2' ${A2}
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Execute Instruction add a3, a1, a2
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Xtensa Register Should Be Equal A3 0x6666
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${arbitrary_jump_target}= Set Variable 0x10
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Execute Command cpu SetRegister 'A1' ${arbitrary_jump_target}
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Execute Instruction jx a1
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PC Should be Equal ${arbitrary_jump_target}
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${some_value}= Set Variable 0x11223344
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Execute Command cpu SetRegister 'A1' 0x100
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Execute Command sysbus WriteDoubleWord 0x100 ${some_value}
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Execute Instruction l32i.n a2, a1, 0
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Xtensa Register Should Be Equal A2 ${some_value}
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${some_value}= Set Variable 0x88112233
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Execute Command cpu SetRegister 'A0' ${some_value}
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Execute Command cpu SetRegister 'A1' 0x100
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Execute Instruction s32i.n a0, a1, 0
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Memory Should Be Equal 0x100 ${some_value}
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Should Handle Illegal Instruction When Disassembling
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Create Machine RiscV64 rv64g
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DisasTest LE 0
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DisasTest LE 0000
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Should Handle Disassembly From Invalid Address
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Create Machine RiscV64 rv64g
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# test with the valid address
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DisasTest LE 02051613 slli a2, a0, 32 hex_addr=1234
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# check whether the output contains error if we only change the address to be outside "mem"
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Run Keyword And Expect Error 'Disassembly error detected* DisasTest LE 02051613 slli a2, a0, 32 hex_addr=02000000
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Should Take Base Address Into Account When Assembling
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Create Machine X86 x86
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AsTest 8d0534120000 a: lea eax, [a] address=0x1234 flags=1
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AsTest 8d053a120000 lea eax, [a]; a: address=0x1234 flags=1
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Should Assemble Multiline Program
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${prog}= Catenate SEPARATOR=\n
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... nop
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... nop
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Create Machine X86 x86
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Execute Command sysbus.cpu AssembleBlock 0 "${prog}"
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${ins}= Execute Command sysbus ReadWord 0
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Should Be Equal As Numbers ${ins} 0x9090
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Should Handle Illegal Instruction When Assembling
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Create Machine RiscV64 rv64g
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Run Keyword And Expect Error *unrecognized instruction mnemonic* AsTest 00 illegalinstruction123
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Run Keyword And Expect Error *invalid operand* AsTest 00 sw s123, 0(sp)
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# The V extension is not in rv64g so this is illegal as well
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Run Keyword And Expect Error *instruction requires * 'V'* AsTest 00 vsetvli a4, a0, e8, m1, tu, mu
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Should Handle Assembler Directives
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Create Machine X86 x86
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AsTest 909090909090 .rept 6; nop; .endr
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