97 lines
3.6 KiB
Plaintext
97 lines
3.6 KiB
Plaintext
mach create
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include @scripts/single-node/bus-isolation/SampleStateAwareReaderWithTransactionState.cs
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include @scripts/single-node/bus-isolation/SampleStateAwareReader.cs
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include @scripts/single-node/bus-isolation/SampleStateAwarePeripheral.cs
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machine LoadPlatformDescriptionFromString """
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cpu0: CPU.CortexM @ sysbus
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cpuType: "cortex-m33"
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numberOfMPURegions: 8
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nvic: nvic
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enableTrustZone: true
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nvic: IRQControllers.NVIC @ sysbus 0xe000e000
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-> cpu0@0
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flash0: Memory.MappedMemory @ sysbus 0x8000000
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size: 0x80000
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"""
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using sysbus
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# Look at SampleStateAwarePeripheral for an example of implementing different peripheral behavior based on the
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# transaction initiator and/or its state, and SampleStateAwareReader for an example of performing a transaction
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# with specified initiator identity.
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# Of course, 2 peripherals can be registered at the same address as long as they require a different cpu
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# state. See the `priv2_` ones as an example.
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machine LoadPlatformDescriptionFromString """
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unpriv: Python.PythonPeripheral @ sysbus new Bus.BusPointRegistration { address: 0x10000; condition: "(cpuSecure || !privileged) && initiator == cpu0" }
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size: 0x4
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initable: false
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script: "request.Value = 0x1010"
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priv: Python.PythonPeripheral @ sysbus new Bus.BusPointRegistration { address: 0x10004; condition: "cpuSecure && privileged && initiator == cpu0" }
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size: 0x4
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initable: false
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script: "request.Value = 0x2020"
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both: Python.PythonPeripheral @ sysbus new Bus.BusPointRegistration { address: 0x10008 }
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size: 0x4
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initable: false
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script: "request.Value = 0x3030"
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priv2_priv: Python.PythonPeripheral @ sysbus new Bus.BusPointRegistration { address: 0x1000c; condition: "privileged" }
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size: 0x4
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initable: false
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script: "request.Value = 0x4444"
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priv2_unpriv: Python.PythonPeripheral @ sysbus new Bus.BusPointRegistration { address: 0x1000c; condition: "!privileged" }
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size: 0x4
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initable: false
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script: "request.Value = 0x0404"
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priv_aware: CPU.SampleStateAwarePeripheral @ sysbus new Bus.BusPointRegistration { address: 0x10010; condition: "initiator == cpu0 || initiator == reader || initiator == reader2" }
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size: 0x100
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priv_aware2: CPU.SampleStateAwarePeripheral @ sysbus new Bus.BusPointRegistration { address: 0x20010; condition: "cpuSecure && initiator == reader" }
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size: 0x100
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reader: CPU.SampleStateAwareReaderWithTransactionState @ sysbus
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reader2: CPU.SampleStateAwareReader @ sysbus
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reader3: CPU.SampleStateAwareReader @ sysbus
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"""
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cpu0 AssembleBlock 0x8000000 """
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// First read in privileged mode
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ldr r0, =0x10000
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ldr r3, [r0] // expect 0x1010 in secure, 0 in nonsecure
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ldr r3, [r0] // expect 0x1010 in secure, 0 in nonsecure
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ldr r4, [r0, #4] // expect 0x2020 in secure, 0 in nonsecure
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ldr r4, [r0, #4] // expect 0x2020 in secure, 0 in nonsecure
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ldr r5, [r0, #8] // expect 0x3030
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ldr r6, [r0, #12] // expect 0x4444
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ldr r7, [r0, #16] // expect 0x63707507 in secure, 0x63707501 in nonsecure
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ldr r8, [r0, #20] // expect 0x63707507 in secure, 0x63707501 in nonsecure
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// Switch to unprivileged mode
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mrs r2, CONTROL
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orr r2, r2, #1
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msr CONTROL, r2
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isb
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// Reread in unprivileged mode
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ldr r9, [r0] // expect 0x1010 in both S and NS
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ldr r10, [r0, #4] // expect 0 in both S and NS
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ldr r11, [r0, #8] // expect 0x3030
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ldr r12, [r0, #12] // expect 0x0404
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ldr r1, [r0, #16] // expect 0x63707506 in secure, 0x63707500 in nonsecure
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ldr r2, [r0, #20] // expect 0x63707506 in secure, 0x63707500 in nonsecure
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b .
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"""
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cpu0 IDAUEnabled true
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cpu0 TryAddImplementationDefinedExemptionRegion 0x8000000 0x80000ff
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cpu0 TryAddImplementationDefinedExemptionRegion 0x10000 0x100ff
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cpu0 PC 0x8000000
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