322 lines
16 KiB
Plaintext
322 lines
16 KiB
Plaintext
*** Variables ***
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${CPU_COUNT} 4
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${INIT_PERIPHBASE_ADDRESS} 0xAE000000
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${INIT_PERIPHBASE} 0x57000
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${NEW_PERIPHBASE_ADDRESS} 0x80000000
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${NEW_PERIPHBASE} 0x40000
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${REPL_PATH} platforms/cpus/cortex-r8_smp.repl
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${SIGNALS_UNIT} signalsUnit
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${GIC_MODEL} Antmicro.Renode.Peripherals.IRQControllers.ARM_GenericInterruptController
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${PRIVATE_TIMER_MODEL} Antmicro.Renode.Peripherals.Timers.ARM_PrivateTimer
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${SCU_MODEL} Antmicro.Renode.Peripherals.Miscellaneous.ArmSnoopControlUnit
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*** Keywords ***
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Create Cortex-R8 Machine
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[Arguments] ${scu_registration}
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Execute Command mach create
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Execute Command machine LoadPlatformDescriptionFromString "using \\"${REPL_PATH}\\"; scu: @ ${scu_registration}"
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Should Modify Peripheral Registration
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Verify Command Output As Integer 0x0 cpu0 GetSystemRegisterValue "CBAR"
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Execute Command emulation RunFor '0.0001'
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FOR ${i} IN RANGE ${CPU_COUNT}
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# SCU address is based on PERIPHBASE with zero offset.
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Verify Command Output As Integer
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... ${INIT_PERIPHBASE_ADDRESS} cpu${i} GetSystemRegisterValue "CBAR"
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END
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Execute Command ${SIGNALS_UNIT} SetSignalFromAddress "PERIPHBASE" ${NEW_PERIPHBASE_ADDRESS}
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# Nothing changes before exiting from reset.
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Verify Peripherals Registered At ${INIT_PERIPHBASE_ADDRESS}
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Verify Command Output As Integer
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... ${INIT_PERIPHBASE_ADDRESS} cpu1 GetSystemRegisterValue "CBAR"
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# Let's make sure the behavior is preserved across serialization.
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${f}= Allocate Temporary File
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Execute Command Save @${f}
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Execute Command Clear
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Execute Command Load @${f}
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Execute Command mach set 0
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FOR ${i} IN RANGE ${CPU_COUNT}
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Execute Command cpu${i} Reset
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END
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Execute Command emulation RunFor '0.0001'
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FOR ${i} IN RANGE ${CPU_COUNT}
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Verify Command Output As Integer ${NEW_PERIPHBASE_ADDRESS} cpu${i} GetSystemRegisterValue "CBAR"
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END
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Verify Peripherals Registered At ${NEW_PERIPHBASE_ADDRESS}
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Verify Command Output As Integer
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[Arguments] ${expected} ${command}
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${output}= Execute Command ${command}
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Should Be Equal As Integers ${expected} ${output} base=16
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Verify Command Output
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[Arguments] ${expected} ${command}
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${output}= Execute Command ${command}
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Should Be Equal ${expected} ${output} strip_spaces=True
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Verify PERIPHBASE Init Value
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Verify Command Output As Integer ${INIT_PERIPHBASE_ADDRESS} ${SIGNALS_UNIT} GetAddress "PERIPHBASE"
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Verify Peripherals Registered At
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[Arguments] ${address}
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FOR ${i} IN RANGE ${CPU_COUNT}
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Verify Command Output
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... ${SCU_MODEL} sysbus WhatPeripheralIsAt ${address} cpu${i}
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Verify Command Output
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... ${GIC_MODEL} sysbus WhatPeripheralIsAt ${${address} + 0x100} cpu${i} # CPU interface
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Verify Command Output
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... ${GIC_MODEL} sysbus WhatPeripheralIsAt ${${address} + 0x1000} cpu${i} # distributor
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Verify Command Output
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... ${PRIVATE_TIMER_MODEL} sysbus WhatPeripheralIsAt ${${address} + 0x600} cpu${i}
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END
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Verify PCs
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[Arguments] ${cpu0_pc_expected} ${cpu1_pc_expected}
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Verify Command Output As Integer ${cpu0_pc_expected} cpu0 PC
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Verify Command Output As Integer ${cpu1_pc_expected} cpu1 PC
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*** Test Cases ***
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Create Machine With SCU Registered
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Create Cortex-R8 Machine scu_registration=sysbus ${INIT_PERIPHBASE_ADDRESS}
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Provides created-cr8-machine
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Should Gracefully Handle Invalid Signal
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Requires created-cr8-machine
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# All available signals should be printed with both names when the given signal can't be found.
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# Let's just check if two example signals are included: INITRAM and PERIPHBASE.
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Run Keyword And Expect Error *No such signal: ''\nAvailable signals are:*INITRAM (InitializeInstructionTCM)*
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... Execute Command ${SIGNALS_UNIT} GetSignal ""
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Run Keyword And Expect Error *No such signal: 'INVALID'\nAvailable signals are:*PERIPHBASE (PeripheralsBase)*
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... Execute Command ${SIGNALS_UNIT} GetSignal "INVALID"
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Should Handle Addresses
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Requires created-cr8-machine
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Verify PERIPHBASE Init Value
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Execute Command ${SIGNALS_UNIT} SetSignalFromAddress "PERIPHBASE" ${NEW_PERIPHBASE_ADDRESS}
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Verify Command Output As Integer ${NEW_PERIPHBASE_ADDRESS} ${SIGNALS_UNIT} GetAddress "PERIPHBASE"
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# When set from address, the signal is set to a value based on address' top bits.
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Verify Command Output As Integer ${NEW_PERIPHBASE} ${SIGNALS_UNIT} GetSignal "PERIPHBASE"
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Create Log Tester 0
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# DBGROMADDR is a 20-bit signal, let's first set it to a non-zero value.
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${exp_value}= Set Variable 0x12345
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${address}= Set Variable ${exp_value}000
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${signal}= Set Variable DebugROMAddress
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Execute Command ${SIGNALS_UNIT} SetSignalFromAddress ${signal} ${address}
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# Setting signals from addresses with bits over 32 set is invalid for Cortex-R8 even though only top 20 bits are set.
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${address_64b}= Set Variable 0xFEDCB00000000000
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Run Keyword And Expect Error *${SIGNALS_UNIT}: ${signal}: 20-bit signal in a 32-bit unit shouldn't be set from ${address_64b} address*
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... Execute Command ${SIGNALS_UNIT} SetSignalFromAddress ${signal} ${address_64b}
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# Valid address/value should be preserved.
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Verify Command Output As Integer ${address} ${SIGNALS_UNIT} GetAddress ${signal}
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Verify Command Output As Integer ${exp_value} ${SIGNALS_UNIT} GetSignal ${signal}
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# PFILTERSTART is a 12-bit signal so setting it from an address with any of bits 0-19 set should fail.
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${address}= Set Variable 0x12340000
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${signal}= Set Variable PeripheralFilterStart
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Run Keyword And Expect Error *${SIGNALS_UNIT}: ${signal}: 12-bit signal in a 32-bit unit shouldn't be set from ${address} address*
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... Execute Command ${SIGNALS_UNIT} SetSignalFromAddress ${signal} ${address}
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# Make sure it stayed zero.
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Verify Command Output As Integer 0x0 ${SIGNALS_UNIT} GetAddress ${signal}
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Verify Command Output As Integer 0x0 ${SIGNALS_UNIT} GetSignal ${signal}
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Should Modify Peripheral Registration With SCU Registered
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Requires created-cr8-machine
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Verify Command Output As Integer ${INIT_PERIPHBASE} ${SIGNALS_UNIT} GetSignal "PERIPHBASE"
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Verify Peripherals Registered At ${INIT_PERIPHBASE_ADDRESS}
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Should Modify Peripheral Registration
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Should Modify Peripheral Registration With SCU Unregistered
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Create Cortex-R8 Machine scu_registration=sysbus
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# SCU initially unregistered, PERIPHBASE not automatically set as when SCU registered at a specific address.
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Verify Command Output As Integer 0x0 ${SIGNALS_UNIT} GetSignal "PERIPHBASE"
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# There should be no peripheral at INIT_PERIPHBASE where SCU is registered by default.
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${peripherals}= Execute Command peripherals
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Should Not Contain ${peripherals} ${INIT_PERIPHBASE_ADDRESS}
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# Now let's set PERIPHBASE which will register SCU there on CPU out of reset and test modifying registrations.
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Execute Command ${SIGNALS_UNIT} SetSignalFromAddress "PERIPHBASE" ${INIT_PERIPHBASE_ADDRESS}
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Should Modify Peripheral Registration
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${peripherals}= Execute Command peripherals
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Should Set PC For Cores With INITRAM And VINITHI High
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Requires created-cr8-machine
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Execute Command cpu0 ExecutionMode SingleStep
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Execute Command cpu1 ExecutionMode SingleStep
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# Both signals will be high only for cpu0.
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Execute Command ${SIGNALS_UNIT} SetSignalStateForCPU "INITRAM" true cpu0
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Execute Command ${SIGNALS_UNIT} SetSignalStateForCPU "INITRAM" true cpu1
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Execute Command ${SIGNALS_UNIT} SetSignalStateForCPU "VINITHI" true cpu0
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Execute Command ${SIGNALS_UNIT} SetSignalStateForCPU "VINITHI" false cpu1
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Verify PCs 0x0 0x0
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Start Emulation
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Verify PCs 0xFFFF0000 0x0
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Execute Command cpu0 PC 0x12345678
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Execute Command cpu1 PC 0x90ABCDE0
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# PCs are set immediately because machine is started right after Reset if it was started before.
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Execute Command machine Reset
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Verify PCs 0xFFFF0000 0x0
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# Now both signals will be high only for cpu1.
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# Setting signals shouldn't influence PCs before starting-after-reset.
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Execute Command ${SIGNALS_UNIT} SetSignalStateForCPU "VINITHI" false cpu0
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Execute Command ${SIGNALS_UNIT} SetSignalStateForCPU "VINITHI" true cpu1
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Verify PCs 0xFFFF0000 0x0
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Execute Command cpu0 Reset
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Execute Command cpu1 Reset
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Verify PCs 0x0 0x0
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Execute Command cpu0 Start
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Execute Command cpu1 Start
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Verify PCs 0x0 0xFFFF0000
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Verify PERIPHBASE Init Value With CPU-specific SCU Registrations
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Execute Command mach create
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${PLATFORM}= Catenate SEPARATOR=\n
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... signalsUnit: Miscellaneous.CortexR8SignalsUnit @ sysbus
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... ${SPACE*4}snoopControlUnit: scu
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...
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... cpu0: CPU.ARMv7R @ sysbus
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... ${SPACE*4}cpuType: "cortex-r8"
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... ${SPACE*4}cpuId: 0
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... ${SPACE*4}signalsUnit: signalsUnit
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...
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... cpu1: CPU.ARMv7R @ sysbus
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... ${SPACE*4}cpuType: "cortex-r8"
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... ${SPACE*4}cpuId: 1
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... ${SPACE*4}signalsUnit: signalsUnit
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...
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... scu: Miscellaneous.ArmSnoopControlUnit @ {
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... ${SPACE*4}sysbus new Bus.BusPointRegistration { address: 0xae000000; cpu: cpu0 };
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... ${SPACE*4}sysbus new Bus.BusPointRegistration { address: 0xae000000; cpu: cpu1 }
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... }
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Execute Command machine LoadPlatformDescriptionFromString """${PLATFORM}"""
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Verify PERIPHBASE Init Value
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Registration Of Unsupported CPU Should Not Be Allowed From The Monitor
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Requires created-cr8-machine
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${CR5_CPU}= Catenate SEPARATOR=\n
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... cr5: CPU.ARMv7R @ sysbus
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... ${SPACE*4}cpuType: "cortex-r5"
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... ${SPACE*4}cpuId: 5
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Execute Command machine LoadPlatformDescriptionFromString """${CR5_CPU}"""
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${MESSAGE}= Catenate SEPARATOR=${SPACE}
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... *Tried to register unsupported CPU model to CortexR8SignalsUnit: cortex-r5;
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... supported CPUs are: cortex-r8*
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Run Keyword And Expect Error ${MESSAGE}
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... Execute Command ${SIGNALS_UNIT} RegisterCPU cr5
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Registration Of Unsupported CPU Should Not Be Allowed From Platform Description
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Execute Command mach create
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${CR8_CPU}= Catenate SEPARATOR=\n
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... ${SIGNALS_UNIT}: Miscellaneous.CortexR5SignalsUnit @ sysbus
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...
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... cpu: CPU.ARMv7R @ sysbus
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... ${SPACE*4}cpuType: "cortex-r8"
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... ${SPACE*4}signalsUnit: ${SIGNALS_UNIT}
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${MESSAGE}= Catenate SEPARATOR=${SPACE}
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... *Tried to register unsupported CPU model to CortexR5SignalsUnit: cortex-r8;
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... supported CPUs are: cortex-r5, cortex-r5f*
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Run Keyword And Expect Error ${MESSAGE}
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... Execute Command machine LoadPlatformDescriptionFromString """${CR8_CPU}"""
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Create Machine With Cortex-R5 And Cortex-R5F
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Execute Command mach create
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${PLATFORM}= Catenate SEPARATOR=\n
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... ${SIGNALS_UNIT}: Miscellaneous.CortexR5SignalsUnit @ sysbus
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...
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... cpu0: CPU.ARMv7R @ sysbus
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... ${SPACE*4}cpuType: "cortex-r5f"
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... ${SPACE*4}cpuId: 0
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... ${SPACE*4}signalsUnit: ${SIGNALS_UNIT}
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...
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... cpu1: CPU.ARMv7R @ sysbus
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... ${SPACE*4}cpuType: "cortex-r5"
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... ${SPACE*4}cpuId: 1
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... ${SPACE*4}signalsUnit: ${SIGNALS_UNIT}
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Execute Command machine LoadPlatformDescriptionFromString """${PLATFORM}"""
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Provides created-cr5-machine
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Set Cortex-R5 Peripheral Interface Region Registers With Signals
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Requires created-cr5-machine
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# So that there's no CPU abort after starting emulation which is also why SingleStep is used.
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Execute Command machine LoadPlatformDescriptionFromString "mem: Memory.MappedMemory @ sysbus 0x0 { size: 0x10000 }"
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# Base can be up to 20 bits.
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Execute Command ${SIGNALS_UNIT} SetSignalFromAddress "PPHBASE" 0x12345000
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Execute Command ${SIGNALS_UNIT} SetSignalFromAddress "PPXBASE" 0x60007000
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Execute Command ${SIGNALS_UNIT} SetSignalFromAddress "PPVBASE" 0x00089000
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# Size can be up to 5 bits.
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Execute Command ${SIGNALS_UNIT} SetSignal "PPHSIZE" 0x1F
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Execute Command ${SIGNALS_UNIT} SetSignal "PPXSIZE" 0x10
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Execute Command ${SIGNALS_UNIT} SetSignal "PPVSIZE" 0x0F
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FOR ${i} IN RANGE 2
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# Init is a per-cpu signal, there's no init signal for Virtual AXI Interface Region Register (PPVR).
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Execute Command ${SIGNALS_UNIT} SetSignalStateForCPU "INITPPH" false cpu${i}
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Execute Command ${SIGNALS_UNIT} SetSignalStateForCPU "INITPPX" true cpu${i}
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# Configuration signals take effect on CPU out of reset.
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Verify Command Output As Integer 0x0 cpu${i} GetSystemRegisterValue "PPHR"
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Verify Command Output As Integer 0x0 cpu${i} GetSystemRegisterValue "PPXR"
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Verify Command Output As Integer 0x0 cpu${i} GetSystemRegisterValue "PPVR"
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# Continuous code execution would quickly reach 0x10000 and cause CPU abort.
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Execute Command cpu${i} ExecutionMode SingleStep
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END
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Start Emulation
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FOR ${i} IN RANGE 2
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Verify Command Output As Integer ${{ hex(0x12345000 | (0x1F << 2) | 0) }} cpu${i} GetSystemRegisterValue "PPHR"
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Verify Command Output As Integer ${{ hex(0x60007000 | (0x10 << 2) | 1) }} cpu${i} GetSystemRegisterValue "PPXR"
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Verify Command Output As Integer ${{ hex(0x00089000 | (0x0F << 2) | 0) }} cpu${i} GetSystemRegisterValue "PPVR"
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END
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