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simulation_core
/
platforms
/
cpus
/
verilated
History
liuwb
b3117648be
仿真平台内核初版 -tlib库 包含<sparc arm riscv powerPC>
2026-02-07 20:43:43 +08:00
..
litex_vexriscv_verilated_cfu.repl
仿真平台内核初版 -tlib库 包含<sparc arm riscv powerPC>
2026-02-07 20:43:43 +08:00
litex_vexriscv_verilated_liteuart.repl
仿真平台内核初版 -tlib库 包含<sparc arm riscv powerPC>
2026-02-07 20:43:43 +08:00
murax_vexriscv_verilated_uart.repl
仿真平台内核初版 -tlib库 包含<sparc arm riscv powerPC>
2026-02-07 20:43:43 +08:00
riscv_verilated_uartlite.repl
仿真平台内核初版 -tlib库 包含<sparc arm riscv powerPC>
2026-02-07 20:43:43 +08:00
verilated_ibex.repl
仿真平台内核初版 -tlib库 包含<sparc arm riscv powerPC>
2026-02-07 20:43:43 +08:00