37 lines
871 B
Plaintext
37 lines
871 B
Plaintext
mem: Memory.MappedMemory @ sysbus 0x0
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size: 0x00040000
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sram: Memory.MappedMemory @ sysbus 0x10000000
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size: 0x00040000
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ddr: Memory.MappedMemory @ sysbus 0x40000000
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size: 0x10000000
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rom: Memory.MappedMemory @ sysbus 0x20020000
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size: 0x00008000
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boot_flash: Memory.ArrayMemory @ sysbus 0x20228000
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size: 0x00100000
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uart: UART.LiteX_UART @ sysbus 0xE0001800
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-> cpu@0
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eth: Network.LiteX_Ethernet @ {
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sysbus 0xE0003800;
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sysbus new Bus.BusMultiRegistration { address: 0xB0000000; size: 0x2000; region: "buffer" }
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}
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-> cpu@2
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cpu: CPU.Minerva @ sysbus
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timer0: Timers.LiteX_Timer @ sysbus 0xE0002800
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frequency: 100000000
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-> cpu@1
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sysbus:
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init:
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Tag <0xE0008000 0x200> "DDR_PHY"
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Tag <0xE0004000 0x200> "SDRAM_CONTROLLER"
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Tag <0xE0000800 0x200> "UART_PHY"
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