仿真平台内核初版 -tlib库 包含<sparc arm riscv powerPC>
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liuwb
477
tests/unit-tests/riscv-unit-tests.robot
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477
tests/unit-tests/riscv-unit-tests.robot
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*** Variables ***
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# RISC-V registers
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${a1} 0xb
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${starting_pc} 0x2000
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${next_instruction} 0x2004
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${mtvec} 0x1010
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${illegal_instruction} 0x2
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${load_misaligned} 0x4
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${store_misaligned} 0x6
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${register_0} 0x0
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${illegal_opcode} 0x00008000
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${illegal_csr} 0xf120d073
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${nonexisting_csr} 0xfff0d073
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${divide_by_zero_flag} ${{ 1 << 3 }}
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*** Keywords ***
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Create Machine
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[Arguments] ${bitness} ${init_pc}
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Execute Command using sysbus
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Execute Command mach create "risc-v"
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Execute Command machine LoadPlatformDescriptionFromString "clint: IRQControllers.CoreLevelInterruptor @ sysbus 0x44000000 { frequency: 66000000 }"
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Execute Command machine LoadPlatformDescriptionFromString "cpu: CPU.RiscV${bitness} @ sysbus { timeProvider: clint; cpuType: \\"rv${bitness}gc_Zfh\\" }"
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Execute Command machine LoadPlatformDescriptionFromString "mem: Memory.MappedMemory @ sysbus 0x1000 { size: 0x40000 }"
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IF ${init_pc}
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Execute Command cpu PC ${starting_pc}
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END
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Create Machine 32
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Create Machine bitness=32 init_pc=True
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Create Machine 64
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Create Machine bitness=64 init_pc=True
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Write Opcode To
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[Arguments] ${adress} ${opcode}
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Execute Command sysbus WriteDoubleWord ${adress} ${opcode}
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Load Program With Invalid Instruction
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[Arguments] ${address}
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${addi_opcode} Set Variable 0x00050593 #addi x11 x10 0
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${vector_opcode} Set Variable 0x00000057 #vadd.vv v0, v0, v0, v0.t
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${fvf_vector_opcode} Set Variable 0x00005057 #vfadd.vf v0, v0, ft0, v0.t
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${start_pc}= Convert To Integer ${address}
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# Depending on the fact if vector extension is enabled or not, the program will cause
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# invalid instruction exception at ${vector_opcode} or ${fvf_vector_opcode}.
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Write Opcode To ${start_pc} ${addi_opcode} #addi x11 x10 0
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Write Opcode To ${start_pc+4} ${addi_opcode} #addi x11 x10 0
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Write Opcode To ${start_pc+8} ${vector_opcode} #vadd.vv v0, v0, v0, v0.t
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Write Opcode To ${start_pc+12} ${addi_opcode} #addi x11 x10 0
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Write Opcode To ${start_pc+16} ${addi_opcode} #addi x11 x10 0
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Write Opcode To ${start_pc+20} ${addi_opcode} #addi x11 x10 0
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Write Opcode To ${start_pc+24} ${fvf_vector_opcode} #vfadd.vf v0, v0, ft0, v0.t
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Write Opcode To ${start_pc+28} ${addi_opcode} #addi x11 x10 0
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Write Opcode To ${start_pc+32} ${vector_opcode} #vadd.vv v0, v0, v0, v0.t
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Write Opcode To ${start_pc+36} ${addi_opcode} #addi x11 x10 0
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Set ResetVector And Verify PC
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[Arguments] ${reset_vector} ${should_set_pc}
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IF ${should_set_pc}
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${expected_pc}= Set Variable ${reset_vector}
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ELSE
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${expected_pc}= Execute Command cpu PC
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END
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Execute Command cpu ResetVector ${reset_vector}
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Verify PC ${expected_pc}
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Should Properly Handle ResetVector
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# Setting ResetVector before setting PC directly, with LoadELF etc. should propagate to PC.
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Set ResetVector And Verify PC 0x1234 should_set_pc=True
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Set ResetVector And Verify PC 0x1238 should_set_pc=True
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# Setting PC other than as an effect of ResetVector should stop the propagation.
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${new_reset_vector_value}= Set Variable 0x123C
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Execute Command cpu PC 0x5678
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Set ResetVector And Verify PC ${new_reset_vector_value} should_set_pc=False
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# Reset should set PC to ResetVector and restore PC propagation on ResetVector.
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Execute Command cpu Reset
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Verify PC ${new_reset_vector_value}
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Set ResetVector And Verify PC 0x1240 should_set_pc=True
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Should Properly Handle ResetVector At Init And After Reset
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Verify PC 0x1000 # Default ResetVector
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Should Properly Handle ResetVector
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${new_reset_vector_value}= Set Variable 0x2468
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Execute Command cpu ResetVector ${new_reset_vector_value}
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Execute Command cpu Reset
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Verify PC ${new_reset_vector_value}
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Should Properly Handle ResetVector
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Verify PC
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[Arguments] ${expected_pc}
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${pc}= Execute Command cpu PC
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Should Be Equal As Integers ${pc} ${expected_pc}
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*** Test Cases ***
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Should Handle LB
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Create Machine 32
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Execute Command cpu SetRegister ${a1} 0x00000000
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# lb a0, 0x00000005(a1)
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Execute Command sysbus WriteDoubleWord ${starting_pc} 0x00558503
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Execute Command cpu Step
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${pc}= Execute Command cpu PC
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Should Be Equal As Numbers ${pc} ${next_instruction}
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Should Handle LH
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Create Machine 32
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Execute Command cpu SetRegister ${a1} 0x00000001
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# lh a0, 0x00000005(a1)
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Execute Command sysbus WriteDoubleWord ${starting_pc} 0x00559503
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Execute Command cpu Step
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${pc}= Execute Command cpu PC
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Should Be Equal As Numbers ${pc} ${next_instruction}
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Should Fail LH
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Create Machine 32
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Execute Command cpu SetRegister ${a1} 0x00000000
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# lh a0, 0x00000005(a1)
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Execute Command sysbus WriteDoubleWord ${starting_pc} 0x00559503
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Execute Command cpu Step
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${pc}= Execute Command cpu PC
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Should Be Equal As Numbers ${pc} ${mtvec}
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${mcause}= Execute Command cpu MCAUSE
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Should Be Equal As Numbers ${mcause} ${load_misaligned}
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Should Handle LW
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Create Machine 32
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Execute Command cpu SetRegister ${a1} 0x00000003
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# lw a0, 0x00000005(a1)
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Execute Command sysbus WriteDoubleWord ${starting_pc} 0x0055a503
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Execute Command cpu Step
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${pc}= Execute Command cpu PC
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Should Be Equal As Numbers ${pc} ${next_instruction}
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Should Fail LW
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Create Machine 32
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Execute Command cpu SetRegister ${a1} 0x00000000
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# lw a0, 0x00000005(a1)
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Execute Command sysbus WriteDoubleWord ${starting_pc} 0x0055a503
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Execute Command cpu Step
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${pc}= Execute Command cpu PC
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Should Be Equal As Numbers ${pc} ${mtvec}
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${mcause}= Execute Command cpu MCAUSE
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Should Be Equal As Numbers ${mcause} ${load_misaligned}
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Should Handle LD
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Create Machine 64
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Execute Command cpu SetRegister ${a1} 0x00000003
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# ld a0, 0x00000005(a1)
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Execute Command sysbus WriteDoubleWord ${starting_pc} 0x0055b503
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Execute Command cpu Step
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${pc}= Execute Command cpu PC
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Should Be Equal As Numbers ${pc} ${next_instruction}
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Should Fail LD
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Create Machine 64
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Execute Command cpu SetRegister ${a1} 0x00000000
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# ld a0, 0x00000005(a1)
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Execute Command sysbus WriteDoubleWord ${starting_pc} 0x0055b503
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Execute Command cpu Step
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${pc}= Execute Command cpu PC
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Should Be Equal As Numbers ${pc} ${mtvec}
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${mcause}= Execute Command cpu MCAUSE
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Should Be Equal As Numbers ${mcause} ${load_misaligned}
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Should Handle SB
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Create Machine 32
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Execute Command cpu SetRegister ${a1} 0x00000000
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# sb a0, 0x00000005(a1)
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Execute Command sysbus WriteDoubleWord ${starting_pc} 0x00a582a3
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Execute Command cpu Step
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${pc}= Execute Command cpu PC
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Should Be Equal As Numbers ${pc} ${next_instruction}
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Should Handle SH
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Create Machine 32
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Execute Command cpu SetRegister ${a1} 0x00000001
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# sh a0, 0x00000005(a1)
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Execute Command sysbus WriteDoubleWord ${starting_pc} 0x00a592a3
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Execute Command cpu Step
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${pc}= Execute Command cpu PC
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Should Be Equal As Numbers ${pc} ${next_instruction}
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Should Fail SH
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Create Machine 32
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Execute Command cpu SetRegister ${a1} 0x00000000
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# sh a0, 0x00000005(a1)
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Execute Command sysbus WriteDoubleWord ${starting_pc} 0x00a592a3
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Execute Command cpu Step
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${pc}= Execute Command cpu PC
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Should Be Equal As Numbers ${pc} ${mtvec}
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${mcause}= Execute Command cpu MCAUSE
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Should Be Equal As Numbers ${mcause} ${store_misaligned}
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Should Handle SW
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Create Machine 32
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Execute Command cpu SetRegister ${a1} 0x00000003
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# sw a0, 0x00000005(a1)
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Execute Command sysbus WriteDoubleWord ${starting_pc} 0x00a5a2a3
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Execute Command cpu Step
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${pc}= Execute Command cpu PC
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Should Be Equal As Numbers ${pc} ${next_instruction}
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Should Fail SW
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Create Machine 32
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Execute Command cpu SetRegister ${a1} 0x00000000
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# sw a0, 0x00000005(a1)
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Execute Command sysbus WriteDoubleWord ${starting_pc} 0x00a5a2a3
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Execute Command cpu Step
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${pc}= Execute Command cpu PC
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Should Be Equal As Numbers ${pc} ${mtvec}
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${mcause}= Execute Command cpu MCAUSE
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Should Be Equal As Numbers ${mcause} ${store_misaligned}
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Should Handle SD
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Create Machine 64
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Execute Command cpu SetRegister ${a1} 0x00000003
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# sd a0, 0x00000005(a1)
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Execute Command sysbus WriteDoubleWord ${starting_pc} 0x00a5b2a3
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Execute Command cpu Step
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${pc}= Execute Command cpu PC
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Should Be Equal As Numbers ${pc} ${next_instruction}
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Should Fail SD
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Create Machine 64
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Execute Command cpu SetRegister ${a1} 0x00000001
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# sd a0, 0x00000005(a1)
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Execute Command sysbus WriteDoubleWord ${starting_pc} 0x00a5b2a3
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Execute Command cpu Step
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${pc}= Execute Command cpu PC
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Should Be Equal As Numbers ${pc} ${mtvec}
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${mcause}= Execute Command cpu MCAUSE
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Should Be Equal As Numbers ${mcause} ${store_misaligned}
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Should Fail On Setting X0 register
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Create Machine 32
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${msg}= Run Keyword And Expect Error * Execute Command cpu SetRegister ${register_0} 0x00000001
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Should Contain ${msg} register is read-only
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Register Should Be Equal 0 0x0
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Should Set MEPC on Illegal Instruction
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Create Machine 32
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# j .
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Execute Command sysbus WriteDoubleWord 0x1010 0x0000006f
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# j 0x4000
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Execute Command sysbus WriteDoubleWord ${starting_pc} 0x0000206f
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# nop
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Execute Command sysbus WriteDoubleWord 0x4000 0x00000013
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# ILLEGAL INSTRUCTION
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Execute Command sysbus WriteDoubleWord 0x4004 ${illegal_opcode}
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Execute Command cpu Step 3
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PC Should Be Equal 0x1010
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${mcause}= Execute Command cpu MCAUSE
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Should Be Equal As Numbers ${mcause} ${illegal_instruction}
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${mtval}= Execute Command cpu MTVAL
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Should Be Equal As Numbers ${mtval} ${illegal_opcode}
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${mepc}= Execute Command cpu MEPC
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Should Be Equal As Numbers ${mepc} 0x4004
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Should Set MEPC on Illegal CSR access
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Create Machine 32
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Execute Command cpu CSRValidation Full
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# j .
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Execute Command sysbus WriteDoubleWord 0x1010 0x0000006f
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# j 0x4000
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Execute Command sysbus WriteDoubleWord ${starting_pc} 0x0000206f
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# nop
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Execute Command sysbus WriteDoubleWord 0x4000 0x00000013
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# csrwi marchid, 1 - this is an illegal CSR operation as `marchid` is read-only
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Execute Command sysbus WriteDoubleWord 0x4004 ${illegal_csr}
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Execute Command cpu Step 3
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PC Should Be Equal 0x1010
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${mcause}= Execute Command cpu MCAUSE
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Should Be Equal As Numbers ${mcause} ${illegal_instruction}
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${mtval}= Execute Command cpu MTVAL
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Should Be Equal As Numbers ${mtval} ${illegal_csr}
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${mepc}= Execute Command cpu MEPC
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Should Be Equal As Numbers ${mepc} 0x4004
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Should Set MEPC on Non-Existing CSR access
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Create Machine 32
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# j .
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Execute Command sysbus WriteDoubleWord 0x1010 0x0000006f
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# j 0x4000
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Execute Command sysbus WriteDoubleWord ${starting_pc} 0x0000206f
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# nop
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Execute Command sysbus WriteDoubleWord 0x4000 0x00000013
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# csrwi marchid, 1 - this is an illegal CSR operation as `marchid` is read-only
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Execute Command sysbus WriteDoubleWord 0x4004 ${nonexisting_csr}
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Execute Command cpu Step 3
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PC Should Be Equal 0x1010
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${mcause}= Execute Command cpu MCAUSE
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Should Be Equal As Numbers ${mcause} ${illegal_instruction}
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${mtval}= Execute Command cpu MTVAL
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Should Be Equal As Numbers ${mtval} ${nonexisting_csr}
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${mepc}= Execute Command cpu MEPC
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Should Be Equal As Numbers ${mepc} 0x4004
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Should Allow SRET In Machine Mode
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Create Machine 32
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Execute Command cpu SEPC 0x1234
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# j 0x4000
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Execute Command sysbus WriteDoubleWord ${starting_pc} 0x0000206f
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# nop
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Execute Command sysbus WriteDoubleWord 0x4000 0x00000013
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# sret
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Execute Command sysbus WriteDoubleWord 0x4004 0x10200073
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Execute Command cpu Step 3
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PC Should Be Equal 0x1234
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Should Exit Translation Block After Invalid Instruction And Report Single Error
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Create Machine 32
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Load Program With Invalid Instruction ${starting_pc}
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Create Log Tester 3
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${start_pc}= Convert To Integer ${starting_pc}
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${illegal_opcode_1_pc} Set Variable ${start_pc+8}
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${illegal_opcode_1_pc_hex}= Convert To Hex ${illegal_opcode_1_pc}
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${illegal_opcode_2_pc} Set Variable ${start_pc+24}
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${illegal_opcode_2_pc_hex}= Convert To Hex ${illegal_opcode_2_pc}
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${illegal_opcode_3_pc} Set Variable ${start_pc+32}
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${illegal_opcode_3_pc_hex}= Convert To Hex ${illegal_opcode_3_pc}
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# It doesn't use single stepping on purpose, as it would cause translation blocks of size 1.
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Execute Command cpu PerformanceInMips 1
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Execute Command emulation SetGlobalQuantum "0.000020"
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Execute Command emulation RunFor "0.000010"
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Wait For Log Entry PC: 0x${illegal_opcode_1_pc_hex}.* instruction set is not enabled for this CPU! treatAsRegex=True
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Should Not Be In Log PC: 0x${illegal_opcode_2_pc_hex}.* instruction set is not enabled for this CPU! 0 treatAsRegex=True
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Should Not Be In Log PC: 0x${illegal_opcode_3_pc_hex}.* instruction set is not enabled for this CPU! 0 treatAsRegex=True
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Should Properly Handle ResetVector After Creation And After Reset 32
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Create Machine bitness=32 init_pc=False
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Should Properly Handle ResetVector At Init And After Reset
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Should Properly Handle ResetVector After Creation And After Reset 64
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Create Machine bitness=64 init_pc=False
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Should Properly Handle ResetVector At Init And After Reset
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Should Set Flag On Single Precision Floating Point Division By Zero
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[Tags] floating-point
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${float32_zero}= Set Variable 0xffffffff00000000
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${float32_one}= Set Variable 0xffffffff3F800000
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${float32_infinity}= Set Variable 0xffffffff7f800000
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Create Machine 64
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Execute Command cpu SetRegister "F0" ${float32_zero}
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Execute Command cpu SetRegister "F1" ${float32_one}
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Execute Command cpu SetRegister "F2" 0x0 # register where result will be stored
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# Expected result: 1/0 = Infinity and Divide by Zero flag set.
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Execute Command cpu AssembleBlock ${starting_pc} "fdiv.s f2, f1, f0"
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Register Should Be Equal F2 0x0
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${fflags}= Execute Command cpu GetRegister "FFLAGS"
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Should Be True (${fflags} & ${divide_by_zero_flag}) == 0
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Execute Command cpu Step
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PC Should Be Equal ${{ ${starting_pc} + 4 }}
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Register Should Be Equal F2 ${float32_infinity}
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${fflags}= Execute Command cpu GetRegister "FFLAGS"
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Should Be True (${fflags} & ${divide_by_zero_flag}) != 0
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Should Set Flag On Half Precision Floating Point Division By Zero
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[Tags] floating-point
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${float16_zero}= Set Variable 0xffffffffffff0000
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${float16_one}= Set Variable 0xffffffffffff3c00
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${float16_infinity}= Set Variable 0xffffffffffff7c00
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Create Machine 64
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Execute Command cpu SetRegister "F0" ${float16_zero}
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Execute Command cpu SetRegister "F1" ${float16_one}
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Execute Command cpu SetRegister "F2" 0x0 # register where result will be stored
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||||
# Expected result: 1/0 = Infinity and Divide by Zero flag set.
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Execute Command cpu AssembleBlock ${starting_pc} "fdiv.h f2, f1, f0"
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||||
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Register Should Be Equal F2 0x0
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${fflags}= Execute Command cpu GetRegister "FFLAGS"
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Should Be True (${fflags} & ${divide_by_zero_flag}) == 0
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||||
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||||
Execute Command cpu Step
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||||
PC Should Be Equal ${{ ${starting_pc} + 4 }}
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||||
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||||
Register Should Be Equal F2 ${float16_infinity}
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||||
${fflags}= Execute Command cpu GetRegister "FFLAGS"
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||||
Should Be True (${fflags} & ${divide_by_zero_flag}) != 0
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||||
Reference in New Issue
Block a user