仿真平台内核初版 -tlib库 包含<sparc arm riscv powerPC>
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liuwb
210
tests/unit-tests/per-core-registration.robot
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210
tests/unit-tests/per-core-registration.robot
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*** Variables ***
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${UART} sysbus.uart
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${COMMON_MEMORY} 0x1400000
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${PER_CORE_MEMORY} 0x3000000
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${CORE1_MEM_ALIAS} 0x2010000
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${CORE2_MEM_ALIAS} 0x2020000
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${UART_ADDR} 0x50230000
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${UART_ADDR_MOVED} 0x60230000
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${URI} @https://dl.antmicro.com/projects/renode
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${TEST_ELF} ${URI}/multibus_test.elf-s_3718712-8ec6b7305242b1bfce702459d75ea02d04f00360
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${CPU1_OVERLAY_MEMORY}= SEPARATOR=
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... """ ${\n}
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... cpu1_mem: Memory.ArrayMemory @ sysbus new Bus.BusPointRegistration { ${\n}
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... ${SPACE*4}address: 0x0; ${\n}
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... ${SPACE*4}cpu: cpu1 ${\n}
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... } ${\n}
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... ${SPACE*4}size: 0x1000 ${\n}
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... """
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${CPU1_SHADOW_MEMORY}= SEPARATOR=
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... """ ${\n}
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... cpu1_shadow_mem: Memory.ArrayMemory @ sysbus new Bus.BusPointRegistration { ${\n}
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... ${SPACE*4}address: 0xF00; ${\n}
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... ${SPACE*4}cpu: cpu1 ${\n}
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... } ${\n}
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... ${SPACE*4}size: 0x1000 ${\n}
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... """
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*** Keywords ***
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Create Machine
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[Arguments] ${elf}
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Execute Command mach create
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Execute Command machine LoadPlatformDescription "${CURDIR}${/}per-core-registration.repl"
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Execute Command macro reset "sysbus LoadELF ${elf}"
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Execute Command runMacro $reset
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Create Terminal Tester ${UART} timeout=1
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Create Machine With Hex File
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[Arguments] ${cpu}
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Execute Command mach create
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Execute Command machine LoadPlatformDescription "${CURDIR}${/}per-core-registration-hex.repl"
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Execute Command sysbus LoadHEX @https://dl.antmicro.com/projects/renode/stm32f072b_disco--zephyr-hello_world.hex-s_34851-4e97c68491cf652d0becd549526cd3df56e8ae66 ${cpu}
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Add Peripheral Move Hook
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[Arguments] ${cpu} ${hook_addr} ${peripheral_addr} ${new_address}
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${hook_script}= Catenate SEPARATOR=\n
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... from Antmicro.Renode.Peripherals.Bus import BusRangeRegistration
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... uart_peripheral = machine.SystemBus.WhatIsAt(${peripheral_addr}, cpu).Peripheral
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... new_registration = BusRangeRegistration(${new_address}, uart_peripheral.Size)
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... machine.SystemBus.MoveRegistrationWithinContext(uart_peripheral, new_registration, cpu)
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Execute Command ${cpu} AddHook ${hook_addr} """${hook_script}"""
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*** Test Cases ***
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Fail On Shadowing Other Registration
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# Create machine with `ram` at 0x0 - 0x1FFFFFF.
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Create Machine ${TEST_ELF}
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# Adding a CPU-specific peripheral over a global one is OK, accesses from that CPU will reach it instead.
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Execute Command machine LoadPlatformDescriptionFromString ${CPU1_OVERLAY_MEMORY}
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# Adding another CPU-specific peripheral at address space already occupied for the given CPU should fail though.
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${out}= Run Keyword And Expect Error KeywordException:*
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... Execute Command
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... machine LoadPlatformDescriptionFromString ${CPU1_SHADOW_MEMORY}
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Should Contain ${out} Error E39: Exception was thrown during registration
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Should Contain ${out} conflicts with peripheral
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${per}= Execute Command peripherals
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Should Contain ${per} cpu1_mem
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Should Not Contain ${per} cpu1_shadow_mem
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Get Same Read From Common Memory
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Create Machine ${TEST_ELF}
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Execute Command sysbus WriteDoubleWord ${COMMON_MEMORY} 0xDEADF00D
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Start Emulation
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Wait For Line On Uart Core 0 read from ${COMMON_MEMORY} returned: 0xDEADF00D
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Wait For Line On Uart Core 1 read from ${COMMON_MEMORY} returned: 0xDEADF00D
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Values Written By One Core Should Not Be Visible By The Other One
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Create Machine ${TEST_ELF}
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Start Emulation
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Wait For Line On Uart Core 0 read from ${PER_CORE_MEMORY} returned: 0x0
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Wait For Line On Uart Core 0 writing 0xB0B0B0B0 to per-core memory
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Wait For Line On Uart Core 0 read from ${PER_CORE_MEMORY} returned: 0xB0B0B0B0
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Wait For Line On Uart Core 1 read from ${PER_CORE_MEMORY} returned: 0x0
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Wait For Line On Uart Core 1 writing 0xBABABABA to per-core memory
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Wait For Line On Uart Core 1 read from ${PER_CORE_MEMORY} returned: 0xBABABABA
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Provides Finished
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Write Values Using Sysbus
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Create Machine ${TEST_ELF}
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Execute Command sysbus.core1_mem WriteDoubleWord 0x0 0xFEEDFACE
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Execute Command sysbus.core2_mem WriteDoubleWord 0x0 0xFEE1DEAD
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Start Emulation
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Wait For Line On Uart Core 0 read from ${PER_CORE_MEMORY} returned: 0xFEEDFACE
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Wait For Line On Uart Core 1 read from ${PER_CORE_MEMORY} returned: 0xFEE1DEAD
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Write Values Using Sysbus With Context
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Create Machine ${TEST_ELF}
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Execute Command sysbus WriteDoubleWord ${PER_CORE_MEMORY} 0xFEEDFACE sysbus.cpu1
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Execute Command sysbus WriteDoubleWord ${PER_CORE_MEMORY} 0xFEE1DEAD sysbus.cpu2
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Start Emulation
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Wait For Line On Uart Core 0 read from ${PER_CORE_MEMORY} returned: 0xFEEDFACE
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Wait For Line On Uart Core 1 read from ${PER_CORE_MEMORY} returned: 0xFEE1DEAD
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Handle Being Simultaneously Registered On The Main Bus
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Requires Finished
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${out}= Execute Command sysbus ReadDoubleWord ${CORE1_MEM_ALIAS}
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Should Be Equal As Numbers ${out} 0xB0B0B0B0
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${out}= Execute Command sysbus ReadDoubleWord ${CORE2_MEM_ALIAS}
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Should Be Equal As Numbers ${out} 0xBABABABA
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Read Values Using Sysbus Context
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Requires Finished
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${out}= Execute Command sysbus ReadDoubleWord ${PER_CORE_MEMORY} sysbus.cpu1
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Should Be Equal As Numbers ${out} 0xB0B0B0B0
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${out}= Execute Command sysbus ReadDoubleWord ${PER_CORE_MEMORY} sysbus.cpu2
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Should Be Equal As Numbers ${out} 0xBABABABA
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Disassemble Code From Per Core Memory
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Create Machine ${TEST_ELF}
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Execute Command sysbus WriteDoubleWord ${PER_CORE_MEMORY} 0x1234 sysbus.cpu1
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Execute Command sysbus WriteDoubleWord ${PER_CORE_MEMORY} 0x5678 sysbus.cpu2
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${out}= Execute Command sysbus.cpu1 DisassembleBlock ${PER_CORE_MEMORY} 2
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Should Contain ${out} addi
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${out}= Execute Command sysbus.cpu2 DisassembleBlock ${PER_CORE_MEMORY} 2
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Should Contain ${out} lw
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Should Move Peripheral Registered Per Core
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Create Machine ${TEST_ELF}
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# Verify expected UART registration
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${out}= Execute Command sysbus WhatIsAt ${UART_ADDR} sysbus.cpu1
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Should Not Be Empty ${out}
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${out}= Execute Command sysbus WhatIsAt ${UART_ADDR} sysbus.cpu2
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Should Not Be Empty ${out}
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${out}= Execute Command sysbus WhatIsAt ${UART_ADDR_MOVED} sysbus.cpu1
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Should Be Empty ${out}
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${out}= Execute Command sysbus WhatIsAt ${UART_ADDR_MOVED} sysbus.cpu2
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Should Be Empty ${out}
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Add Peripheral Move Hook sysbus.cpu2 `sysbus GetSymbolAddress "thread_entry"` ${UART_ADDR} ${UART_ADDR_MOVED}
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Execute Command showAnalyzer sysbus.uart
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Execute Command start
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Wait For Line On Uart Core 0 read from ${PER_CORE_MEMORY} returned: 0xB0B0B0B0
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Run Keyword And Expect Error InvalidOperationException: Terminal tester failed!*
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... Wait For Line On Uart
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... Core 1 read from ${PER_CORE_MEMORY} returned: 0xBABABABA
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Execute Command pause
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Execute Command sysbus.cpu2 RemoveHooksAt `sysbus GetSymbolAddress "thread_entry"`
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Add Peripheral Move Hook sysbus.cpu2 `sysbus GetSymbolAddress "thread_entry"` ${UART_ADDR_MOVED} ${UART_ADDR}
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Clear Terminal Tester Report
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Execute Command runMacro $reset
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# UART registration shouldn't reset
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${out}= Execute Command sysbus WhatIsAt ${UART_ADDR} sysbus.cpu1
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Should Not Be Empty ${out}
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${out}= Execute Command sysbus WhatIsAt ${UART_ADDR_MOVED} sysbus.cpu2
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Should Not Be Empty ${out}
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${out}= Execute Command sysbus WhatIsAt ${UART_ADDR_MOVED} sysbus.cpu1
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Should Be Empty ${out}
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${out}= Execute Command sysbus WhatIsAt ${UART_ADDR} sysbus.cpu2
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Should Be Empty ${out}
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Execute Command start
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Wait For Line On Uart Core 0 read from ${PER_CORE_MEMORY} returned: 0xB0B0B0B0
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Wait For Line On Uart Core 1 read from ${PER_CORE_MEMORY} returned: 0xBABABABA
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Should Not Load Hex To Invalid Core Specific Memory
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Create Log Tester 0 # no need for additional timeout, we're only testing synchronous operations
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Create Machine With Hex File sysbus.cpu1
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Wait For Log Entry Tried to access bytes at non-existing peripheral
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Should Load Hex To Core Specific Memory
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Create Log Tester 0 # no need for additional timeout, we're only testing synchronous operations
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Create Machine With Hex File sysbus.cpu2
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Should Not Be In Log Tried to access bytes at non-existing peripheral
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