仿真平台内核初版 -tlib库 包含<sparc arm riscv powerPC>
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44
tests/unit-tests/per-core-registration-hex.repl
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44
tests/unit-tests/per-core-registration-hex.repl
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cpu1: CPU.CortexM @ sysbus
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cpuType: "cortex-m4"
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nvic: nvic1
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id: 0
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cpu2: CPU.CortexM @ sysbus
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cpuType: "cortex-m4"
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nvic: nvic2
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id: 1
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core1_mem: Memory.MappedMemory @ {
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sysbus new Bus.BusPointRegistration {
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address: 0x07000000;
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cpu: cpu1
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}
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}
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size: 0x4000
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core2_mem: Memory.MappedMemory @ {
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sysbus new Bus.BusPointRegistration {
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address: 0x08000000;
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cpu: cpu2
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}
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}
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size: 0x4000
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nvic1: IRQControllers.NVIC @ sysbus new Bus.BusPointRegistration {
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address: 0xE000E000;
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cpu: cpu1
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}
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priorityMask: 0xF0
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systickFrequency: 72000000
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-> cpu1@0
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nvic2: IRQControllers.NVIC @ sysbus new Bus.BusPointRegistration {
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address: 0xE000E000;
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cpu: cpu2
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}
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priorityMask: 0xF0
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systickFrequency: 72000000
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-> cpu2@0
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