仿真平台内核初版 -tlib库包含<sparc arm riscv powerPC>

2026-02-07 20:43:43 +08:00
parent de61f9e2b0
commit b3117648be
9748 changed files with 4309137 additions and 0 deletions
--- a/tests/unit-tests/per-core-registration-hex.repl
+++ b/tests/unit-tests/per-core-registration-hex.repl
@@ -0,0 +1,44 @@
+cpu1: CPU.CortexM @ sysbus
+    cpuType: "cortex-m4"
+    nvic: nvic1
+    id: 0
+
+
+cpu2: CPU.CortexM @ sysbus
+    cpuType: "cortex-m4"
+    nvic: nvic2
+    id: 1
+
+
+core1_mem: Memory.MappedMemory @ {
+    sysbus new Bus.BusPointRegistration {
+        address: 0x07000000;
+        cpu: cpu1
+    }
+}
+    size: 0x4000
+
+
+core2_mem: Memory.MappedMemory @ {
+    sysbus new Bus.BusPointRegistration {
+        address: 0x08000000;
+        cpu: cpu2
+    }
+}
+    size: 0x4000
+
+nvic1: IRQControllers.NVIC @ sysbus new Bus.BusPointRegistration {
+        address: 0xE000E000;
+        cpu: cpu1
+    }
+    priorityMask: 0xF0
+    systickFrequency: 72000000
+    -> cpu1@0
+
+nvic2: IRQControllers.NVIC @ sysbus new Bus.BusPointRegistration {
+        address: 0xE000E000;
+        cpu: cpu2
+    }
+    priorityMask: 0xF0
+    systickFrequency: 72000000
+    -> cpu2@0