仿真平台内核初版 -tlib库包含<sparc arm riscv powerPC>

2026-02-07 20:43:43 +08:00
parent de61f9e2b0
commit b3117648be
9748 changed files with 4309137 additions and 0 deletions
--- a/tests/unit-tests/offset-bus-registrations.repl
+++ b/tests/unit-tests/offset-bus-registrations.repl
@@ -0,0 +1,21 @@
+cpu: CPU.RiscV64 @ sysbus {
+    cpuType: "rv64g";
+    timeProvider: empty
+}
+
+code: Memory.MappedMemory @ sysbus 0x2000 {
+    size: 0x10000
+}
+
+dram: Memory.MappedMemory @ {
+        sysbus new Bus.BusRangeRegistration { address: 0x81000000; size: 0x1000; offset: 0x4000; cpu: cpu};
+        sysbus 0x80000000
+    }
+    size: 0x10000000
+
+mmio: Memory.ArrayMemory @ {
+        sysbus new Bus.BusRangeRegistration { address: 0x91000000; size: 0x1000; offset: 0x4000; cpu: cpu};
+        sysbus 0x90000000
+    }
+    size: 0x10000000
+