仿真平台内核初版 -tlib库 包含<sparc arm riscv powerPC>

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liuwb
2026-02-07 20:43:43 +08:00
parent de61f9e2b0
commit b3117648be
9748 changed files with 4309137 additions and 0 deletions

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*** Variables ***
${URI} @https://dl.antmicro.com/projects/renode
${HIFIVE1} @platforms/cpus/sifive-fe310.repl
*** Keywords ***
Create Machine
Execute Command using sysbus
Execute Command mach create
Execute Command machine LoadPlatformDescription @${HIFIVE1}
Execute Command sysbus LoadELF @${URI}/hifive--zephyr-test_gpio_api_1pin.elf-s_642052-3e07acfbb42b60dfda51d4a66eb6f4ad714d3e34
Create Terminal Tester sysbus.uart0
*** Test Cases ***
Should Pass Zephyr "drivers/gpio/gpio_api_1pin" test suite on HiFive1
Create Machine
Wait For Line On Uart PROJECT EXECUTION SUCCESSFUL