仿真平台内核初版 -tlib库 包含<sparc arm riscv powerPC>
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liuwb
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tests/unit-tests/bus-isolation.robot
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206
tests/unit-tests/bus-isolation.robot
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*** Variables ***
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${CPU0_INITIATOR_STRING} the initiator 'cpu0'
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${POSSIBLE_INITIATORS_STRING} peripherals implementing IPeripheralWithTransactionState (initiator not specified)
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${SIMPLE_M33_REPL} SEPARATOR=\n
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... """
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... nvic: IRQControllers.NVIC @ sysbus new Bus.BusPointRegistration {
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... ${SPACE*8}address: 0xE000E000;
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... ${SPACE*8}cpu: cpu
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... ${SPACE*4}}
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... ${SPACE*4}-> cpu@0
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... cpu: CPU.CortexM @ sysbus
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... ${SPACE*4}cpuType: "cortex-m33"
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... ${SPACE*4}nvic: nvic
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... ${SPACE*4}cpuId: 0
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... mem: Memory.ArrayMemory @ sysbus new Bus.BusPointRegistration { address: 0x10000; condition: "privileged && cpuSecure && attributionSecure"}
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... ${SPACE*4}size: 0x1000
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*** Keywords ***
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Command Result Should Be Number
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[Arguments] ${command} ${result}
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${actual}= Execute Command ${command}
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Should Be Equal As Numbers ${actual} ${result}
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Create Bus Isolation Machine
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Execute Script tests/unit-tests/bus_isolation.resc
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Register With Condition And Expect Error
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[Arguments] ${condition} ${error}
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Run Keyword And Expect Error *${error}*
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... Execute Command machine LoadPlatformDescriptionFromString "uart: UART.PL011 @ sysbus new Bus.BusPointRegistration { address: 0x0; condition: \\"${condition}\\" }"
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Create Simple M33 Machine
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[Arguments] ${enableTrustZone}=true
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Execute Command mach create
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Execute Command machine LoadPlatformDescriptionFromString ${SIMPLE_M33_REPL}\ncpu: { enableTrustZone: ${enableTrustZone} }"""
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*** Test Cases ***
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Should Handle Separation By State In Secure World
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Create Bus Isolation Machine
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Execute Command cpu0 Step 100
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Register Should Be Equal 3 0x1010
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Register Should Be Equal 4 0x2020
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Register Should Be Equal 5 0x3030
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Register Should Be Equal 6 0x4444
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Register Should Be Equal 7 0x63707507
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Register Should Be Equal 8 0x63707507
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Register Should Be Equal 9 0x1010
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Register Should Be Equal 10 0
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Register Should Be Equal 11 0x3030
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Register Should Be Equal 12 0x0404
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Register Should Be Equal 1 0x63707506
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Register Should Be Equal 2 0x63707506
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Should Handle Separation By State In Nonsecure World
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Create Bus Isolation Machine
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Execute Command cpu0 SecureState false
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Execute Command cpu0 Step 100
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Register Should Be Equal 3 0
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Register Should Be Equal 4 0
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Register Should Be Equal 5 0x3030
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Register Should Be Equal 6 0x4444
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Register Should Be Equal 7 0x63707501
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Register Should Be Equal 8 0x63707501
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Register Should Be Equal 9 0x1010
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Register Should Be Equal 10 0
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Register Should Be Equal 11 0x3030
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Register Should Be Equal 12 0x0404
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Register Should Be Equal 1 0x63707500
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Register Should Be Equal 2 0x63707500
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Should Change Access Conditions At Runtime
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Create Bus Isolation Machine
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# Execute `ldr r0, =0x10000` and `ldr r3, [r0]` (the first iteration of the first read)
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Execute Command cpu0 Step 2
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Register Should Be Equal 3 0x1010 # Read OK because the condition in the repl is "(cpuSecure || !privileged) && initiator == cpu0"
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Register Should Be Equal 4 0 # Not reached yet
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# Now change the condition on the peripheral at 0x10000 to fail
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Execute Command sysbus ChangePeripheralAccessCondition unpriv "initiator == cpu0 && (!cpuSecure || !privileged)"
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# The next instruction is another `ldr r3, [r0]`, which will now see 0 (open bus)
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Execute Command cpu0 Step
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Register Should Be Equal 3 0 # Read 0 because the condition is now "(!cpuSecure || !privileged)" which fails
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Register Should Be Equal 4 0 # Not reached yet
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Should Read Through Privilege Aware Reader
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Create Bus Isolation Machine
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# ↓ raw initiator state which gets passed to the peripheral
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Command Result Should Be Number reader Read 0x10010 0x00 0x72656100
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Command Result Should Be Number reader Read 0x10010 0x01 0x72656101
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Command Result Should Be Number reader Read 0x10010 0xa5 0x72656105
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Command Result Should Be Number reader Read 0x20010 0x02 0x72656102
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# Now we'll read some peripherals that have various conditions.
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Command Result Should Be Number reader Read 0x10008 0x00 0x3030 # no condition
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Command Result Should Be Number reader Read 0x10008 0x01 0x3030 # no condition
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# condition: privileged and condition: !privileged, here decoded according to CortexM.StateBits,
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# so it should only differ based on bit[0] of state
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Command Result Should Be Number reader Read 0x1000c 0x00 0x0404
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Command Result Should Be Number reader Read 0x1000c 0x01 0x4444
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Command Result Should Be Number reader Read 0x1000c 0x02 0x0404
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Command Result Should Be Number reader Read 0x1000c 0x03 0x4444
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# condition: cpuSecure && privileged && initiator == cpu0, so we will not be able to read it even if the correct state
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# (0x3) is specified
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Command Result Should Be Number reader Read 0x10004 0x00 0
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Command Result Should Be Number reader Read 0x10004 0x03 0
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Should Handle Readers And Log Context Access
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Create Bus Isolation Machine
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Create Log Tester 1
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Command Result Should Be Number reader Read 0x10010 0x00 0x72656100
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Wait For Log Entry priv_aware: Read from context
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Command Result Should Be Number reader2 Read 0x10010 0x00 0
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Wait For Log Entry priv_aware: No context
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Command Result Should Be Number reader3 Read 0x10010 0x00 0
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Wait For Log Entry sysbus: ReadDoubleWord from non existing peripheral at 0x10010
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Should Not Read Directly From Sysbus
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Create Bus Isolation Machine
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# Because priv_aware has a requirement that the initiator is cpu0 or reader, this will not work to access it
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Command Result Should Be Number sysbus ReadDoubleWord 0x10010 0
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# Because priv2_priv and priv2_unpriv have state requirements, this will not work to access either of them
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Command Result Should Be Number sysbus ReadDoubleWord 0x1000c 0
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# Because priv requires that the initiator is cpu0 in a specific state, this will not work either
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Command Result Should Be Number sysbus ReadDoubleWord 0x10004 0
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Test Unsupported Condition Without Initiator
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Create Bus Isolation Machine
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Register With Condition And Expect Error
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... !invalid
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... Provided condition is unsupported by ${POSSIBLE_INITIATORS_STRING}: invalid; supported conditions: 'privileged', 'cpuSecure', 'attributionSecure'
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Test Unsupported Condition With Initiator
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Create Bus Isolation Machine
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Register With Condition And Expect Error
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... invalid && initiator == cpu0
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... Provided condition is unsupported by ${CPU0_INITIATOR_STRING}: invalid; supported conditions: 'privileged', 'cpuSecure', 'attributionSecure'
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Test Condition With Initiator Not Supporting States
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Create Bus Isolation Machine
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Register With Condition And Expect Error
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... cpuSecure && initiator == reader2 && !privileged
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... Conditions provided (cpuSecure && !privileged) but the initiator 'reader2' doesn't implement IPeripheralWithTransactionState or has no state bits
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Test Conditions With Unregistered Initiator
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Execute Command mach create
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Register With Condition And Expect Error
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... cpuSecure && initiator == reader
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... Invalid initiator: reader
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Test Unregistered Initiator
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Execute Command mach create
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Register With Condition And Expect Error
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... initiator == reader
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... Invalid initiator: reader
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Test Condition With No Initiators In The Machine
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Execute Command mach create
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Register With Condition And Expect Error
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... !privileged
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... Conditions provided (!privileged) but there are no peripherals implementing IPeripheralWithTransactionState or they have no common state bits
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Test Conflicting Conditions
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Create Bus Isolation Machine
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Register With Condition And Expect Error
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... cpuSecure && !cpuSecure
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... Conditions conflict detected for ${POSSIBLE_INITIATORS_STRING}: cpuSecure
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Should Access VTOR in Secure State
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Create Simple M33 Machine
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Execute Command sysbus.mem WriteDoubleWord 0x0 0x10100
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Execute Command sysbus.mem WriteDoubleWord 0x4 0x10234
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Execute Command sysbus.cpu VectorTableOffset 0x10000
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Start Emulation
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PC Should Be Equal 0x10234
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Register Should Be Equal SP 0x10100
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Should Access VTOR Without TrustZone Enabled
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Create Simple M33 Machine enableTrustZone=false
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Execute Command sysbus.mem WriteDoubleWord 0x0 0x10100
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Execute Command sysbus.mem WriteDoubleWord 0x4 0x10234
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Execute Command sysbus.cpu VectorTableOffset 0x10000
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Start Emulation
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PC Should Be Equal 0x10234
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Register Should Be Equal SP 0x10100
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