仿真平台内核初版 -tlib库 包含<sparc arm riscv powerPC>
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liuwb
145
tests/unit-tests/arm-cortex-m-trustzone.robot
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145
tests/unit-tests/arm-cortex-m-trustzone.robot
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*** Variables ***
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${SRAM_BASE_S} 0x20020000
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${SRAM_BASE_NS} 0x30020000
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${SRAM_CPU0_CODE_S} 0x20021000
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${SRAM_CPU0_STACKTOP_S} 0x20021F80
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${SRAM_CPU0_CODE_NS} 0x30023000
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${SRAM_CPU0_STACKTOP_NS} 0x30023F80
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${UART_BASE_S} 0x40208000
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${UART_BASE_NS} 0x50208000
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${CPU} sysbus.cpu0
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${REPL_STRING} SEPARATOR=\n
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... """
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... sram: Memory.ArrayMemory @ {
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... ${SPACE*8}sysbus ${SRAM_BASE_S};
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... ${SPACE*8}sysbus ${SRAM_BASE_NS}
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... ${SPACE*4}}
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... ${SPACE*4}size: 0x80000
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...
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... nvic0: IRQControllers.NVIC @ {
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... ${SPACE*8}sysbus new Bus.BusPointRegistration { address: 0xE000E000; cpu: cpu0 };
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... ${SPACE*8}sysbus new Bus.BusMultiRegistration { address: 0xE002E000; size: 0x1000; region: "NonSecure"; cpu: cpu0 }
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... ${SPACE*4}}
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... ${SPACE*4}-> cpu0@0
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...
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... cpu0: CPU.CortexM @ sysbus
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... ${SPACE*4}cpuType: "cortex-m33"
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... ${SPACE*4}nvic: nvic0
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... ${SPACE*4}cpuId: 0
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... ${SPACE*4}enableTrustZone: true
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...
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... uart: UART.TrivialUart @ {
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... ${SPACE*4}sysbus ${UART_BASE_S};
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... ${SPACE*4}sysbus ${UART_BASE_NS}
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... }
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... """
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${TRUSTZONE_TEST_S} SEPARATOR=\n
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... ldr sp, =${SRAM_CPU0_STACKTOP_S}
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... adr r3, cpu0_strings
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... ldr r4, =${UART_BASE_S}
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... ldr r0, =${SRAM_CPU0_CODE_NS}
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... ldr r11, [r0, #4] // r11 = initial PC from nonsecure vector table
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... bic r11, #1 // blxns instr expects bit[0] clear for branch to nonsecure
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... bl str_print // hello
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... // configure SAU region 0
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... // start=(SRAM_CPU0_CODE_NS) limit=(SRAM_CPU0_STACKTOP_NS) nonsecure
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... ldr r9, =0xe000edd0
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... mov r10, #0
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... str r10, [r9, #0x8] // SAU->RNR = 0
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... str r0, [r9, #0xc] // SAU->RBAR = (SRAM_CPU0_CODE_NS)
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... ldr r10, =${SRAM_CPU0_STACKTOP_NS}+0x1
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... str r10, [r9, #0x10] // SAU->RLAR = (SRAM_CPU0_STACKTOP_NS) | (nonsecure)
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... // configure SAU region 1
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... // start=0x50000000 limit=0x5fffffe0 nonsecure
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... mov r10, #1
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... str r10, [r9, #0x8] // SAU->RNR = 1
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... ldr r10, =0x50000000
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... str r10, [r9, #0xc] // SAU->RBAR = 0x50000000
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... ldr r10, =0x5fffffe1
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... str r10, [r9, #0x10] // SAU->RLAR = 0x5fffffe0 | (nonsecure)
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... // enable SAU
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... mov r10, #3
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... str r10, [r9] // SAU->CTRL = (enable) | (allns)
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... // set nonsecure vector table ptr
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... ldr r9, =0xe002ed08
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... str r0, [r9] // SCB->VTOR_NS = (SRAM_CPU0_CODE_NS)
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... // initialize MSP_NS
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... ldr r10, [r0]
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... msr msp_ns, r10
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... // synchronization barrier
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... dsb
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... isb
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... // ready to call nonsecure
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... blxns r11 // test 1
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... 1: wfi
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... b 1b
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... cpu0_strings:
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... .asciz "Hello from cpu0 secure\\n"
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...
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... str_print:
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... push {r7, lr}
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... 1: ldrb r7, [r3] // iterate chars in string
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... add r3, r3, #1
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... cbz r7, 2f
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... str r7, [r4] // write char
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... b 1b
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... 2: pop {r7, pc}
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${TRUSTZONE_TEST_NS} SEPARATOR=\n
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... // nonsecure vector table
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... .word ${SRAM_CPU0_STACKTOP_NS} // initial SP
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... .word ${SRAM_CPU0_CODE_NS}+0x201 // initial PC = nonsecure_app
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... .fill (9), 4, 0 // unused vectors
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... .word ${SRAM_CPU0_CODE_NS}+0x201+nonsecure_svc_handler-nonsecure_app
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... .align 8 // hack to get org to ${SRAM_CPU0_CODE_NS}+0x100
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... nonsecure_str_ptr:
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... .word nonsecure_hello
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... .word svc_hello
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... nonsecure_hello:
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... .asciz "Hello from cpu0 nonsecure\\n"
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... svc_hello:
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... .asciz "Hello from cpu0 svc\\n"
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... .align 9 // hack to get org to ${SRAM_CPU0_CODE_NS}+0x200
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... nonsecure_app:
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... push {r0, r4, r5, lr}
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... ldr r4, =${UART_BASE_NS}
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... ldr r5, =nonsecure_hello
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... bl nonsecure_print
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... svc #0
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... 1: wfi
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... b 1b
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... nonsecure_svc_handler:
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... ldr r4, =${UART_BASE_NS}
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... ldr r5, =svc_hello
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... bl nonsecure_print
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... 1: wfi
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... b 1b
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... nonsecure_print:
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... push {r3, r7, lr}
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... mov r3, r5
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... 1: ldrb r7, [r3] // iterate chars in string
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... add r3, r3, #1
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... cbz r7, 2f
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... str r7, [r4] // write char
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... b 1b
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... 2: str r3, [r5]
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... pop {r3, r7, pc}
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*** Keywords ***
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Create Machine
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Execute Command mach create
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Execute Command machine LoadPlatformDescriptionFromString ${REPL_STRING}
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*** Test Cases ***
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Should Print Hello From Both States
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Create Machine
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Execute Command showAnalyzer sysbus.uart
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Create Terminal Tester sysbus.uart
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Execute Command ${CPU} PC ${SRAM_CPU0_CODE_S}
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Execute Command ${CPU} AssembleBlock `${CPU} PC` """${TRUSTZONE_TEST_S}"""
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Execute Command ${CPU} AssembleBlock ${SRAM_CPU0_CODE_NS} """${TRUSTZONE_TEST_NS}"""
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Wait For Line On Uart Hello from cpu0 secure
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Wait For Line On Uart Hello from cpu0 nonsecure
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Wait For Line On Uart Hello from cpu0 svc
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