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仿真平台内核初版 -tlib库 包含<sparc arm riscv powerPC>

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liuwb
2026-02-07 20:43:43 +08:00
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tests/platforms/SiFive-FE310/SiFive-FE310.robot Normal file
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*** Variables ***
${CPU} sysbus.cpu
${UART} sysbus.uart0
${URI} @https://dl.antmicro.com/projects/renode
${SCRIPT} ${CURDIR}/../../../scripts/single-node/sifive_fe310.resc
*** Test Cases ***
Should Run Shell
[Documentation] Runs Zephyr's 'shell' sample on SiFive Freedom E310 platform.
[Tags] zephyr uart interrupts
Execute Command $bin = ${URI}/zephyr-fe310-shell.elf-s_323068-cf87169150ecdb30ad5a14c87ae209c53dd3eca2
Execute Script ${SCRIPT}
Create Terminal Tester ${UART} endLineOption=TreatCarriageReturnAsEndLine
Start Emulation
Wait For Prompt On Uart shell>
# this sleep here is to prevent against writing to soon on uart - it can happen under high stress of the host CPU - when an uart driver is not initalized which leads to irq-loop
Sleep 3
Write Line To Uart select sample_module
Wait For Prompt On Uart sample_module>
Write Line To Uart ping
Wait For Line On Uart pong