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仿真平台内核初版 -tlib库 包含<sparc arm riscv powerPC>

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liuwb
2026-02-07 20:43:43 +08:00
parent de61f9e2b0
commit b3117648be
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tests/peripherals/CLIC/CLIC-indirect-csr.robot Normal file
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*** Variables ***
${UART} sysbus.uart
*** Keywords ***
Create Machine
Execute Command mach create
Execute Command using sysbus
Execute Command machine LoadPlatformDescription @tests/peripherals/CLIC/CLIC-test-platform.repl
*** Test Cases ***
Registers Should Be Accessible Through Indirect CSRs
Create Machine
Execute Command sysbus LoadELF @https://dl.antmicro.com/projects/renode/clic/clic_indirect_csr-01.elf-s_6164-08ee198d10e7c86b0cf15f54a4c90cfa2f6cd5f8
Create Terminal Tester ${UART}
Wait For Line On Uart OK