仿真平台内核初版 -tlib库 包含<sparc arm riscv powerPC>

tests/network-server/litex_vexriscv.repl

@@ -0,0 +1,43 @@
+
+rom: Memory.MappedMemory @ { sysbus 0x0 }
+    size: 0x10000
+
+sram: Memory.MappedMemory @ { sysbus 0x1000000 }
+    size: 0x8000
+
+spiflash: Memory.MappedMemory @ { sysbus 0x20000000 }
+    size: 0x1000000
+
+main_ram: Memory.MappedMemory @ { sysbus 0x40000000 }
+    size: 0x10000000
+
+cpu: CPU.VexRiscv @ sysbus
+    cpuType: "rv32im_zicsr_zifencei"
+
+ctrl: Miscellaneous.LiteX_SoC_Controller @ { sysbus 0x82000000 }
+
+uart: UART.LiteX_UART @ { sysbus 0x82002000 }
+    -> cpu@0
+
+timer0: Timers.LiteX_Timer @ { sysbus 0x82002800 }
+    -> cpu@1
+    frequency: 100000000
+
+sysbus:
+    init add:
+        SilenceRange <2181050368 0x200> # ddrphy
+
+sysbus:
+    init add:
+        SilenceRange <2181052416 0x200> # sdram
+
+ethmac: Network.LiteX_Ethernet @ {
+    sysbus 0x82006000;
+    sysbus new Bus.BusMultiRegistration { address: 0xb0000000; size: 0x2000; region: "buffer" };
+    sysbus new Bus.BusMultiRegistration { address: 0x82005800; size: 0x800; region: "phy" }
+}
+    -> cpu@2
+
+
+ethphy: Network.EthernetPhysicalLayer @ ethmac 0
+    VendorSpecific1: 0x4400 // MDIO status: 100Mbps + link up