仿真平台内核初版 -tlib库包含<sparc arm riscv powerPC>

2026-02-07 20:43:43 +08:00
parent de61f9e2b0
commit b3117648be
9748 changed files with 4309137 additions and 0 deletions
--- a/tests/network-server/NetworkServer.robot
+++ b/tests/network-server/NetworkServer.robot
@@ -0,0 +1,35 @@
+*** Test Cases ***
+Download File Over TFTP
+    Execute Command             using sysbus
+    Execute Command             mach create "litex-vexriscv"
+    Execute Command             machine LoadPlatformDescription "${CURDIR}/litex_vexriscv.repl"
+    Execute Command             sysbus LoadBinary @https://dl.antmicro.com/projects/renode/bios.bin-s_27076-9b28166a445deb24d5d3547871ae0de8365ba4d0 0x0
+    Execute Command             cpu PC 0x0
+
+    Execute Command             emulation CreateSwitch "switch"
+    Execute Command             connector Connect ethmac switch
+
+    Execute Command             emulation CreateNetworkServer "server" "192.168.100.100"
+    Execute Command             connector Connect server switch
+    Execute Command             server StartTFTP 6069
+    Execute Command             server.tftp ServeFile @https://dl.antmicro.com/projects/renode/litex_vexriscv-micropython.bin-s_218608-db594ec6a9a75d77d2475afd714b6c28fb6e6498 "boot.bin"
+
+    Create Terminal Tester      sysbus.uart
+    Execute Command             showAnalyzer sysbus.uart
+    Start Emulation
+
+    Wait For Line On Uart      Press Q or ESC to abort boot completely.
+    # send Q
+    Send Key To Uart           0x51 
+    
+    Wait For Prompt On Uart    litex> 
+    Write Line To Uart         netboot
+
+    Wait For Line On Uart      Downloaded 218608 bytes from boot.bin over TFTP to 0x40000000
+    Wait For Line On Uart      MicroPython v1.9.4-1431
+
+    Wait For Prompt On Uart    >>>
+
+    Write Line To Uart         2 + 3
+    Wait For Line On Uart      5
+
--- a/tests/network-server/litex_vexriscv.repl
+++ b/tests/network-server/litex_vexriscv.repl
@@ -0,0 +1,43 @@
+
+rom: Memory.MappedMemory @ { sysbus 0x0 }
+    size: 0x10000
+
+sram: Memory.MappedMemory @ { sysbus 0x1000000 }
+    size: 0x8000
+
+spiflash: Memory.MappedMemory @ { sysbus 0x20000000 }
+    size: 0x1000000
+
+main_ram: Memory.MappedMemory @ { sysbus 0x40000000 }
+    size: 0x10000000
+
+cpu: CPU.VexRiscv @ sysbus
+    cpuType: "rv32im_zicsr_zifencei"
+
+ctrl: Miscellaneous.LiteX_SoC_Controller @ { sysbus 0x82000000 }
+
+uart: UART.LiteX_UART @ { sysbus 0x82002000 }
+    -> cpu@0
+
+timer0: Timers.LiteX_Timer @ { sysbus 0x82002800 }
+    -> cpu@1
+    frequency: 100000000
+
+sysbus:
+    init add:
+        SilenceRange <2181050368 0x200> # ddrphy
+
+sysbus:
+    init add:
+        SilenceRange <2181052416 0x200> # sdram
+
+ethmac: Network.LiteX_Ethernet @ {
+    sysbus 0x82006000;
+    sysbus new Bus.BusMultiRegistration { address: 0xb0000000; size: 0x2000; region: "buffer" };
+    sysbus new Bus.BusMultiRegistration { address: 0x82005800; size: 0x800; region: "phy" }
+}
+    -> cpu@2
+
+
+ethphy: Network.EthernetPhysicalLayer @ ethmac 0
+    VendorSpecific1: 0x4400 // MDIO status: 100Mbps + link up