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仿真平台内核初版 -tlib库 包含<sparc arm riscv powerPC>

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liuwb
2026-02-07 20:43:43 +08:00
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scripts/single-node/verilated_ibex.resc Normal file
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:name: Verilated Ibex
:description: This script runs LiteX BIOS on the verilated Ibex CPU.
$name?="Verilated Ibex"
using sysbus
mach create $name
machine LoadPlatformDescription @platforms/cpus/verilated/verilated_ibex.repl
$bios?=@https://dl.antmicro.com/projects/renode/litex_ibex--bios.bin-s_20712-80d064cf8ab28801b78c0e5a63cac4830016f6c8
$cpuLinux?=@https://dl.antmicro.com/projects/renode/libVcpu_ibex-Linux-x86_64-13112907851.so-s_2251128-ab2dcb1801188d7f934bdeafa93f9c1edc60ad39
$cpuWindows?=@https://dl.antmicro.com/projects/renode/libVcpu_ibex-Windows-x86_64-13112907851.dll-s_3426669-58d11ffc81ea755c1d1151e6b33fc13164bb13d5
$cpuMacOS?=@https://dl.antmicro.com/projects/renode/libVcpu_ibex-macOS-x86_64-13112907851.dylib-s_336528-7677f09f18bfb2937ad2bffdd63ed7d76bb15d56
showAnalyzer sysbus.uart
cpu SimulationFilePathLinux $cpuLinux
cpu SimulationFilePathWindows $cpuWindows
cpu SimulationFilePathMacOS $cpuMacOS
macro reset
"""
sysbus LoadBinary $bios 0x0
sysbus.cpu PC 0x0
"""
runMacro $reset