liuwenbo/simulation_core
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

仿真平台内核初版 -tlib库 包含<sparc arm riscv powerPC>

Browse Source
This commit is contained in:
liuwb
2026-02-07 20:43:43 +08:00
parent de61f9e2b0
commit b3117648be
9748 changed files with 4309137 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

27
scripts/single-node/kendryte_k210.resc Normal file
View File

@@ -0,0 +1,27 @@
using sysbus
mach create
machine LoadPlatformDescription @platforms/cpus/kendryte_k210.repl
$bin?=@https://dl.antmicro.com/projects/renode/kendryte-k210--vmlinux-s_2206416-2c1f2b2c2f2fc0c48a7b12a3f3c65809b81f452e
$ex=`machine SetSerialExecution True`
showAnalyzer uart
sysbus Tag <0x50440000 0x10000> "SYSCTL"
sysbus Tag <0x50440018 0x4> "pll_lock" 0xFFFFFFFF
sysbus Tag <0x5044000C 0x4> "pll1"
sysbus Tag <0x50440008 0x4> "pll0"
sysbus Tag <0x50440020 0x4> "clk_sel0"
sysbus Tag <0x50440028 0x4> "clk_en_cent"
sysbus Tag <0x5044002c 0x4> "clk_en_peri"
# enable uart tx
uart WriteDoubleWord 0x8 0x1
macro reset
"""
sysbus LoadELF $bin
"""
runMacro $reset